From 444ba34fa395ad19cdff8c855876d2425d8402c0 Mon Sep 17 00:00:00 2001 From: IChooseYou Date: Wed, 18 Feb 2026 07:10:13 -0700 Subject: [PATCH] feat: disasm popup, symbol separation, context menu improvements, RVA fixes - Add Fadec x86 disassembler with hover popup for FuncPtr/void Pointer nodes - Separate pointer symbol from address: // prefix, green comment coloring, independent hover/click zones (address triggers popup, symbol is passive) - Fix RVA margin and inline local offset for pointer-expanded vtable children using ptrBase field threaded through composition - Expand multi-select context menu with quick-convert, duplicate, copy address - Remove Edit Value from hex node context menu - Fix heatmap flickering on hex nodes (remove per-byte alternation) - Fix popup repositioning when moving mouse between lines - Truncate disasm popup to 6 lines with ... indicator - Add BUILD_UI_TESTS option to skip widget tests on headless CI - Add test_disasm with 35 test cases for disassembly and hex dump - Add KUSER_SHARED_DATA example .rcx file --- CMakeLists.txt | 102 +- src/compose.cpp | 15 + src/controller.cpp | 120 +- src/core.h | 1 + src/disasm.cpp | 76 + src/disasm.h | 15 + src/editor.cpp | 328 +- src/editor.h | 8 + src/examples/KUSER_SHARED_DATA.rcx | 1316 ++++++++ src/format.cpp | 8 +- src/main.cpp | 102 +- tests/test_disasm.cpp | 470 +++ third_party/fadec/.build.yml | 16 + third_party/fadec/.github/workflows/ci.yml | 51 + third_party/fadec/.gitignore | 1 + third_party/fadec/CMakeLists.txt | 109 + third_party/fadec/LICENSE | 28 + third_party/fadec/README.md | 184 ++ third_party/fadec/decode-test.c | 3248 ++++++++++++++++++++ third_party/fadec/decode.c | 791 +++++ third_party/fadec/encode-test.c | 62 + third_party/fadec/encode-test.inc | 2192 +++++++++++++ third_party/fadec/encode.c | 460 +++ third_party/fadec/encode2-test.c | 64 + third_party/fadec/encode2-test.cc | 64 + third_party/fadec/encode2.c | 345 +++ third_party/fadec/fadec-decode-private.inc | 18 + third_party/fadec/fadec-decode-public.inc | 1888 ++++++++++++ third_party/fadec/fadec-enc.h | 113 + third_party/fadec/fadec-enc2.h | 226 ++ third_party/fadec/fadec.h | 286 ++ third_party/fadec/format.c | 563 ++++ third_party/fadec/instrs.txt | 2596 ++++++++++++++++ third_party/fadec/meson.build | 126 + third_party/fadec/meson_options.txt | 6 + third_party/fadec/parseinstrs.py | 1403 +++++++++ 36 files changed, 17291 insertions(+), 110 deletions(-) create mode 100644 src/disasm.cpp create mode 100644 src/disasm.h create mode 100644 src/examples/KUSER_SHARED_DATA.rcx create mode 100644 tests/test_disasm.cpp create mode 100644 third_party/fadec/.build.yml create mode 100644 third_party/fadec/.github/workflows/ci.yml create mode 100644 third_party/fadec/.gitignore create mode 100644 third_party/fadec/CMakeLists.txt create mode 100644 third_party/fadec/LICENSE create mode 100644 third_party/fadec/README.md create mode 100644 third_party/fadec/decode-test.c create mode 100644 third_party/fadec/decode.c create mode 100644 third_party/fadec/encode-test.c create mode 100644 third_party/fadec/encode-test.inc create mode 100644 third_party/fadec/encode.c create mode 100644 third_party/fadec/encode2-test.c create mode 100644 third_party/fadec/encode2-test.cc create mode 100644 third_party/fadec/encode2.c create mode 100644 third_party/fadec/fadec-decode-private.inc create mode 100644 third_party/fadec/fadec-decode-public.inc create mode 100644 third_party/fadec/fadec-enc.h create mode 100644 third_party/fadec/fadec-enc2.h create mode 100644 third_party/fadec/fadec.h create mode 100644 third_party/fadec/format.c create mode 100644 third_party/fadec/instrs.txt create mode 100644 third_party/fadec/meson.build create mode 100644 third_party/fadec/meson_options.txt create mode 100644 third_party/fadec/parseinstrs.py diff --git a/CMakeLists.txt b/CMakeLists.txt index 89eec2e..6d79be6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,8 +1,9 @@ cmake_minimum_required(VERSION 3.20) -project(Reclass VERSION 0.1 LANGUAGES CXX) +project(Reclass VERSION 0.1 LANGUAGES C CXX) set(CMAKE_CXX_STANDARD 17) set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_C_STANDARD 11) set(CMAKE_AUTOMOC ON) set(CMAKE_AUTORCC ON) set(CMAKE_AUTOUIC ON) @@ -72,10 +73,14 @@ add_executable(Reclass src/titlebar.cpp src/mcp/mcp_bridge.h src/mcp/mcp_bridge.cpp + src/disasm.h + src/disasm.cpp + third_party/fadec/decode.c + third_party/fadec/format.c $<$:src/app.rc> ) -target_include_directories(Reclass PRIVATE src) +target_include_directories(Reclass PRIVATE src third_party/fadec) target_link_libraries(Reclass PRIVATE ${QT}::Widgets @@ -135,7 +140,7 @@ foreach(_f \"${CMAKE_SOURCE_DIR}/src/generator.cpp\" \"${CMAKE_SOURCE_DIR}/src/main.cpp\") file(READ \${_f} _content) - file(APPEND \${_out} \${_content}) + file(APPEND \${_out} \"\${_content}\") file(APPEND \${_out} \"\\n\") endforeach() message(STATUS \"Combined sources -> \${_out}\") @@ -152,6 +157,11 @@ if(BUILD_TESTING) find_package(${QT} REQUIRED COMPONENTS Test) enable_testing() + # Disasm/Fadec sources needed by any test that links editor.cpp + set(DISASM_SRCS src/disasm.cpp third_party/fadec/decode.c third_party/fadec/format.c) + + # ── Headless tests (Qt::Core only — safe for CI without a display) ── + add_executable(test_core tests/test_core.cpp src/format.cpp src/compose.cpp) target_include_directories(test_core PRIVATE src) target_link_libraries(test_core PRIVATE ${QT}::Core ${QT}::Test) @@ -167,7 +177,6 @@ if(BUILD_TESTING) target_link_libraries(test_compose PRIVATE ${QT}::Core ${QT}::Test) add_test(NAME test_compose COMMAND test_compose) - add_executable(test_provider tests/test_provider.cpp) target_include_directories(test_provider PRIVATE src) target_link_libraries(test_provider PRIVATE ${QT}::Core ${QT}::Test) @@ -178,12 +187,47 @@ if(BUILD_TESTING) target_link_libraries(test_command_row PRIVATE ${QT}::Core ${QT}::Test) add_test(NAME test_command_row COMMAND test_command_row) + add_executable(test_generator tests/test_generator.cpp + src/generator.cpp src/compose.cpp src/format.cpp) + target_include_directories(test_generator PRIVATE src) + target_link_libraries(test_generator PRIVATE ${QT}::Core ${QT}::Test) + add_test(NAME test_generator COMMAND test_generator) + + add_executable(test_import_xml tests/test_import_xml.cpp + src/import_reclass_xml.cpp src/format.cpp src/compose.cpp) + target_include_directories(test_import_xml PRIVATE src) + target_link_libraries(test_import_xml PRIVATE ${QT}::Core ${QT}::Test) + add_test(NAME test_import_xml COMMAND test_import_xml) + + add_executable(test_import_source tests/test_import_source.cpp + src/import_source.cpp src/format.cpp src/compose.cpp) + target_include_directories(test_import_source PRIVATE src) + target_link_libraries(test_import_source PRIVATE ${QT}::Core ${QT}::Test) + add_test(NAME test_import_source COMMAND test_import_source) + + add_executable(test_export_xml tests/test_export_xml.cpp + src/export_reclass_xml.cpp src/import_reclass_xml.cpp src/format.cpp src/compose.cpp) + target_include_directories(test_export_xml PRIVATE src) + target_link_libraries(test_export_xml PRIVATE ${QT}::Core ${QT}::Test) + add_test(NAME test_export_xml COMMAND test_export_xml) + + add_executable(test_disasm tests/test_disasm.cpp + src/disasm.cpp src/compose.cpp src/format.cpp + third_party/fadec/decode.c third_party/fadec/format.c) + target_include_directories(test_disasm PRIVATE src third_party/fadec) + target_link_libraries(test_disasm PRIVATE ${QT}::Core ${QT}::Test) + add_test(NAME test_disasm COMMAND test_disasm) + + # ── UI tests (require Qt::Widgets / QScintilla / display — skip on headless CI) ── + option(BUILD_UI_TESTS "Build tests that require a display (Qt Widgets)" ON) + if(BUILD_UI_TESTS) + add_executable(test_controller tests/test_controller.cpp src/editor.cpp src/compose.cpp src/format.cpp src/controller.cpp src/processpicker.cpp src/processpicker.ui src/providerregistry.cpp src/typeselectorpopup.cpp - src/themes/theme.cpp src/themes/thememanager.cpp) - target_include_directories(test_controller PRIVATE src) + src/themes/theme.cpp src/themes/thememanager.cpp ${DISASM_SRCS}) + target_include_directories(test_controller PRIVATE src third_party/fadec) target_link_libraries(test_controller PRIVATE ${QT}::Widgets ${QT}::PrintSupport ${QT}::Concurrent ${QT}::Test QScintilla::QScintilla) @@ -196,8 +240,8 @@ if(BUILD_TESTING) src/editor.cpp src/compose.cpp src/format.cpp src/controller.cpp src/processpicker.cpp src/processpicker.ui src/providerregistry.cpp src/typeselectorpopup.cpp - src/themes/theme.cpp src/themes/thememanager.cpp) - target_include_directories(test_validation PRIVATE src) + src/themes/theme.cpp src/themes/thememanager.cpp ${DISASM_SRCS}) + target_include_directories(test_validation PRIVATE src third_party/fadec) target_link_libraries(test_validation PRIVATE ${QT}::Widgets ${QT}::PrintSupport ${QT}::Concurrent ${QT}::Test QScintilla::QScintilla) @@ -206,18 +250,12 @@ if(BUILD_TESTING) endif() add_test(NAME test_validation COMMAND test_validation) - add_executable(test_generator tests/test_generator.cpp - src/generator.cpp src/compose.cpp src/format.cpp) - target_include_directories(test_generator PRIVATE src) - target_link_libraries(test_generator PRIVATE ${QT}::Core ${QT}::Test) - add_test(NAME test_generator COMMAND test_generator) - add_executable(test_context_menu tests/test_context_menu.cpp src/editor.cpp src/compose.cpp src/format.cpp src/controller.cpp src/processpicker.cpp src/processpicker.ui src/providerregistry.cpp src/typeselectorpopup.cpp - src/themes/theme.cpp src/themes/thememanager.cpp) - target_include_directories(test_context_menu PRIVATE src) + src/themes/theme.cpp src/themes/thememanager.cpp ${DISASM_SRCS}) + target_include_directories(test_context_menu PRIVATE src third_party/fadec) target_link_libraries(test_context_menu PRIVATE ${QT}::Widgets ${QT}::PrintSupport ${QT}::Concurrent ${QT}::Test QScintilla::QScintilla) @@ -229,8 +267,8 @@ if(BUILD_TESTING) add_executable(test_editor tests/test_editor.cpp src/editor.cpp src/compose.cpp src/format.cpp src/providerregistry.cpp - src/themes/theme.cpp src/themes/thememanager.cpp) - target_include_directories(test_editor PRIVATE src) + src/themes/theme.cpp src/themes/thememanager.cpp ${DISASM_SRCS}) + target_include_directories(test_editor PRIVATE src third_party/fadec) target_link_libraries(test_editor PRIVATE ${QT}::Widgets ${QT}::PrintSupport ${QT}::Test QScintilla::QScintilla) @@ -248,8 +286,8 @@ if(BUILD_TESTING) src/generator.cpp src/compose.cpp src/format.cpp src/controller.cpp src/editor.cpp src/processpicker.cpp src/processpicker.ui src/providerregistry.cpp src/typeselectorpopup.cpp - src/themes/theme.cpp src/themes/thememanager.cpp) - target_include_directories(test_new_features PRIVATE src) + src/themes/theme.cpp src/themes/thememanager.cpp ${DISASM_SRCS}) + target_include_directories(test_new_features PRIVATE src third_party/fadec) target_link_libraries(test_new_features PRIVATE ${QT}::Widgets ${QT}::PrintSupport ${QT}::Concurrent ${QT}::Test QScintilla::QScintilla) @@ -262,8 +300,8 @@ if(BUILD_TESTING) src/editor.cpp src/compose.cpp src/format.cpp src/controller.cpp src/processpicker.cpp src/processpicker.ui src/providerregistry.cpp src/typeselectorpopup.cpp - src/themes/theme.cpp src/themes/thememanager.cpp) - target_include_directories(test_type_selector PRIVATE src) + src/themes/theme.cpp src/themes/thememanager.cpp ${DISASM_SRCS}) + target_include_directories(test_type_selector PRIVATE src third_party/fadec) target_link_libraries(test_type_selector PRIVATE ${QT}::Widgets ${QT}::PrintSupport ${QT}::Concurrent ${QT}::Test QScintilla::QScintilla) @@ -284,24 +322,6 @@ if(BUILD_TESTING) target_link_libraries(test_options_dialog PRIVATE ${QT}::Widgets ${QT}::Test) add_test(NAME test_options_dialog COMMAND test_options_dialog) - add_executable(test_import_xml tests/test_import_xml.cpp - src/import_reclass_xml.cpp src/format.cpp src/compose.cpp) - target_include_directories(test_import_xml PRIVATE src) - target_link_libraries(test_import_xml PRIVATE ${QT}::Core ${QT}::Test) - add_test(NAME test_import_xml COMMAND test_import_xml) - - add_executable(test_import_source tests/test_import_source.cpp - src/import_source.cpp src/format.cpp src/compose.cpp) - target_include_directories(test_import_source PRIVATE src) - target_link_libraries(test_import_source PRIVATE ${QT}::Core ${QT}::Test) - add_test(NAME test_import_source COMMAND test_import_source) - - add_executable(test_export_xml tests/test_export_xml.cpp - src/export_reclass_xml.cpp src/import_reclass_xml.cpp src/format.cpp src/compose.cpp) - target_include_directories(test_export_xml PRIVATE src) - target_link_libraries(test_export_xml PRIVATE ${QT}::Core ${QT}::Test) - add_test(NAME test_export_xml COMMAND test_export_xml) - if(WIN32) add_executable(test_windbg_provider tests/test_windbg_provider.cpp plugins/WinDbgMemory/WinDbgMemoryPlugin.cpp) @@ -331,6 +351,8 @@ if(BUILD_TESTING) COMMENT "Deploying Qt runtime DLLs for tests..." ) endif() + + endif() # BUILD_UI_TESTS endif() add_subdirectory(plugins/ProcessMemory) if(WIN32) diff --git a/src/compose.cpp b/src/compose.cpp index d97078c..9955ba5 100644 --- a/src/compose.cpp +++ b/src/compose.cpp @@ -22,6 +22,7 @@ struct ComposeState { int nameW = kColName; // global name column width (fallback) int offsetHexDigits = 8; // hex digit tier for offset margin bool baseEmitted = false; // only first root struct shows base address + uint64_t currentPtrBase = 0; // absolute addr of current pointer expansion target // Precomputed for O(1) lookups QHash> childMap; @@ -141,6 +142,7 @@ void composeLeaf(ComposeState& state, const NodeTree& tree, lm.nodeKind = node.kind; lm.offsetText = fmt::fmtOffsetMargin(tree.baseAddress + absAddr, isCont, state.offsetHexDigits); lm.offsetAddr = tree.baseAddress + absAddr; + lm.ptrBase = state.currentPtrBase; lm.markerMask = computeMarkers(node, prov, absAddr, isCont, depth); lm.foldLevel = computeFoldLevel(depth, false); lm.effectiveTypeW = typeW; @@ -187,6 +189,7 @@ void composeParent(ComposeState& state, const NodeTree& tree, lm.lineKind = LineKind::Field; lm.offsetText = fmt::fmtOffsetMargin(tree.baseAddress + absAddr, false, state.offsetHexDigits); lm.offsetAddr = tree.baseAddress + absAddr; + lm.ptrBase = state.currentPtrBase; lm.nodeKind = node.kind; lm.markerMask = (1u << M_CYCLE) | (1u << M_ERR); lm.foldLevel = computeFoldLevel(depth, false); @@ -205,6 +208,7 @@ void composeParent(ComposeState& state, const NodeTree& tree, lm.lineKind = LineKind::ArrayElementSeparator; lm.offsetText = fmt::fmtOffsetMargin(tree.baseAddress + absAddr, false, state.offsetHexDigits); lm.offsetAddr = tree.baseAddress + absAddr; + lm.ptrBase = state.currentPtrBase; lm.nodeKind = node.kind; lm.foldLevel = computeFoldLevel(depth, false); lm.markerMask = 0; @@ -234,6 +238,7 @@ void composeParent(ComposeState& state, const NodeTree& tree, lm.lineKind = LineKind::Header; lm.offsetText = fmt::fmtOffsetMargin(tree.baseAddress + absAddr, false, state.offsetHexDigits); lm.offsetAddr = tree.baseAddress + absAddr; + lm.ptrBase = state.currentPtrBase; lm.nodeKind = node.kind; lm.isRootHeader = false; lm.foldHead = true; @@ -297,6 +302,7 @@ void composeParent(ComposeState& state, const NodeTree& tree, lm.isArrayElement = true; lm.offsetText = fmt::fmtOffsetMargin(tree.baseAddress + elemAddr, false, state.offsetHexDigits); lm.offsetAddr = tree.baseAddress + elemAddr; + lm.ptrBase = state.currentPtrBase; lm.markerMask = computeMarkers(elem, prov, elemAddr, false, childDepth); lm.foldLevel = computeFoldLevel(childDepth, false); lm.effectiveTypeW = eTW; @@ -350,6 +356,7 @@ void composeParent(ComposeState& state, const NodeTree& tree, tree.baseAddress + absAddr + child.offset, false, state.offsetHexDigits); lm.offsetAddr = tree.baseAddress + absAddr + child.offset; + lm.ptrBase = state.currentPtrBase; lm.nodeKind = child.kind; lm.foldHead = true; lm.foldCollapsed = true; @@ -394,6 +401,7 @@ void composeParent(ComposeState& state, const NodeTree& tree, int sz = tree.structSpan(node.id, &state.childMap); lm.offsetText = fmt::fmtOffsetMargin(tree.baseAddress + absAddr + sz, false, state.offsetHexDigits); lm.offsetAddr = tree.baseAddress + absAddr + sz; + lm.ptrBase = state.currentPtrBase; state.emitLine(fmt::fmtStructFooter(node, depth, sz), lm); } @@ -439,6 +447,7 @@ void composeNode(ComposeState& state, const NodeTree& tree, lm.lineKind = effectiveCollapsed ? LineKind::Field : LineKind::Header; lm.offsetText = fmt::fmtOffsetMargin(tree.baseAddress + absAddr, false, state.offsetHexDigits); lm.offsetAddr = tree.baseAddress + absAddr; + lm.ptrBase = state.currentPtrBase; lm.nodeKind = node.kind; lm.foldHead = true; lm.foldCollapsed = effectiveCollapsed; @@ -481,6 +490,9 @@ void composeNode(ComposeState& state, const NodeTree& tree, if (!ptrReadable) pBase = (uint64_t)0 - tree.baseAddress; + uint64_t savedPtrBase = state.currentPtrBase; + state.currentPtrBase = tree.baseAddress + pBase; + if (hasMaterialized) { // Render materialized children at the pointer target address. // These are real tree nodes with independent state — use rootId @@ -519,6 +531,8 @@ void composeNode(ComposeState& state, const NodeTree& tree, } } + state.currentPtrBase = savedPtrBase; + // Footer for pointer fold { LineMeta lm; @@ -668,6 +682,7 @@ ComposeResult compose(const NodeTree& tree, const Provider& prov, uint64_t viewR lm.foldHead = false; lm.offsetText = fmt::fmtOffsetMargin(tree.baseAddress, false, state.offsetHexDigits); lm.offsetAddr = tree.baseAddress; + lm.ptrBase = state.currentPtrBase; lm.markerMask = 0; lm.effectiveTypeW = state.typeW; lm.effectiveNameW = state.nameW; diff --git a/src/controller.cpp b/src/controller.cpp index 590e141..5dfed50 100644 --- a/src/controller.cpp +++ b/src/controller.cpp @@ -654,9 +654,15 @@ void RcxController::refresh() { const Node& node = m_doc->tree.nodes[lm.nodeIdx]; // Skip containers — they don't have scalar values if (node.kind == NodeKind::Struct || node.kind == NodeKind::Array) continue; + // Skip FuncPtr nodes — vtable entries don't change; tracking them + // causes false heatmap and popup fighting with the disasm popup. + if (isFuncPtr(node.kind)) continue; - int64_t nodeOff = m_doc->tree.computeOffset(lm.nodeIdx); - uint64_t addr = static_cast(nodeOff); // provider-relative + // Use the absolute address from compose (correct for pointer-expanded nodes) + // and convert to provider-relative by subtracting the base address. + uint64_t addr = lm.offsetAddr >= m_doc->tree.baseAddress + ? lm.offsetAddr - m_doc->tree.baseAddress + : static_cast(m_doc->tree.computeOffset(lm.nodeIdx)); int sz = node.byteSize(); if (sz <= 0 || !prov->isReadable(addr, sz)) continue; @@ -690,9 +696,18 @@ void RcxController::refresh() { } } + // Resolve providers for disasm popup: + // - snapProv: snapshot or real — for reading pointer values within the tree + // - realProv: always the real process provider — for reading code at arbitrary addresses + const Provider* snapProv = m_snapshotProv + ? static_cast(m_snapshotProv.get()) + : (m_doc->provider ? m_doc->provider.get() : nullptr); + const Provider* realProv = m_doc->provider ? m_doc->provider.get() : nullptr; + for (auto* editor : m_editors) { editor->setCustomTypeNames(customTypes); editor->setValueHistoryRef(&m_valueHistory); + editor->setProviderRef(snapProv, realProv, &m_doc->tree); ViewState vs = editor->saveViewState(); editor->applyDocument(m_lastResult); editor->restoreViewState(vs); @@ -1160,35 +1175,111 @@ void RcxController::showContextMenu(RcxEditor* editor, int line, int nodeIdx, } } - // Multi-select batch actions at top + // Multi-select batch actions if (hasNode && m_selIds.size() > 1) { QMenu menu; int count = m_selIds.size(); QSet ids = m_selIds; - menu.addAction(icon("trash.svg"), QString("Delete %1 nodes").arg(count), [this, ids]() { + + // Helper: collect indices from selected ids + auto collectIndices = [this, &ids]() { QVector indices; for (uint64_t id : ids) { int idx = m_doc->tree.indexOfId(id); if (idx >= 0) indices.append(idx); } - batchRemoveNodes(indices); - }); + return indices; + }; + + // Quick-convert shortcuts when all selected nodes share the same kind + NodeKind commonKind = NodeKind::Hex64; + bool allSame = true; + { + bool first = true; + for (uint64_t id : ids) { + int idx = m_doc->tree.indexOfId(id); + if (idx < 0) continue; + if (first) { commonKind = m_doc->tree.nodes[idx].kind; first = false; } + else if (m_doc->tree.nodes[idx].kind != commonKind) { allSame = false; break; } + } + } + bool addedQuickConvert = false; + if (allSame) { + if (commonKind == NodeKind::Hex64) { + menu.addAction("Change to uint64_t", [this, collectIndices]() { + batchChangeKind(collectIndices(), NodeKind::UInt64); }); + menu.addAction("Change to uint32_t", [this, collectIndices]() { + batchChangeKind(collectIndices(), NodeKind::UInt32); }); + addedQuickConvert = true; + } else if (commonKind == NodeKind::Hex32) { + menu.addAction("Change to uint32_t", [this, collectIndices]() { + batchChangeKind(collectIndices(), NodeKind::UInt32); }); + addedQuickConvert = true; + } else if (commonKind == NodeKind::Hex16) { + menu.addAction("Change to int16_t", [this, collectIndices]() { + batchChangeKind(collectIndices(), NodeKind::Int16); }); + addedQuickConvert = true; + } + if (commonKind == NodeKind::Hex64 || commonKind == NodeKind::Pointer64) { + menu.addAction("Change to fnptr64", [this, collectIndices]() { + batchChangeKind(collectIndices(), NodeKind::FuncPtr64); }); + addedQuickConvert = true; + } + if (commonKind == NodeKind::Hex32 || commonKind == NodeKind::Pointer32) { + menu.addAction("Change to fnptr32", [this, collectIndices]() { + batchChangeKind(collectIndices(), NodeKind::FuncPtr32); }); + addedQuickConvert = true; + } + if (commonKind == NodeKind::FuncPtr64) { + menu.addAction("Change to ptr64", [this, collectIndices]() { + batchChangeKind(collectIndices(), NodeKind::Pointer64); }); + addedQuickConvert = true; + } + if (commonKind == NodeKind::FuncPtr32) { + menu.addAction("Change to ptr32", [this, collectIndices]() { + batchChangeKind(collectIndices(), NodeKind::Pointer32); }); + addedQuickConvert = true; + } + } + if (addedQuickConvert) + menu.addSeparator(); + menu.addAction(icon("symbol-structure.svg"), QString("Change type of %1 nodes...").arg(count), - [this, ids]() { + [this, ids, collectIndices]() { QStringList types; for (const auto& e : kKindMeta) types << e.name; bool ok; QString sel = QInputDialog::getItem(nullptr, "Change Type", "Type:", types, 0, false, &ok); - if (ok) { - QVector indices; - for (uint64_t id : ids) { - int idx = m_doc->tree.indexOfId(id); - if (idx >= 0) indices.append(idx); - } - batchChangeKind(indices, kindFromString(sel)); + if (ok) + batchChangeKind(collectIndices(), kindFromString(sel)); + }); + + menu.addSeparator(); + + menu.addAction(icon("files.svg"), QString("Duplicate %1 nodes").arg(count), [this, ids]() { + for (uint64_t id : ids) { + int idx = m_doc->tree.indexOfId(id); + if (idx >= 0) duplicateNode(idx); } }); + menu.addAction(icon("trash.svg"), QString("Delete %1 nodes").arg(count), [this, collectIndices]() { + batchRemoveNodes(collectIndices()); + }); + + menu.addSeparator(); + + menu.addAction(icon("link.svg"), "Copy &Address", [this, ids]() { + QStringList addrs; + for (uint64_t id : ids) { + int ni = m_doc->tree.indexOfId(id); + if (ni < 0) continue; + uint64_t addr = m_doc->tree.baseAddress + m_doc->tree.computeOffset(ni); + addrs << QStringLiteral("0x") + QString::number(addr, 16).toUpper(); + } + QApplication::clipboard()->setText(addrs.join('\n')); + }); + menu.exec(globalPos); return; } @@ -1258,6 +1349,7 @@ void RcxController::showContextMenu(RcxEditor* editor, int line, int nodeIdx, menu.addSeparator(); bool isEditable = node.kind != NodeKind::Struct && node.kind != NodeKind::Array + && !isHexNode(node.kind) && m_doc->provider->isWritable(); if (isEditable) { menu.addAction(icon("edit.svg"), "Edit &Value\tEnter", [editor, line]() { diff --git a/src/core.h b/src/core.h index b6474c3..0a2896d 100644 --- a/src/core.h +++ b/src/core.h @@ -487,6 +487,7 @@ struct LineMeta { int arrayElementIdx = -1; // Index of this element within parent array (-1 if not array element) QString offsetText; uint64_t offsetAddr = 0; // Raw absolute address (for margin toggle) + uint64_t ptrBase = 0; // Pointer expansion base (non-zero = use for RVA) uint32_t markerMask = 0; bool dataChanged = false; // true if any byte in this node changed since last refresh int heatLevel = 0; // 0=static, 1=cold, 2=warm, 3=hot (from ValueHistory) diff --git a/src/disasm.cpp b/src/disasm.cpp new file mode 100644 index 0000000..a844403 --- /dev/null +++ b/src/disasm.cpp @@ -0,0 +1,76 @@ +#include "disasm.h" + +extern "C" { +#include +} + +namespace rcx { + +QString disassemble(const QByteArray& bytes, uint64_t baseAddr, int bitness, int maxBytes) { + if (bytes.isEmpty() || (bitness != 32 && bitness != 64)) + return {}; + + int len = qMin((int)bytes.size(), maxBytes); + const auto* buf = reinterpret_cast(bytes.constData()); + + QString result; + int off = 0; + while (off < len) { + FdInstr instr; + int ret = fd_decode(buf + off, len - off, bitness, baseAddr + off, &instr); + if (ret < 0) + break; + + char fmtBuf[128]; + fd_format(&instr, fmtBuf, sizeof(fmtBuf)); + + if (!result.isEmpty()) + result += QLatin1Char('\n'); + result += QStringLiteral("%1 %2") + .arg(baseAddr + off, bitness == 64 ? 16 : 8, 16, QLatin1Char('0')) + .arg(QString::fromLatin1(fmtBuf)); + + off += ret; + } + return result; +} + +QString hexDump(const QByteArray& bytes, uint64_t baseAddr, int maxBytes) { + if (bytes.isEmpty()) + return {}; + + int len = qMin((int)bytes.size(), maxBytes); + QString result; + + for (int off = 0; off < len; off += 16) { + int lineLen = qMin(16, len - off); + + if (!result.isEmpty()) + result += QLatin1Char('\n'); + + // Address + bool wide = (baseAddr + len > 0xFFFFFFFFULL); + result += QStringLiteral("%1 ").arg(baseAddr + off, wide ? 16 : 8, 16, QLatin1Char('0')); + + // Hex bytes + for (int i = 0; i < 16; i++) { + if (i < lineLen) { + uint8_t b = static_cast(bytes[off + i]); + result += QStringLiteral("%1 ").arg(b, 2, 16, QLatin1Char('0')); + } else { + result += QStringLiteral(" "); + } + if (i == 7) result += QLatin1Char(' '); + } + + // ASCII + result += QLatin1Char(' '); + for (int i = 0; i < lineLen; i++) { + char c = bytes[off + i]; + result += (c >= 0x20 && c < 0x7f) ? QLatin1Char(c) : QLatin1Char('.'); + } + } + return result; +} + +} // namespace rcx diff --git a/src/disasm.h b/src/disasm.h new file mode 100644 index 0000000..499b0ea --- /dev/null +++ b/src/disasm.h @@ -0,0 +1,15 @@ +#pragma once +#include +#include +#include + +namespace rcx { + +// Disassemble up to maxBytes of x86 code, returning formatted asm lines. +// bitness: 32 or 64. Returns one line per instruction, prefixed with offset. +QString disassemble(const QByteArray& bytes, uint64_t baseAddr, int bitness, int maxBytes = 128); + +// Format bytes as hex dump lines (16 bytes per line with ASCII sidebar). +QString hexDump(const QByteArray& bytes, uint64_t baseAddr, int maxBytes = 128); + +} // namespace rcx diff --git a/src/editor.cpp b/src/editor.cpp index 8ad4a87..19e39d9 100644 --- a/src/editor.cpp +++ b/src/editor.cpp @@ -1,4 +1,5 @@ #include "editor.h" +#include "disasm.h" #include "providerregistry.h" #include #include @@ -131,7 +132,6 @@ public: } void showAt(const QPoint& globalPos) { - if (isVisible()) return; QSize sz = sizeHint(); QRect screen = QApplication::screenAt(globalPos) ? QApplication::screenAt(globalPos)->availableGeometry() @@ -141,7 +141,7 @@ public: if (y + sz.height() > screen.bottom()) y = globalPos.y() - sz.height() - 4; move(x, y); - show(); + if (!isVisible()) show(); } void dismiss() { @@ -152,6 +152,106 @@ public: } }; +// ── Disassembly / hex-dump hover popup ── + +class DisasmPopup : public QFrame { + uint64_t m_nodeId = 0; + QString m_body; + QLabel* m_titleLabel = nullptr; + QLabel* m_bodyLabel = nullptr; +public: + explicit DisasmPopup(QWidget* parent) + : QFrame(parent, Qt::ToolTip | Qt::FramelessWindowHint) + { + setAttribute(Qt::WA_DeleteOnClose, false); + setAttribute(Qt::WA_ShowWithoutActivating, true); + setFrameShape(QFrame::NoFrame); + setAutoFillBackground(true); + + auto* vbox = new QVBoxLayout(this); + vbox->setContentsMargins(8, 6, 8, 6); + vbox->setSpacing(2); + + m_titleLabel = new QLabel; + QFont bold = m_titleLabel->font(); + bold.setBold(true); + m_titleLabel->setFont(bold); + vbox->addWidget(m_titleLabel); + + auto* sep = new QFrame; + sep->setFrameShape(QFrame::HLine); + sep->setFrameShadow(QFrame::Plain); + sep->setFixedHeight(1); + vbox->addWidget(sep); + + m_bodyLabel = new QLabel; + m_bodyLabel->setTextFormat(Qt::PlainText); + m_bodyLabel->setWordWrap(false); + vbox->addWidget(m_bodyLabel); + } + + uint64_t nodeId() const { return m_nodeId; } + + void populate(uint64_t nodeId, const QString& title, const QString& body, + const QFont& font) { + if (nodeId == m_nodeId && body == m_body && isVisible()) + return; + + m_nodeId = nodeId; + m_body = body; + + const auto& theme = ThemeManager::instance().current(); + QPalette pal; + pal.setColor(QPalette::Window, theme.backgroundAlt); + pal.setColor(QPalette::WindowText, theme.text); + setPalette(pal); + + QFont bold = font; + bold.setBold(true); + m_titleLabel->setFont(bold); + m_titleLabel->setText(title); + m_titleLabel->setStyleSheet( + QStringLiteral("color: %1;").arg(theme.text.name())); + + // Find and style the separator + for (auto* child : findChildren()) { + if (child->frameShape() == QFrame::HLine) { + QPalette sp; + sp.setColor(QPalette::WindowText, theme.border); + child->setPalette(sp); + break; + } + } + + m_bodyLabel->setFont(font); + m_bodyLabel->setText(body); + m_bodyLabel->setStyleSheet( + QStringLiteral("color: %1;").arg(theme.syntaxNumber.name())); + + setMaximumWidth(600); + adjustSize(); + } + + void showAt(const QPoint& globalPos) { + QSize sz = sizeHint(); + QRect screen = QApplication::screenAt(globalPos) + ? QApplication::screenAt(globalPos)->availableGeometry() + : QRect(0, 0, 1920, 1080); + int x = qMin(globalPos.x(), screen.right() - sz.width()); + int y = globalPos.y(); + if (y + sz.height() > screen.bottom()) + y = globalPos.y() - sz.height() - 4; + move(x, y); + if (!isVisible()) show(); + } + + void dismiss() { + if (isVisible()) hide(); + m_nodeId = 0; + m_body.clear(); + } +}; + static constexpr int IND_EDITABLE = 8; static constexpr int IND_HEX_DIM = 9; static constexpr int IND_BASE_ADDR = 10; // Default text color override for command row address @@ -570,6 +670,7 @@ void RcxEditor::applyDocument(const ComposeResult& result) { applyFoldLevels(result.meta); applyHexDimming(result.meta); applyHeatmapHighlight(result.meta); + applySymbolColoring(result.meta); applyCommandRowPills(); // Reset hint line - applySelectionOverlay will repaint indicators @@ -626,7 +727,8 @@ void RcxEditor::reformatMargins() { lm.lineKind == LineKind::CommandRow) { lm.offsetText = QString(hexDigits + 1, ' '); } else { - uint64_t rel = lm.offsetAddr >= base ? lm.offsetAddr - base : 0; + uint64_t rvaBase = lm.ptrBase ? lm.ptrBase : base; + uint64_t rel = lm.offsetAddr >= rvaBase ? lm.offsetAddr - rvaBase : 0; lm.offsetText = (QStringLiteral("+") + QString::number(rel, 16).toUpper()) .rightJustified(hexDigits, ' ') + QChar(' '); @@ -663,17 +765,22 @@ void RcxEditor::reformatMargins() { }; if (m_relativeOffsets) { - // Derive local offset: find enclosing header or array element separator + // Derive local offset: for pointer-expanded children use ptrBase, + // otherwise find enclosing header or array element separator uint64_t parentAddr = base; - for (int j = i - 1; j >= 0; j--) { - const auto& pLm = m_meta[j]; - if (pLm.lineKind == LineKind::Header && pLm.depth < lm.depth) { - parentAddr = pLm.offsetAddr; - break; - } - if (pLm.lineKind == LineKind::ArrayElementSeparator && pLm.depth <= lm.depth) { - parentAddr = pLm.offsetAddr; - break; + if (lm.ptrBase != 0) { + parentAddr = lm.ptrBase; + } else { + for (int j = i - 1; j >= 0; j--) { + const auto& pLm = m_meta[j]; + if (pLm.lineKind == LineKind::Header && pLm.depth < lm.depth) { + parentAddr = pLm.offsetAddr; + break; + } + if (pLm.lineKind == LineKind::ArrayElementSeparator && pLm.depth <= lm.depth) { + parentAddr = pLm.offsetAddr; + break; + } } } uint64_t localOff = lm.offsetAddr >= parentAddr ? lm.offsetAddr - parentAddr : 0; @@ -908,6 +1015,22 @@ ColumnSpan RcxEditor::typeSpan(const LineMeta& lm, int typeW) { return typeSpan ColumnSpan RcxEditor::nameSpan(const LineMeta& lm, int typeW, int nameW) { return nameSpanFor(lm, typeW, nameW); } ColumnSpan RcxEditor::valueSpan(const LineMeta& lm, int lineLength, int typeW, int nameW) { return valueSpanFor(lm, lineLength, typeW, nameW); } +// For pointer-like nodes, narrow value span to just the address portion +// (before the " // " separator that precedes the symbol like "Module+0x1234"). +static ColumnSpan narrowPtrValueSpan(const LineMeta& lm, const ColumnSpan& vs, + const QString& lineText) { + if (!vs.valid) return vs; + if (!isFuncPtr(lm.nodeKind) + && lm.nodeKind != NodeKind::Pointer32 + && lm.nodeKind != NodeKind::Pointer64) + return vs; + QString valText = lineText.mid(vs.start, vs.end - vs.start); + int sep = valText.indexOf(QLatin1String(" // ")); + if (sep > 0) + return {vs.start, vs.start + sep, true}; + return vs; +} + // ── Multi-selection ── QSet RcxEditor::selectedNodeIndices() const { @@ -956,28 +1079,10 @@ void RcxEditor::applyHeatmapHighlight(const QVector& meta) { // Pick the right indicator for this heat level (1→cold, 2→warm, 3→hot) int activeInd = heatIndicators[qBound(0, heat - 1, 2)]; - // For hex preview nodes: per-byte heat coloring on changed bytes - if (isHexPreview(lm.nodeKind) && lm.dataChanged && !lm.changedByteIndices.isEmpty()) { - int ind = kFoldCol + lm.depth * 3; - int asciiStart = ind + typeW + kSepWidth; - int hexStart = asciiStart + nameW + kSepWidth; - - for (int byteIdx : lm.changedByteIndices) { - fillIndicatorCols(activeInd, i, asciiStart + byteIdx, asciiStart + byteIdx + 1); - int hexCol = hexStart + byteIdx * 3; - fillIndicatorCols(activeInd, i, hexCol, hexCol + 2); - } - // Clear the other two heat indicators on this line - for (int hi : heatIndicators) { - if (hi != activeInd) - clearIndicatorLine(hi, i); - } - continue; - } - - // Non-hex nodes: apply heat-level indicator to value span + // Apply heat-level indicator to value span (narrowed for pointer-like nodes) QString lineText = getLineText(m_sci, i); - ColumnSpan vs = valueSpan(lm, lineText.size(), typeW, nameW); + ColumnSpan vs = narrowPtrValueSpan(lm, + valueSpan(lm, lineText.size(), typeW, nameW), lineText); if (!vs.valid) continue; fillIndicatorCols(activeInd, i, vs.start, vs.end); @@ -990,6 +1095,28 @@ void RcxEditor::applyHeatmapHighlight(const QVector& meta) { } } +void RcxEditor::applySymbolColoring(const QVector& meta) { + for (int i = 0; i < meta.size(); i++) { + const LineMeta& lm = meta[i]; + if (!isFuncPtr(lm.nodeKind) + && lm.nodeKind != NodeKind::Pointer32 + && lm.nodeKind != NodeKind::Pointer64) + continue; + QString lineText = getLineText(m_sci, i); + // Find " // " within the value region and color "// sym" portion green + ColumnSpan vs = valueSpan(lm, lineText.size(), lm.effectiveTypeW, lm.effectiveNameW); + if (!vs.valid) continue; + int searchFrom = vs.start; + int sep = lineText.indexOf(QLatin1String(" // "), searchFrom); + if (sep < 0 || sep >= vs.end) continue; + int symStart = sep + 2; // start of "// sym" + int symEnd = vs.end; + while (symEnd > symStart && lineText[symEnd - 1] == ' ') symEnd--; + if (symEnd > symStart) + fillIndicatorCols(IND_HINT_GREEN, i, symStart, symEnd); + } +} + void RcxEditor::applyBaseAddressColoring(const QVector& meta) { if (meta.isEmpty() || meta[0].lineKind != LineKind::CommandRow) return; @@ -1354,7 +1481,8 @@ static bool hitTestTarget(QsciScintilla* sci, ColumnSpan ts = RcxEditor::typeSpan(lm, typeW); ColumnSpan ns = RcxEditor::nameSpan(lm, typeW, nameW); - ColumnSpan vs = RcxEditor::valueSpan(lm, textLen, typeW, nameW); + ColumnSpan vs = narrowPtrValueSpan(lm, + RcxEditor::valueSpan(lm, textLen, typeW, nameW), lineText); // Pointer fields/headers: check sub-spans within type column first if (lm.nodeKind == NodeKind::Pointer32 || lm.nodeKind == NodeKind::Pointer64) { @@ -2440,14 +2568,19 @@ void RcxEditor::applyHoverCursor() { if (!showPopup && m_historyPopup && m_historyPopup->isVisible()) static_cast(m_historyPopup)->dismiss(); } + // Always dismiss disasm popup during inline editing + if (m_disasmPopup && m_disasmPopup->isVisible()) + static_cast(m_disasmPopup)->dismiss(); return; } - // Mouse left viewport - set Arrow, dismiss history popup + // Mouse left viewport - set Arrow, dismiss popups // (but not during applyDocument — the Leave is synthetic from setText) if (!m_hoverInside) { if (m_historyPopup && !m_applyingDocument) static_cast(m_historyPopup)->dismiss(); + if (m_disasmPopup && !m_applyingDocument) + static_cast(m_disasmPopup)->dismiss(); m_sci->viewport()->setCursor(Qt::ArrowCursor); return; } @@ -2522,6 +2655,18 @@ void RcxEditor::applyHoverCursor() { m_hoverSpanLines.append(line); } } + // Narrow pointer-like nodes to address portion only (exclude symbol) + if (!narrowed && (isFuncPtr(lm.nodeKind) + || lm.nodeKind == NodeKind::Pointer32 + || lm.nodeKind == NodeKind::Pointer64)) { + ColumnSpan full = valueSpan(lm, lineText.size(), lm.effectiveTypeW, lm.effectiveNameW); + ColumnSpan narrow = narrowPtrValueSpan(lm, full, lineText); + if (h.col >= narrow.start && h.col < narrow.end) { + fillIndicatorCols(IND_HOVER_SPAN, line, narrow.start, narrow.end); + m_hoverSpanLines.append(line); + } + narrowed = true; + } } if (!narrowed && h.col >= span.start && h.col < span.end) { fillIndicatorCols(IND_HOVER_SPAN, line, span.start, span.end); @@ -2537,11 +2682,16 @@ void RcxEditor::applyHoverCursor() { } // Value history popup on hover (read-only, no buttons) + // Skip FuncPtr and void-Pointer nodes — they use the disasm popup instead. { bool showPopup = false; if (m_valueHistory && h.line >= 0 && h.line < m_meta.size()) { const LineMeta& lm = m_meta[h.line]; - if (lm.heatLevel > 0 && lm.nodeId != 0) { + bool skipForDisasm = isFuncPtr(lm.nodeKind) + || ((lm.nodeKind == NodeKind::Pointer32 + || lm.nodeKind == NodeKind::Pointer64) + && lm.pointerTargetName.isEmpty()); + if (lm.heatLevel > 0 && lm.nodeId != 0 && !skipForDisasm) { auto it = m_valueHistory->find(lm.nodeId); if (it != m_valueHistory->end() && it->uniqueCount() > 1) { QString lineText = getLineText(m_sci, h.line); @@ -2571,6 +2721,110 @@ void RcxEditor::applyHoverCursor() { static_cast(m_historyPopup)->dismiss(); } + // Disasm / hex-dump popup on hover for FuncPtr and void Pointer nodes + { + bool showDisasm = false; + if (m_disasmProvider && m_disasmTree && h.line >= 0 && h.line < m_meta.size()) { + const LineMeta& lm = m_meta[h.line]; + bool isFP = isFuncPtr(lm.nodeKind); + bool isVoidPtr = (lm.nodeKind == NodeKind::Pointer32 + || lm.nodeKind == NodeKind::Pointer64) + && lm.pointerTargetName.isEmpty(); + if ((isFP || isVoidPtr) && lm.nodeIdx >= 0 + && lm.nodeIdx < m_disasmTree->nodes.size()) { + // Check hover is over the address portion of the value column + QString lineText = getLineText(m_sci, h.line); + ColumnSpan vs = narrowPtrValueSpan(lm, + valueSpan(lm, lineText.size(), lm.effectiveTypeW, lm.effectiveNameW), + lineText); + if (vs.valid && h.col >= vs.start && h.col < vs.end) { + const Node& node = m_disasmTree->nodes[lm.nodeIdx]; + // For void ptrs, only show hex dump if refId == 0 + if (!isVoidPtr || node.refId == 0) { + bool is64 = (lm.nodeKind == NodeKind::FuncPtr64 + || lm.nodeKind == NodeKind::Pointer64); + // Use composed address (correct for pointer-expanded nodes) + // not node.offset (which is just offset within struct definition). + uint64_t provAddr = lm.offsetAddr >= m_disasmTree->baseAddress + ? lm.offsetAddr - m_disasmTree->baseAddress + : static_cast(node.offset); + uint64_t ptrVal = is64 + ? m_disasmProvider->readU64(provAddr) + : (uint64_t)m_disasmProvider->readU32(provAddr); + if (ptrVal != 0 && ptrVal != UINT64_MAX + && !(is64 == false && ptrVal == 0xFFFFFFFF)) { + // Read code bytes from the function target address. + // Use the real provider (not snapshot) because function + // code lives at arbitrary process addresses that aren't + // in the snapshot page table. The provider reads from + // m_base + addr via ReadProcessMemory, so we convert + // the absolute ptrVal to provider-relative. + const Provider* codeProv = m_disasmRealProv + ? m_disasmRealProv : m_disasmProvider; + constexpr int kMaxRead = 128; + uint64_t codeAddr = ptrVal - m_disasmTree->baseAddress; + QByteArray bytes(kMaxRead, Qt::Uninitialized); + bool readOk = codeProv->read(codeAddr, bytes.data(), kMaxRead); + if (readOk) { + QString title, body; + if (isFP) { + title = QStringLiteral("Disassembly"); + body = disassemble(bytes, ptrVal, + is64 ? 64 : 32, kMaxRead); + } else { + title = QStringLiteral("Hex Dump"); + body = hexDump(bytes, ptrVal, kMaxRead); + } + // Cap at 6 lines so the popup stays compact + { + const int kMaxLines = 6; + int nth = 0, idx = 0; + while (nth < kMaxLines && (idx = body.indexOf('\n', idx)) != -1) + { ++nth; ++idx; } + if (nth == kMaxLines && idx < body.size()) { + body.truncate(idx); + body += QStringLiteral("..."); + } + } + if (!body.isEmpty()) { + if (!m_disasmPopup) + m_disasmPopup = new DisasmPopup(this); + auto* popup = static_cast( + m_disasmPopup); + popup->populate(lm.nodeId, title, body, + editorFont()); + long linePos = m_sci->SendScintilla( + QsciScintillaBase::SCI_POSITIONFROMLINE, + (unsigned long)h.line); + long byteOff = lineText.left(vs.start) + .toUtf8().size(); + int px = (int)m_sci->SendScintilla( + QsciScintillaBase::SCI_POINTXFROMPOSITION, + (unsigned long)0, linePos + byteOff); + int py = (int)m_sci->SendScintilla( + QsciScintillaBase::SCI_POINTYFROMPOSITION, + (unsigned long)0, linePos); + int lh = (int)m_sci->SendScintilla( + QsciScintillaBase::SCI_TEXTHEIGHT, + (unsigned long)h.line); + QPoint anchor = m_sci->viewport()->mapToGlobal( + QPoint(px, py + lh)); + popup->showAt(anchor); + showDisasm = true; + // Dismiss value history popup to avoid fighting + if (m_historyPopup && m_historyPopup->isVisible()) + static_cast(m_historyPopup)->dismiss(); + } + } + } + } + } + } + } + if (!showDisasm && m_disasmPopup && m_disasmPopup->isVisible()) + static_cast(m_disasmPopup)->dismiss(); + } + // Determine cursor shape based on interaction type Qt::CursorShape desired = Qt::ArrowCursor; diff --git a/src/editor.h b/src/editor.h index c340e27..3a5f468 100644 --- a/src/editor.h +++ b/src/editor.h @@ -55,6 +55,9 @@ public: QString textWithMargins() const; void setCustomTypeNames(const QStringList& names); void setValueHistoryRef(const QHash* ref) { m_valueHistory = ref; } + void setProviderRef(const Provider* prov, const Provider* realProv, const NodeTree* tree) { + m_disasmProvider = prov; m_disasmRealProv = realProv; m_disasmTree = tree; + } // Saved sources for quick-switch in source picker void setSavedSources(const QVector& sources) { m_savedSourceDisplay = sources; } @@ -133,6 +136,10 @@ private: // ── Value history ref (owned by controller) ── const QHash* m_valueHistory = nullptr; QWidget* m_historyPopup = nullptr; // ValueHistoryPopup (file-local class in editor.cpp) + QWidget* m_disasmPopup = nullptr; // DisasmPopup (file-local class in editor.cpp) + const Provider* m_disasmProvider = nullptr; // snapshot or real — for reading tree data + const Provider* m_disasmRealProv = nullptr; // real process provider — for reading code at arbitrary addresses + const NodeTree* m_disasmTree = nullptr; // ── Reentrancy guards ── bool m_applyingDocument = false; @@ -152,6 +159,7 @@ private: void applyFoldLevels(const QVector& meta); void applyHexDimming(const QVector& meta); void applyHeatmapHighlight(const QVector& meta); + void applySymbolColoring(const QVector& meta); void applyBaseAddressColoring(const QVector& meta); void applyCommandRowPills(); diff --git a/src/examples/KUSER_SHARED_DATA.rcx b/src/examples/KUSER_SHARED_DATA.rcx new file mode 100644 index 0000000..49de2e4 --- /dev/null +++ b/src/examples/KUSER_SHARED_DATA.rcx @@ -0,0 +1,1316 @@ +{ + "baseAddress": "7ffe0000", + "nextId": "704", + "nodes": [ + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "46", + "kind": "Struct", + "name": "ksd", + "offset": 0, + "parentId": "0", + "refId": "0", + "strLen": 64, + "structTypeName": "KUSER_SHARED_DATA" + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "47", + "kind": "UInt32", + "name": "TickCountLowDeprecated", + "offset": 0, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "48", + "kind": "UInt32", + "name": "TickCountMultiplier", + "offset": 4, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "49", + "kind": "UInt32", + "name": "InterruptTime.LowPart", + "offset": 8, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "50", + "kind": "UInt32", + "name": "InterruptTime.High1Time", + "offset": 12, + "parentId": "46", + "refId": "0", + "strLen": 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"collapsed": false, + "elementKind": "UInt8", + "id": "677", + "kind": "UInt32", + "name": "Offset", + "offset": 0, + "parentId": "676", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "678", + "kind": "UInt32", + "name": "Size", + "offset": 4, + "parentId": "676", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 64, + "collapsed": true, + "elementKind": "UInt8", + "id": "679", + "kind": "Array", + "name": "ProcessorFeatures", + "offset": 628, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 4, + "collapsed": true, + "elementKind": "UInt32", + "id": "680", + "kind": "Array", + "name": "EnclaveFeatureMask", + "offset": 876, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 16, + "collapsed": true, + "elementKind": "UInt16", + "id": "681", + "kind": "Array", + "name": "UserModeGlobalLogger", + "offset": 896, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 64, + "collapsed": true, + "elementKind": "Struct", + "id": "688", + "kind": "Array", + "name": "XState.Features", + "offset": 1008, + "parentId": "46", + "refId": "676", + "strLen": 64 + }, + { + "arrayLen": 64, + "collapsed": true, + "elementKind": "UInt32", + "id": "690", + "kind": "Array", + "name": "XState.AllFeatures", + "offset": 1540, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "691", + "kind": "UInt32", + "name": "FeatureConfigChangeStamp.LowPart", + "offset": 1824, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "692", + "kind": "UInt32", + "name": "FeatureConfigChangeStamp.High1Time", + "offset": 1828, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "693", + "kind": "UInt32", + "name": "FeatureConfigChangeStamp.High2Time", + "offset": 1832, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "694", + "kind": "UInt32", + "name": "Spare", + "offset": 1836, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 1, + "collapsed": false, + "elementKind": "UInt8", + "id": "695", + "kind": "UInt64", + "name": "UserPointerAuthMask", + "offset": 1840, + "parentId": "46", + "refId": "0", + "strLen": 64 + }, + { + "arrayLen": 210, + "collapsed": true, + "elementKind": "UInt32", + "id": "696", + "kind": "Array", + "name": "Reserved10", + "offset": 1848, + "parentId": "46", + "refId": "0", + "strLen": 64 + } + ] +} diff --git a/src/format.cpp b/src/format.cpp index b548c32..f2f9e34 100644 --- a/src/format.cpp +++ b/src/format.cpp @@ -262,7 +262,7 @@ static QString readValueImpl(const Node& node, const Provider& prov, if (!display) return rawHex(val, 8); QString s = fmtPointer32(val); QString sym = prov.getSymbol((uint64_t)val); - if (!sym.isEmpty()) s += QStringLiteral(" ") + sym; + if (!sym.isEmpty()) s += QStringLiteral(" // ") + sym; return s; } case NodeKind::Pointer64: { @@ -270,7 +270,7 @@ static QString readValueImpl(const Node& node, const Provider& prov, if (!display) return rawHex(val, 16); QString s = fmtPointer64(val); QString sym = prov.getSymbol(val); - if (!sym.isEmpty()) s += QStringLiteral(" ") + sym; + if (!sym.isEmpty()) s += QStringLiteral(" // ") + sym; return s; } case NodeKind::FuncPtr32: { @@ -278,7 +278,7 @@ static QString readValueImpl(const Node& node, const Provider& prov, if (!display) return rawHex(val, 8); QString s = fmtPointer32(val); QString sym = prov.getSymbol((uint64_t)val); - if (!sym.isEmpty()) s += QStringLiteral(" ") + sym; + if (!sym.isEmpty()) s += QStringLiteral(" // ") + sym; return s; } case NodeKind::FuncPtr64: { @@ -286,7 +286,7 @@ static QString readValueImpl(const Node& node, const Provider& prov, if (!display) return rawHex(val, 16); QString s = fmtPointer64(val); QString sym = prov.getSymbol(val); - if (!sym.isEmpty()) s += QStringLiteral(" ") + sym; + if (!sym.isEmpty()) s += QStringLiteral(" // ") + sym; return s; } case NodeKind::Vec2: diff --git a/src/main.cpp b/src/main.cpp index f09b273..7270286 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -808,24 +808,96 @@ void MainWindow::newDocument() { rebuildWorkspaceModel(); } -void MainWindow::selfTest() { -#ifdef Q_OS_WIN - // Auto-open KUSER_SHARED_DATA example if available - QString exPath = QCoreApplication::applicationDirPath() - + "/examples/KUSER_SHARED_DATA.rcx"; - if (QFile::exists(exPath)) { - project_open(exPath); - } else { - project_new(); +static void buildEditorDemo(NodeTree& tree, uintptr_t editorAddr) { + tree.nodes.clear(); + tree.invalidateIdCache(); + tree.m_nextId = 1; + tree.baseAddress = static_cast(editorAddr); + + // ── Root struct: RcxEditor ── + Node root; + root.kind = NodeKind::Struct; + root.name = QStringLiteral("editor"); + root.structTypeName = QStringLiteral("RcxEditor"); + root.classKeyword = QStringLiteral("class"); + int ri = tree.addNode(root); + uint64_t rootId = tree.nodes[ri].id; + + // ── VTable struct definition (separate root) ── + Node vtStruct; + vtStruct.kind = NodeKind::Struct; + vtStruct.name = QStringLiteral("VTable"); + vtStruct.structTypeName = QStringLiteral("QWidgetVTable"); + int vti = tree.addNode(vtStruct); + uint64_t vtId = tree.nodes[vti].id; + + // VTable entries — these are real virtual function pointers from QObject/QWidget + static const char* vfNames[] = { + "deleting_dtor", "metaObject", "qt_metacast", "qt_metacall", + "event", "eventFilter", "timerEvent", "childEvent", + "customEvent", "connectNotify", "disconnectNotify", "devType", + "setVisible", "sizeHint", "minimumSizeHint", "heightForWidth", + }; + for (int i = 0; i < 16; i++) { + Node fn; + fn.kind = NodeKind::FuncPtr64; + fn.name = QString::fromLatin1(vfNames[i]); + fn.parentId = vtId; + fn.offset = i * 8; + tree.addNode(fn); } - // Auto-attach process memory plugin to self - auto* ctrl = activeController(); - if (ctrl) { - DWORD pid = GetCurrentProcessId(); - QString target = QString("%1:Reclass.exe").arg(pid); - ctrl->attachViaPlugin(QStringLiteral("processmemory"), target); + // ── RcxEditor fields ── + // offset 0: vtable pointer → QWidgetVTable + { + Node n; + n.kind = NodeKind::Pointer64; + n.name = QStringLiteral("__vptr"); + n.parentId = rootId; + n.offset = 0; + n.refId = vtId; + tree.addNode(n); } + // offset 8: QObjectData* d_ptr (QObject internals) + { + Node n; + n.kind = NodeKind::Pointer64; + n.name = QStringLiteral("d_ptr"); + n.parentId = rootId; + n.offset = 8; + tree.addNode(n); + } + // The rest of the object: raw memory visible as Hex64 fields + // QWidget base is large (~200+ bytes), then RcxEditor members follow. + // Lay out enough to cover the interesting editor state. + for (int off = 16; off < 512; off += 8) { + Node n; + n.kind = NodeKind::Hex64; + n.name = QStringLiteral("field_%1").arg(off, 3, 16, QLatin1Char('0')); + n.parentId = rootId; + n.offset = off; + tree.addNode(n); + } +} + +void MainWindow::selfTest() { +#ifdef Q_OS_WIN + // Create a new project, then point it at the live editor object + project_new(); + + auto* ctrl = activeController(); + if (!ctrl || ctrl->editors().isEmpty()) return; + + auto* editor = ctrl->editors().first(); + auto* doc = ctrl->document(); + + // Build a tree describing RcxEditor, based at the real object address + buildEditorDemo(doc->tree, reinterpret_cast(editor)); + + // Attach process memory to self — provider base will be set to the editor address + DWORD pid = GetCurrentProcessId(); + QString target = QString("%1:Reclass.exe").arg(pid); + ctrl->attachViaPlugin(QStringLiteral("processmemory"), target); #else project_new(); #endif diff --git a/tests/test_disasm.cpp b/tests/test_disasm.cpp new file mode 100644 index 0000000..5817760 --- /dev/null +++ b/tests/test_disasm.cpp @@ -0,0 +1,470 @@ +#include +#include "disasm.h" +#include "core.h" +#include "providers/buffer_provider.h" + +using namespace rcx; + +// Helper: extract mnemonic portion from disassembly output (after "addr ") +static QString mnemonic(const QString& line) { + int sep = line.indexOf(" "); + return sep >= 0 ? line.mid(sep + 2) : line; +} + +class TestDisasm : public QObject { + Q_OBJECT +private slots: + // ────────────────────────────────────────────────── + // disassemble() unit tests – exact mnemonic match + // ────────────────────────────────────────────────── + + void testDisasm64_pushMov() { + QByteArray code("\x55\x48\x89\xe5", 4); + QString result = disassemble(code, 0x401000, 64); + QStringList lines = result.split('\n'); + QCOMPARE(lines.size(), 2); + QVERIFY(lines[0].startsWith("0000000000401000")); + QVERIFY(lines[1].startsWith("0000000000401001")); + QCOMPARE(mnemonic(lines[0]), QStringLiteral("push rbp")); + QCOMPARE(mnemonic(lines[1]), QStringLiteral("mov rbp, rsp")); + } + + void testDisasm64_ret() { QCOMPARE(mnemonic(disassemble(QByteArray("\xc3",1), 0x7FF000, 64)), QStringLiteral("ret")); } + void testDisasm64_nop() { QCOMPARE(mnemonic(disassemble(QByteArray("\x90",1), 0, 64)), QStringLiteral("nop")); } + void testDisasm64_xorEax() { QCOMPARE(mnemonic(disassemble(QByteArray("\x31\xc0",2), 0, 64)), QStringLiteral("xor eax, eax")); } + void testDisasm64_subRsp() { QCOMPARE(mnemonic(disassemble(QByteArray("\x48\x83\xec\x20",4), 0, 64)), QStringLiteral("sub rsp, 0x20")); } + void testDisasm64_int3() { QCOMPARE(mnemonic(disassemble(QByteArray("\xcc",1), 0, 64)), QStringLiteral("int3")); } + void testDisasm64_pushRdi() { QCOMPARE(mnemonic(disassemble(QByteArray("\x57",1), 0, 64)), QStringLiteral("push rdi")); } + void testDisasm64_popRsi() { QCOMPARE(mnemonic(disassemble(QByteArray("\x5e",1), 0, 64)), QStringLiteral("pop rsi")); } + void testDisasm64_testEax() { QCOMPARE(mnemonic(disassemble(QByteArray("\x85\xc0",2), 0, 64)), QStringLiteral("test eax, eax")); } + + void testDisasm64_leaRipRel() { + QCOMPARE(mnemonic(disassemble(QByteArray("\x48\x8d\x05\x10\x00\x00\x00",7), 0x1000, 64)), + QStringLiteral("lea rax, [rip+0x10]")); + } + void testDisasm64_callRel() { + // call target = 0x1000 + 5 + 0x100 = 0x1105 + QCOMPARE(mnemonic(disassemble(QByteArray("\xe8\x00\x01\x00\x00",5), 0x1000, 64)), + QStringLiteral("call 0x1105")); + } + void testDisasm64_jmpRel() { + // jmp target = 0x1000 + 2 + 0x10 = 0x1012 + QCOMPARE(mnemonic(disassemble(QByteArray("\xeb\x10",2), 0x1000, 64)), + QStringLiteral("jmp 0x1012")); + } + void testDisasm64_movMemRead() { + QCOMPARE(mnemonic(disassemble(QByteArray("\x48\x8b\x43\x10",4), 0, 64)), + QStringLiteral("mov rax, qword ptr [rbx+0x10]")); + } + void testDisasm64_movMemWrite() { + QCOMPARE(mnemonic(disassemble(QByteArray("\x48\x89\x4c\x24\x08",5), 0, 64)), + QStringLiteral("mov qword ptr [rsp+0x8], rcx")); + } + + void testDisasm64_functionPrologue() { + QByteArray code("\x55\x48\x89\xe5\x48\x83\xec\x20\xc3", 9); + QStringList lines = disassemble(code, 0x140001000ULL, 64).split('\n'); + QCOMPARE(lines.size(), 4); + QVERIFY(lines[0].startsWith("0000000140001000")); + QCOMPARE(mnemonic(lines[0]), QStringLiteral("push rbp")); + QCOMPARE(mnemonic(lines[1]), QStringLiteral("mov rbp, rsp")); + QCOMPARE(mnemonic(lines[2]), QStringLiteral("sub rsp, 0x20")); + QCOMPARE(mnemonic(lines[3]), QStringLiteral("ret")); + } + + void testDisasm64_multipleNops() { + QStringList lines = disassemble(QByteArray(5,'\x90'), 0x1000, 64).split('\n'); + QCOMPARE(lines.size(), 5); + for (int i = 0; i < 5; i++) { + QCOMPARE(mnemonic(lines[i]), QStringLiteral("nop")); + QVERIFY(lines[i].startsWith(QStringLiteral("%1").arg(0x1000+i, 16, 16, QLatin1Char('0')))); + } + } + + void testDisasm32_pushMov() { + QByteArray code("\x55\x89\xe5", 3); + QStringList lines = disassemble(code, 0x401000, 32).split('\n'); + QCOMPARE(lines.size(), 2); + QVERIFY(lines[0].startsWith("00401000")); + QCOMPARE(mnemonic(lines[0]), QStringLiteral("push ebp")); + QCOMPARE(mnemonic(lines[1]), QStringLiteral("mov ebp, esp")); + } + + void testDisasm_empty() { QVERIFY(disassemble({}, 0, 64).isEmpty()); QVERIFY(disassemble({}, 0, 32).isEmpty()); } + void testDisasm_invalidBitness() { QVERIFY(disassemble(QByteArray("\x90",1), 0, 16).isEmpty()); } + void testDisasm_maxBytes() { QCOMPARE(disassemble(QByteArray(200,'\x90'), 0, 64, 128).count('\n') + 1, 128); } + void testDisasm64_addrWidth() { QCOMPARE(disassemble(QByteArray("\x90",1), 0, 64).indexOf(" "), 16); } + void testDisasm32_addrWidth() { QCOMPARE(disassemble(QByteArray("\x90",1), 0, 32).indexOf(" "), 8); } + + // ────────────────────────────────────────────────── + // hexDump() unit tests + // ────────────────────────────────────────────────── + + void testHexDump_basic() { + QByteArray data; for (int i=0;i<32;i++) data.append((char)i); + QString r = hexDump(data, 0x1000, 128); + QCOMPARE(r.count('\n')+1, 2); + QVERIFY(r.startsWith("00001000")); + } + void testHexDump_ascii() { + QVERIFY(hexDump(QByteArray("Hello, World!xx",15), 0, 128).contains("Hello")); + } + void testHexDump_nonPrintable() { + QByteArray d(16,'\0'); d[0]='A'; d[15]='Z'; + QVERIFY(hexDump(d, 0, 128).contains("A..............Z")); + } + void testHexDump_empty() { QVERIFY(hexDump({}, 0).isEmpty()); } + void testHexDump_maxBytes() { QCOMPARE(hexDump(QByteArray(200,'\xAA'), 0, 64).count('\n')+1, 4); } + void testHexDump_wideAddr() { QVERIFY(hexDump(QByteArray(16,'\0'), 0x100000000ULL, 128).startsWith("0000000100000000")); } + void testHexDump_hexValues() { + QByteArray d; d.append('\xDE'); d.append('\xAD'); d.append('\xBE'); d.append('\xEF'); + while (d.size()<16) d.append('\0'); + QVERIFY(hexDump(d, 0, 128).contains("de ad be ef", Qt::CaseInsensitive)); + } + void testHexDump_secondLineAddr() { + QStringList lines = hexDump(QByteArray(32,'\x42'), 0x2000, 128).split('\n'); + QCOMPARE(lines.size(), 2); + QVERIFY(lines[1].startsWith("00002010")); + } + + // ────────────────────────────────────────────────── + // End-to-end: pointer-expanded VTable with FuncPtr64 + // Verifies we read from the COMPOSED address, not node.offset + // ────────────────────────────────────────────────── + + void testVTableDisasm_composedAddress() { + // Memory layout (provider-relative, i.e. offset from baseAddress): + // + // [0x0000] Root "Obj" struct + // +0x00: Pointer64 __vptr => points to 0xBASE+0x100 (vtable) + // + // [0x0100] VTable (expanded via pointer deref) + // +0x00: func ptr 0 => value 0xBASE+0x200 (func0 code) + // +0x08: func ptr 1 => value 0xBASE+0x300 (func1 code) + // + // [0x0200] func0 code: push rbp; ret + // [0x0300] func1 code: xor eax, eax; ret + // + const uint64_t kBase = 0x7FF600000000ULL; + + // Build a 4KB buffer + QByteArray mem(4096, '\0'); + auto w64 = [&](int off, uint64_t val) { + memcpy(mem.data() + off, &val, 8); + }; + + // Root object at offset 0: __vptr points to vtable at kBase + 0x100 + w64(0x00, kBase + 0x100); + + // VTable at offset 0x100: two function pointers + w64(0x100, kBase + 0x200); // slot 0 -> func0 + w64(0x108, kBase + 0x300); // slot 1 -> func1 + + // func0 at offset 0x200: push rbp; ret + mem[0x200] = '\x55'; + mem[0x201] = '\xc3'; + + // func1 at offset 0x300: xor eax, eax; ret + mem[0x300] = '\x31'; + mem[0x301] = '\xc0'; + mem[0x302] = '\xc3'; + + BufferProvider prov(mem); + + // Build node tree + NodeTree tree; + tree.baseAddress = kBase; + + // Root struct "Obj" + Node root; + root.kind = NodeKind::Struct; + root.name = "Obj"; + root.parentId = 0; + root.offset = 0; + int ri = tree.addNode(root); + uint64_t rootId = tree.nodes[ri].id; + + // VTable struct definition (template) + Node vtDef; + vtDef.kind = NodeKind::Struct; + vtDef.name = "VTable"; + vtDef.parentId = 0; + vtDef.offset = 0x1000; // parked far away so it doesn't overlap + int vti = tree.addNode(vtDef); + uint64_t vtId = tree.nodes[vti].id; + + // Two FuncPtr64 children inside VTable definition + Node fp0; + fp0.kind = NodeKind::FuncPtr64; + fp0.name = "func0"; + fp0.parentId = vtId; + fp0.offset = 0; + tree.addNode(fp0); + + Node fp1; + fp1.kind = NodeKind::FuncPtr64; + fp1.name = "func1"; + fp1.parentId = vtId; + fp1.offset = 8; + tree.addNode(fp1); + + // Pointer64 "__vptr" in root, pointing to VTable via refId + Node vptr; + vptr.kind = NodeKind::Pointer64; + vptr.name = "__vptr"; + vptr.parentId = rootId; + vptr.offset = 0; + vptr.refId = vtId; + tree.addNode(vptr); + + // Compose the tree + ComposeResult result = compose(tree, prov); + + // Find the FuncPtr64 lines in the composed output that are inside the + // pointer-expanded VTable (near vtable address), not the standalone definition. + struct FuncInfo { int line; uint64_t offsetAddr; NodeKind kind; QString name; }; + QVector funcPtrs; + for (int i = 0; i < result.meta.size(); i++) { + const LineMeta& lm = result.meta[i]; + if (lm.nodeKind == NodeKind::FuncPtr64 && lm.lineKind == LineKind::Field) { + // Only include the pointer-expanded ones (near vtable at kBase+0x100) + if (lm.offsetAddr >= kBase + 0x100 && lm.offsetAddr < kBase + 0x200) { + int nodeIdx = lm.nodeIdx; + funcPtrs.append({i, lm.offsetAddr, lm.nodeKind, + nodeIdx >= 0 ? tree.nodes[nodeIdx].name : QString()}); + } + } + } + + QCOMPARE(funcPtrs.size(), 2); + + // Verify composed addresses point to the vtable, NOT to the root struct + // func0 should be at kBase + 0x100 (vtable + 0) + QCOMPARE(funcPtrs[0].offsetAddr, kBase + 0x100); + // func1 should be at kBase + 0x108 (vtable + 8) + QCOMPARE(funcPtrs[1].offsetAddr, kBase + 0x108); + + // Now simulate what the hover code should do: + // Read the function pointer VALUE from the correct provider address + for (const auto& fp : funcPtrs) { + // Provider-relative address = offsetAddr - baseAddress + uint64_t provAddr = fp.offsetAddr - kBase; + + // Read the pointer value (the function address) + uint64_t ptrVal = prov.readU64(provAddr); + + // Verify we got the right pointer values + if (fp.name == "func0") { + QCOMPARE(ptrVal, kBase + 0x200); + } else { + QCOMPARE(ptrVal, kBase + 0x300); + } + + // Convert pointer value to provider-relative for reading code bytes + uint64_t codeProvAddr = ptrVal - kBase; + QByteArray codeBytes = prov.readBytes(codeProvAddr, 128); + + // Disassemble and verify + QString asm_ = disassemble(codeBytes, ptrVal, 64, 128); + QVERIFY2(!asm_.isEmpty(), qPrintable("Empty disasm for " + fp.name)); + + QStringList lines = asm_.split('\n'); + if (fp.name == "func0") { + // Should decode: push rbp; ret + QVERIFY2(lines.size() >= 2, qPrintable(QString("Expected >= 2 lines for func0, got %1: %2").arg(lines.size()).arg(asm_))); + QCOMPARE(mnemonic(lines[0]), QStringLiteral("push rbp")); + QCOMPARE(mnemonic(lines[1]), QStringLiteral("ret")); + // Verify address in output matches the real function address + QVERIFY2(lines[0].startsWith("00007ff600000200"), + qPrintable("func0 addr wrong: " + lines[0])); + } else { + // Should decode: xor eax, eax; ret + QVERIFY2(lines.size() >= 2, qPrintable(QString("Expected >= 2 lines for func1, got %1: %2").arg(lines.size()).arg(asm_))); + QCOMPARE(mnemonic(lines[0]), QStringLiteral("xor eax, eax")); + QCOMPARE(mnemonic(lines[1]), QStringLiteral("ret")); + QVERIFY2(lines[0].startsWith("00007ff600000300"), + qPrintable("func1 addr wrong: " + lines[0])); + } + } + + // CRITICAL: Verify that reading from node.offset (the WRONG way) gives + // different/wrong results. node.offset for func0=0, func1=8, which are + // inside the ROOT struct, not the vtable. + uint64_t wrongVal0 = prov.readU64(0); // node.offset=0: reads __vptr value + uint64_t wrongVal1 = prov.readU64(8); // node.offset=8: reads garbage after __vptr + // wrongVal0 = kBase + 0x100 (the vptr itself, NOT a function address) + QCOMPARE(wrongVal0, kBase + 0x100); + // This is the vtable address, not a function — disassembling it would be wrong + QVERIFY2(wrongVal0 != kBase + 0x200, + "node.offset reads the vptr, not the function pointer"); + QVERIFY2(wrongVal1 != kBase + 0x300, + "node.offset=8 reads past vptr, not the second function pointer"); + } + + void testVTableDisasm_wrongAddressGivesWrongCode() { + // Demonstrate that using node.offset instead of composed address + // gives completely wrong disassembly results + const uint64_t kBase = 0x10000; + QByteArray mem(1024, '\0'); + auto w64 = [&](int off, uint64_t val) { memcpy(mem.data()+off, &val, 8); }; + + // Root at 0: vptr -> 0x80 + w64(0x00, kBase + 0x80); + // VTable at 0x80: one func ptr -> 0x100 + w64(0x80, kBase + 0x100); + // Code at 0x100: sub rsp, 0x28; nop; ret + mem[0x100] = '\x48'; mem[0x101] = '\x83'; mem[0x102] = '\xec'; + mem[0x103] = '\x28'; mem[0x104] = '\x90'; mem[0x105] = '\xc3'; + + BufferProvider prov(mem); + + // WRONG: read from node.offset=0 (root's vptr value, not the func ptr) + uint64_t wrongPtrVal = prov.readU64(0); + QCOMPARE(wrongPtrVal, kBase + 0x80); // This is the vtable addr, not a function! + + // RIGHT: read from composed address (vtable + 0) + uint64_t rightPtrVal = prov.readU64(0x80); + QCOMPARE(rightPtrVal, kBase + 0x100); // This IS the function address + + // Disassemble the RIGHT target + QByteArray rightCode = prov.readBytes(0x100, 128); + QString rightAsm = disassemble(rightCode, kBase + 0x100, 64, 128); + QStringList rightLines = rightAsm.split('\n'); + QVERIFY(rightLines.size() >= 3); + QCOMPARE(mnemonic(rightLines[0]), QStringLiteral("sub rsp, 0x28")); + QCOMPARE(mnemonic(rightLines[1]), QStringLiteral("nop")); + QCOMPARE(mnemonic(rightLines[2]), QStringLiteral("ret")); + + // Disassemble the WRONG target (vtable data, not code!) + QByteArray wrongCode = prov.readBytes(0x80, 128); + QString wrongAsm = disassemble(wrongCode, kBase + 0x80, 64, 128); + // The wrong bytes are the vtable entries (pointer values), + // which decode as garbage instructions, not sub/nop/ret + QVERIFY2(!wrongAsm.contains("sub rsp"), + qPrintable("Wrong address should NOT produce sub rsp: " + wrongAsm)); + } + + void testHoverFlow_fullSimulation() { + // Full simulation of the hover flow as implemented in editor.cpp: + // + // 1. Compose the tree to get LineMeta with correct offsetAddr + // 2. For each FuncPtr64 line, read pointer value from snapshot/provider + // using lm.offsetAddr - baseAddress (composed address) + // 3. Read code bytes from the REAL provider using ptrVal - baseAddress + // (the real provider can read any process address; snapshot cannot) + // 4. Disassemble the code bytes + // + // The key distinction: step 2 reads from composed tree addresses (in + // the snapshot), step 3 reads from arbitrary code addresses (needs + // the real provider, not snapshot). + + const uint64_t kBase = 0x7FF600000000ULL; + QByteArray mem(8192, '\0'); + auto w64 = [&](int off, uint64_t val) { + memcpy(mem.data() + off, &val, 8); + }; + + // Layout: + // [0x000] Root struct: __vptr -> vtable at kBase + 0x100 + // [0x100] VTable: func0 -> kBase + 0x1000, func1 -> kBase + 0x1800 + // [0x1000] func0 code: push rbp; mov rbp, rsp; sub rsp, 0x20; ret + // [0x1800] func1 code: xor eax, eax; ret + w64(0x000, kBase + 0x100); // __vptr + w64(0x100, kBase + 0x1000); // vtable[0] + w64(0x108, kBase + 0x1800); // vtable[1] + // func0 code + memcpy(mem.data() + 0x1000, "\x55\x48\x89\xe5\x48\x83\xec\x20\xc3", 9); + // func1 code + memcpy(mem.data() + 0x1800, "\x31\xc0\xc3", 3); + + // This provider represents the real process memory. + // In production, this is the ProcessMemoryProvider that reads via + // ReadProcessMemory at m_base + addr. + BufferProvider realProv(mem); + + // Build a snapshot that only contains tree-data pages (like the + // async refresh does). The snapshot does NOT contain function code pages. + // This simulates the real scenario where SnapshotProvider only has + // pages for the root struct and pointer-expanded structs. + QByteArray snapData(0x200, '\0'); // only pages for root + vtable + memcpy(snapData.data(), mem.constData(), 0x200); + BufferProvider snapProv(snapData); + + // Build node tree + NodeTree tree; + tree.baseAddress = kBase; + + Node root; root.kind = NodeKind::Struct; root.name = "Obj"; + root.parentId = 0; root.offset = 0; + int ri = tree.addNode(root); + uint64_t rootId = tree.nodes[ri].id; + + Node vtDef; vtDef.kind = NodeKind::Struct; vtDef.name = "VTable"; + vtDef.parentId = 0; vtDef.offset = 0x2000; + int vti = tree.addNode(vtDef); + uint64_t vtId = tree.nodes[vti].id; + + Node fp0; fp0.kind = NodeKind::FuncPtr64; fp0.name = "func0"; + fp0.parentId = vtId; fp0.offset = 0; + tree.addNode(fp0); + Node fp1; fp1.kind = NodeKind::FuncPtr64; fp1.name = "func1"; + fp1.parentId = vtId; fp1.offset = 8; + tree.addNode(fp1); + + Node vptr; vptr.kind = NodeKind::Pointer64; vptr.name = "__vptr"; + vptr.parentId = rootId; vptr.offset = 0; vptr.refId = vtId; + tree.addNode(vptr); + + // Compose with the snapshot (like production: compose uses snapshot) + ComposeResult result = compose(tree, snapProv); + + // Find expanded FuncPtr64 lines + for (int i = 0; i < result.meta.size(); i++) { + const LineMeta& lm = result.meta[i]; + if (lm.nodeKind != NodeKind::FuncPtr64 || lm.lineKind != LineKind::Field) + continue; + if (lm.offsetAddr < kBase + 0x100 || lm.offsetAddr >= kBase + 0x200) + continue; // skip standalone VTable definition entries + + // --- Hover step 1: read pointer value from snapshot --- + uint64_t provAddr = lm.offsetAddr - tree.baseAddress; + // The snapshot has this data (vtable pages are in it) + QVERIFY2(snapProv.isReadable(provAddr, 8), + qPrintable(QString("Snapshot should have vtable page at %1") + .arg(provAddr, 0, 16))); + uint64_t ptrVal = snapProv.readU64(provAddr); + QVERIFY2(ptrVal != 0, "Function pointer should not be zero"); + + // --- Hover step 2: read code from REAL provider --- + // The snapshot does NOT have the code pages: + uint64_t codeAddr = ptrVal - tree.baseAddress; + QVERIFY2(!snapProv.isReadable(codeAddr, 1), + "Snapshot should NOT have function code pages"); + // But the real provider does: + QByteArray codeBytes(128, Qt::Uninitialized); + bool readOk = realProv.read(codeAddr, codeBytes.data(), 128); + QVERIFY2(readOk, "Real provider should be able to read code bytes"); + + // --- Hover step 3: disassemble --- + QString asm_ = disassemble(codeBytes, ptrVal, 64, 128); + QVERIFY2(!asm_.isEmpty(), qPrintable("Empty disasm for line " + QString::number(i))); + + QStringList lines = asm_.split('\n'); + const Node& node = tree.nodes[lm.nodeIdx]; + if (node.name == "func0") { + QVERIFY(lines.size() >= 4); + QCOMPARE(mnemonic(lines[0]), QStringLiteral("push rbp")); + QCOMPARE(mnemonic(lines[1]), QStringLiteral("mov rbp, rsp")); + QCOMPARE(mnemonic(lines[2]), QStringLiteral("sub rsp, 0x20")); + QCOMPARE(mnemonic(lines[3]), QStringLiteral("ret")); + } else if (node.name == "func1") { + QVERIFY(lines.size() >= 2); + QCOMPARE(mnemonic(lines[0]), QStringLiteral("xor eax, eax")); + QCOMPARE(mnemonic(lines[1]), QStringLiteral("ret")); + } + } + } +}; + +QTEST_MAIN(TestDisasm) +#include "test_disasm.moc" diff --git a/third_party/fadec/.build.yml b/third_party/fadec/.build.yml new file mode 100644 index 0000000..0f6334d --- /dev/null +++ b/third_party/fadec/.build.yml @@ -0,0 +1,16 @@ +image: alpine/edge +sources: +- https://git.sr.ht/~aengelke/fadec +packages: +- meson +tasks: +- build: | + mkdir fadec-build1 + meson fadec-build1 fadec + ninja -C fadec-build1 + ninja -C fadec-build1 test + # Complete test with encode2 API. + mkdir fadec-build2 + meson fadec-build2 fadec -Dwith_encode2=true + ninja -C fadec-build2 + ninja -C fadec-build2 test diff --git a/third_party/fadec/.github/workflows/ci.yml b/third_party/fadec/.github/workflows/ci.yml new file mode 100644 index 0000000..6bf51b5 --- /dev/null +++ b/third_party/fadec/.github/workflows/ci.yml @@ -0,0 +1,51 @@ +name: CI + +on: [push] + +jobs: + build-linux: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - name: Install dependencies + run: sudo apt install -y ninja-build meson + - name: Configure + run: mkdir build; CC=clang CXX=clang++ meson -Dbuildtype=debugoptimized -Dwith_encode2=true build + - name: Build + run: ninja -v -C build + - name: Test + run: meson test -v -C build + build-linux-cmake: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - name: Install dependencies + run: sudo apt install -y ninja-build cmake + - name: Configure + run: CC=clang CXX=clang++ cmake -B build -G Ninja -DFADEC_ENCODE2=ON + - name: Build + run: cmake --build build -v + - name: Test + run: ctest --test-dir build -V + build-windows: + runs-on: windows-latest + steps: + - uses: actions/checkout@v4 + - name: Install dependencies + run: pip install ninja meson + - name: Configure + run: mkdir build; meson setup --vsenv -Dbuildtype=debugoptimized -Dwith_encode2=true build + - name: Build + run: meson compile -v -C build + - name: Test + run: meson test -v -C build + build-windows-cmake: + runs-on: windows-latest + steps: + - uses: actions/checkout@v4 + - name: Configure + run: cmake -B build -DFADEC_ENCODE2=ON + - name: Build + run: cmake --build build -v + - name: Test + run: ctest --test-dir build -V -C Debug diff --git a/third_party/fadec/.gitignore b/third_party/fadec/.gitignore new file mode 100644 index 0000000..84c048a --- /dev/null +++ b/third_party/fadec/.gitignore @@ -0,0 +1 @@ +/build/ diff --git a/third_party/fadec/CMakeLists.txt b/third_party/fadec/CMakeLists.txt new file mode 100644 index 0000000..4f27a59 --- /dev/null +++ b/third_party/fadec/CMakeLists.txt @@ -0,0 +1,109 @@ +cmake_minimum_required(VERSION 3.23) + +project(fadec LANGUAGES C) +enable_testing() + +# TODO: make this actually optional +enable_language(CXX OPTIONAL) + +# Options +set(FADEC_ARCHMODE "both" CACHE STRING "Support only 32-bit x86, 64-bit x86 or both") +set_property(CACHE FADEC_ARCHMODE PROPERTY STRINGS both only32 only64) + +option(FADEC_UNDOC "Include undocumented instructions" FALSE) +option(FADEC_DECODE "Include support for decoding" TRUE) +option(FADEC_ENCODE "Include support for encoding" TRUE) +option(FADEC_ENCODE2 "Include support for new encoding API" FALSE) + +set(CMAKE_C_STANDARD 11) + +if (MSVC) + add_compile_options(/W4 -D_CRT_SECURE_NO_WARNINGS /wd4018 /wd4146 /wd4244 /wd4245 /wd4267 /wd4310) + add_compile_options($<$:-Zc:preprocessor>) +else() + add_compile_options(-Wall -Wextra -Wpedantic -Wno-overlength-strings) +endif() + +find_package(Python3 3.9 REQUIRED) + +add_library(fadec) +add_library(fadec::fadec ALIAS fadec) +set_target_properties(fadec PROPERTIES + LINKER_LANGUAGE C +) + +set(GEN_ARGS "") +if (NOT FADEC_ARCHMODE STREQUAL "only64") + list(APPEND GEN_ARGS "--32") +endif () +if (NOT FADEC_ARCHMODE STREQUAL "only32") + list(APPEND GEN_ARGS "--64") +endif () +if (FADEC_UNDOC) + list(APPEND GEN_ARGS "--with-undoc") +endif () + +file(MAKE_DIRECTORY "${CMAKE_CURRENT_BINARY_DIR}/include") + +function(fadec_component) + cmake_parse_arguments(ARG "" "NAME" "HEADERS;SOURCES" ${ARGN}) + + set(PRIV_INC ${CMAKE_CURRENT_BINARY_DIR}/include/fadec-${ARG_NAME}-private.inc) + set(PUB_INC ${CMAKE_CURRENT_BINARY_DIR}/include/fadec-${ARG_NAME}-public.inc) + + add_custom_command( + OUTPUT ${PRIV_INC} ${PUB_INC} + COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/parseinstrs.py ${ARG_NAME} ${CMAKE_CURRENT_SOURCE_DIR}/instrs.txt + ${PUB_INC} ${PRIV_INC} ${GEN_ARGS} + DEPENDS instrs.txt parseinstrs.py + COMMENT "Building table for ${ARG_NAME}" + ) + + list(APPEND FADEC_HEADERS ${PUB_INC}) + target_sources(fadec PRIVATE + ${ARG_SOURCES} + + PUBLIC + FILE_SET HEADERS + BASE_DIRS . + FILES + ${ARG_HEADERS} + + PUBLIC + FILE_SET generated_public TYPE HEADERS + BASE_DIRS ${CMAKE_CURRENT_BINARY_DIR}/include + FILES + ${PUB_INC} + + PRIVATE + FILE_SET generated_private TYPE HEADERS + BASE_DIRS ${CMAKE_CURRENT_BINARY_DIR}/include + FILES + ${PRIV_INC} + ) + + add_executable(fadec-${ARG_NAME}-test ${ARG_NAME}-test.c) + target_link_libraries(fadec-${ARG_NAME}-test PRIVATE fadec) + add_test(NAME ${ARG_NAME} COMMAND fadec-${ARG_NAME}-test) + + if (CMAKE_CXX_COMPILER AND ${ARG_NAME} STREQUAL "encode2") + add_executable(fadec-${ARG_NAME}-test-cpp ${ARG_NAME}-test.cc) + target_link_libraries(fadec-${ARG_NAME}-test-cpp PRIVATE fadec) + add_test(NAME ${ARG_NAME}-cpp COMMAND fadec-${ARG_NAME}-test-cpp) + endif() +endfunction() + +if (FADEC_DECODE) + fadec_component(NAME decode SOURCES decode.c format.c HEADERS fadec.h) +endif () +if (FADEC_ENCODE) + fadec_component(NAME encode SOURCES encode.c HEADERS fadec-enc.h) +endif () +if (FADEC_ENCODE2) + fadec_component(NAME encode2 SOURCES encode2.c HEADERS fadec-enc2.h) +endif () + +install(TARGETS fadec EXPORT fadec + LIBRARY + ARCHIVE + FILE_SET HEADERS FILE_SET generated_public) diff --git a/third_party/fadec/LICENSE b/third_party/fadec/LICENSE new file mode 100644 index 0000000..0f97558 --- /dev/null +++ b/third_party/fadec/LICENSE @@ -0,0 +1,28 @@ +Copyright (c) 2018, Alexis Engelke +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/third_party/fadec/README.md b/third_party/fadec/README.md new file mode 100644 index 0000000..eea732b --- /dev/null +++ b/third_party/fadec/README.md @@ -0,0 +1,184 @@ +# Fadec — Fast Decoder for x86-32 and x86-64 and Encoder for x86-64 + +Fadec is a fast and lightweight decoder for x86-32 and x86-64. To meet the goal of speed, lookup tables are used to map the opcode the (internal) description of the instruction encoding. This table currently has a size of roughly 37 kiB (for 32/64-bit combined). + +Fadec-Enc (or Faenc) is a small, lightweight and easy-to-use encoder, currently for x86-64 only. + +## Key features + +> **Q: Why not just use any other decoding/encoding library available out there?** +> +> A: I needed to embed a small and fast decoder in a project for a freestanding environment (i.e., no libc). Further, only very few plain encoding libraries are available for x86-64; and most of them are large or make heavy use of external dependencies. + +- **Small size:** the entire library with the x86-64/32 decoder and the x86-64 encoder are only 95 kiB; for specific use cases, the size can be reduced even further (e.g., by dropping AVX-512). The main decode/encode routines are only a few hundreds lines of code. +- **Performance:** Fadec is significantly faster than libopcodes, Capstone, or Zydis due to the absence of high-level abstractions and the small lookup table. +- **Zero dependencies:** the entire library has no dependencies, even on the standard library, making it suitable for freestanding environments without a full libc or `malloc`-style memory allocation. +- **Correctness:** even corner cases should be handled correctly (if not, that's a bug), e.g., the order of prefixes, immediate sizes of jump instructions, the presence of the `lock` prefix, or properly handling VEX.W in 32-bit mode. + +All components of this library target the Intel 64 implementations of x86. While AMD64 is _mostly similar_, there are some minor differences (e.g. operand sizes for jump instructions, more instructions, `cr8` can be accessed with `lock` prefix, `f34190` is `xchg`, not `pause`) which are currently not handled. + +## Decoder Usage + +### Example +```c +uint8_t buffer[] = {0x49, 0x90}; +FdInstr instr; +// Decode from buffer into instr in 64-bit mode. +int ret = fd_decode(buffer, sizeof(buffer), 64, 0, &instr); +// ret<0 indicates an error, ret>0 the number of decoded bytes +// Relevant properties of instructions can now be queried using the FD_* macros. +// Or, we can format the instruction to a string buffer: +char fmtbuf[64]; +fd_format(&instr, fmtbuf, sizeof(fmtbuf)); +// fmtbuf now reads: "xchg r8, rax" +``` + +### API + +The API consists of two functions to decode and format instructions, as well as several accessor macros. A full documentation can be found in [fadec.h](fadec.h). Direct access of any structure fields is not recommended. + +- `int fd_decode(const uint8_t* buf, size_t len, int mode, uintptr_t address, FdInstr* out_instr)` + - Decode a single instruction. For internal performance reasons, note that: + - The decoded operand sizes are not always exact. However, the exact size can be reconstructed in all cases. + - An implicit `fwait` in FPU instructions is decoded as a separate instruction (matching the opcode layout in machine code). For example, `finit` is decoded as `FD_FWAIT` + `FD_FINIT` + - Return value: number of bytes used, or a negative value in case of an error. + - `buf`/`len`: buffer containing instruction bytes. At most 15 bytes will be read. If the instruction is longer than `len`, an error value is returned. + - `mode`: architecture mode, either `32` or `64`. + - `address`: set to `0`. (Obsolete use: virtual address of the decoded instruction.) + - `out_instr`: Pointer to the instruction buffer, might get written partially in case of an error. +- `void fd_format(const FdInstr* instr, char* buf, size_t len)` + - Format a single instruction to a human-readable format. + - `instr`: decoded instruction. + - `buf`/`len`: buffer for formatted instruction string +- Various accessor macros: see [fadec.h](fadec.h). + +## Encoder Usage + +The encoder has two API variants: "v1" has a single entry point (`fe_enc64`) and the instruction is specified as integer parameter. "v2" has one entry point per instruction. v2 is currently about 3x faster than v1, but also has much larger code size (v1: <10 kiB; v2: ~3 MiB) and takes much longer to compile. It is therefore off by default and can be enabled by passing `-Dwith_encode2=true` to Meson. Both variants are supported. + +### Example (API v1) + +```c +int failed = 0; +uint8_t buf[64]; +uint8_t* cur = buf; + +// xor eax, eax +failed |= fe_enc64(&cur, FE_XOR32rr, FE_AX, FE_AX); +// movzx ecx, byte ptr [rdi + 1*rax + 0] +failed |= fe_enc64(&cur, FE_MOVZXr32m8, FE_CX, FE_MEM(FE_DI, 1, FE_AX, 0)); +// test ecx, ecx +failed |= fe_enc64(&cur, FE_TEST32rr, FE_CX, FE_CX); +// jnz $ +// This will be replaced later; FE_JMPL enforces use of longest offset +uint8_t* fwd_jmp = cur; +failed |= fe_enc64(&cur, FE_JNZ|FE_JMPL, (intptr_t) cur); +uint8_t* loop_tgt = cur; +// add rax, rcx +failed |= fe_enc64(&cur, FE_ADD64rr, FE_AX, FE_CX); +// sub ecx, 1 +failed |= fe_enc64(&cur, FE_SUB32ri, FE_CX, 1); +// jnz loop_tgt +failed |= fe_enc64(&cur, FE_JNZ, (intptr_t) loop_tgt); +// (alternatively: fe_enc64(&cur, FE_Jcc|FE_CC_NZ, (intptr_t) loop_tgt).) +// Update previous jump to jump here. Note that we _must_ specify FE_JMPL too. +failed |= fe_enc64(&fwd_jmp, FE_JNZ|FE_JMPL, (intptr_t) cur); +// ret +failed |= fe_enc64(&cur, FE_RET); +// cur now points to the end of the buffer, failed indicates any failures. +``` + +### Example (API v2) + +```c +uint8_t buf[64]; +uint8_t* cur = buf; + +// xor eax, eax +cur += fe64_XOR32rr(cur, 0, FE_AX, FE_AX); +// movzx ecx, byte ptr [rdi + 1*rax + 0] +cur += fe64_MOVZXr32m8(cur, 0, FE_CX, FE_MEM(FE_DI, 1, FE_AX, 0)); +// test ecx, ecx +cur += fe64_TEST32rr(cur, 0, FE_CX, FE_CX); +// jnz $ +// This will be replaced later; FE_JMPL enforces use of longest offset +uint8_t* fwd_jmp = cur; +cur += fe64_JNZ(cur, FE_JMPL, cur); +uint8_t* loop_tgt = cur; +// add rax, rcx +cur += fe64_ADD64rr(cur, 0, FE_AX, FE_CX); +// sub ecx, 1 +cur += fe64_SUB32ri(cur, 0, FE_CX, 1); +// jnz loop_tgt +cur += fe64_JNZ(cur, 0, loop_tgt); +// (alternatively: fe64_Jcc(cur, FE_CC_NZ, loop_tgt).) +// Update previous jump to jump here. Note that we _must_ specify FE_JMPL too. +fe64_JNZ(fwd_jmp, FE_JMPL, cur); +// ret +cur += fe64_RET(cur, 0); +// cur now points to the end of the buffer +// errors are ignored, this example should not cause any :-) +``` + +### API v1 + +The API consists of one function to handle encode requests, as well as some macros. More information can be found in [fadec-enc.h](fadec-enc.h). Usage of internals like enum values is not recommended. + +- `int fe_enc64(uint8_t** buf, uint64_t mnem, int64_t operands...)` + - Encodes an instruction for x86-64 into `*buf`. EVEX-encoded instructions will transparently encode with the shorter VEX prefix where permitted. + - Return value: `0` on success, a negative value in error cases. + - `buf`: Pointer to the pointer to the instruction buffer. The pointer (`*buf`) will be advanced by the number of bytes written. The instruction buffer must have at least 15 bytes left. + - `mnem`: Instruction mnemonic to encode combined with extra flags: + - `FE_SEG(segreg)`: override segment to specified segment register. + - `FE_ADDR32`: override address size to 32-bit. + - `FE_JMPL`: use longest possible offset encoding, useful when jump target is not known. + - `FE_MASK(maskreg)`: specify non-zero mask register (1--7) for instructions that support masking (suffixed with `_mask` or `_maskz`) or require a mask (AVX-512 gather/scatter). + - `FE_RC_RN/RD/RU/RZ`: set rounding mode for instructions with static rounding control (suffixed `_er`). + - `FE_CC_O/NO/E/NE/...`: set condition code for instructions with unspecified condition code (`Jcc`, `SETcc`, `CMOVcc`, `CMPccXADD`). + - `operands...`: Up to 4 instruction operands. The operand kinds must match the requirements of the mnemonic. + - For register operands (`r`=non-mask register, `k`=mask register), use the register: `FE_AX`, `FE_AH`, `FE_XMM12`. + - For immediate operands (`i`=regular, `a`=absolute address), use the constant: `12`, `-0xbeef`. + - For memory operands (`m`=regular or `b`=broadcast), use: `FE_MEM(basereg,scale,indexreg,offset)`. Use `0` to specify _no register_. For RIP-relative addressing, the size of the instruction is added automatically. + - For offset operands (`o`), specify the target address. + +### API v2 + +The API consists of one function per instruction, as well as some macros. The API provides type safety for different register types as well as for memory operands (regular vs. VSIB). Besides a few details listed here, the usage is very similar to API v1. More information can be found in [fadec-enc2.h](fadec-enc2.h). Usage of internals like enum values is not recommended. + +- `int fe64_(uint8_t* buf, int flags, )` + - Encodes the specified instruction for x86-64 into `buf`. EVEX-encoded instructions will transparently encode with the shorter VEX prefix where permitted. + - Return value: `0` on failure, otherwise the instruction length. + - `buf`: Pointer to the instruction buffer. The instruction buffer must have at least 15 bytes left. Bytes beyond the returned instruction length can be overwritten. + - `flags`: combination of extra flags, default to `0`: + - `FE_SEG(segreg)`: override segment to specified segment register. + - `FE_ADDR32`: override address size to 32-bit. + - `FE_JMPL`: use longest possible offset encoding, useful when jump target is not known. + - `FE_RC_RN/RD/RU/RZ`: set rounding mode for instructions with static rounding control (suffixed `_er`). + - `FE_CC_O/NO/E/NE/...`: set condition code for instructions with unspecified condition code (`Jcc`, `SETcc`, `CMOVcc`, `CMPccXADD`). + - `FeRegMASK opmask` (instructions with opmask only): specify non-zero mask register (1--7) for instructions suffixed with `_mask`/`_maskz` and AVX-512 gather/scatter. + - `operands...`: up to four instruction operands. + - Registers have types `FeRegGP`/`FeRegXMM`/`FeRegMASK`/etc.; byte registers accepting high-byte operands also accept `FeRegGPH`. + - Immediate operands have an appropriately sized integer type. + - Memory operands use a `FeMem` (VSIB: `FeMemV`) structure, use the macro `FE_MEM(basereg,scale,indexreg,offset)` (VSIB: `FE_MEMV(...)`). Use `FE_NOREG` to specify _no register_. For RIP-relative addressing, the size of the instruction is added automatically. + - For offset operands (`o`), specify the target address relative to `buf`. +- `int fe64_NOP(uint8_t* buf, unsigned size)` + - Encode a series of `nop`s of `size` bytes, but at least emit one byte. This will use larger the `nop` encodings to reduce the number of instructions and is intended for filling padding. + +## Known issues +- Decoder/Encoder: register uniqueness constraints are not enforced. This affects: + - VSIB-encoded instructions: no vector register may be used more than once + - AMX instructions: no tile register may be used more than once + - AVX-512 complex FP16 multiplication: destination must be not be equal to a source register +- Prefixes for indirect jumps and calls are not properly decoded, e.g. `notrack`, `bnd`. +- Low test coverage. (Help needed.) +- No Python API. + +Some ISA extensions are not supported, often because they are deprecated or unsupported by recent hardware. These are unlikely to be implemented in the near future: + +- (Intel) MPX: Intel lists MPX as deprecated. +- (Intel) HLE prefixes `xacquire`/`xrelease`: Intel lists HLE as deprecated. The formatter for decoded instructions is able to reconstruct these in most cases, though. +- (Intel) Xeon Phi (KNC/KNL/KNM) extensions, including the MVEX prefix: the hardware is discontinued/no longer available. +- (AMD) XOP: unsupported by newer hardware. +- (AMD) FMA4: unsupported by newer hardware. + +If you find any other issues, please report a bug. Or, even better, send a patch fixing the issue. diff --git a/third_party/fadec/decode-test.c b/third_party/fadec/decode-test.c new file mode 100644 index 0000000..f8d80cc --- /dev/null +++ b/third_party/fadec/decode-test.c @@ -0,0 +1,3248 @@ + +#include +#include +#include +#include + +#include + + +static +void +print_hex(const uint8_t* buf, size_t len) +{ + for (size_t i = 0; i < len; i++) + printf("%02x", buf[i]); +} + +static +int +test(const void* buf, size_t buf_len, unsigned mode, const char* exp_fmt) +{ + FdInstr instr; + char fmt[128]; + + memset(fmt, 0, sizeof(fmt)); + int retval = fd_decode(buf, buf_len, mode, 0, &instr); + + if (retval == FD_ERR_INTERNAL) { + return 0; // not compiled with this arch-mode (32/64 bit) + } else if (retval == FD_ERR_PARTIAL) { + strcpy(fmt, "PARTIAL"); + } else if (retval == FD_ERR_UD) { + strcpy(fmt, "UD"); + } else { + fd_format(&instr, fmt, sizeof(fmt)); + } + + if ((retval < 0 || (unsigned) retval == buf_len)) { + if (!strcmp(fmt, exp_fmt)) + return 0; + // Consider 32/64 bit differences, e.g. for addressing mode. + const char* it = exp_fmt; + while ((it = (const char*) strchr(it, '@'))) { + if (fmt[it - exp_fmt] == (mode != 64 ? 'e' : 'r')) + fmt[it - exp_fmt] = '@'; + it++; + } + if (!strcmp(fmt, exp_fmt)) + return 0; + } + + printf("Failed case (%u-bit): ", mode); + print_hex(buf, buf_len); + printf("\n Exp (%2zu): %s", buf_len, exp_fmt); + printf("\n Got (%2d): %s\n", retval, fmt); + return -1; +} + +#define TEST1(mode, buf, exp_fmt) test(buf, sizeof(buf)-1, mode, exp_fmt) +#define TEST32(...) failed |= TEST1(32, __VA_ARGS__) +#define TEST64(...) failed |= TEST1(64, __VA_ARGS__) +#define TEST3264(buf, exp_fmt32, exp_fmt64) \ + failed |= TEST1(32, buf, exp_fmt32) | TEST1(64, buf, exp_fmt64) +#define TEST(...) failed |= TEST1(32, __VA_ARGS__) | TEST1(64, __VA_ARGS__) + +int +main(int argc, char** argv) +{ + (void) argc; (void) argv; + + int failed = 0; + + TEST("\x90", "nop"); + TEST("\xac", "lodsb"); + TEST3264("\x26\xac", "es lodsb", "lodsb"); + TEST3264("\x2e\xac", "cs lodsb", "lodsb"); + TEST3264("\x36\xac", "ss lodsb", "lodsb"); + TEST3264("\x3e\xac", "ds lodsb", "lodsb"); + TEST("\x64\xac", "fs lodsb"); + TEST("\x65\xac", "gs lodsb"); + TEST3264("\x2e\x2e\xac", "cs lodsb", "lodsb"); + TEST3264("\x2e\x26\xac", "es lodsb", "lodsb"); + TEST3264("\x26\x2e\xac", "cs lodsb", "lodsb"); + TEST3264("\x26\x65\xac", "gs lodsb", "gs lodsb"); + TEST3264("\x65\x26\xac", "es lodsb", "gs lodsb"); + TEST("\x01\x00", "add dword ptr [@ax], eax"); + TEST3264("\x26\x01\x00", "add dword ptr es:[eax], eax", "add dword ptr [rax], eax"); + TEST3264("\x2e\x01\x00", "add dword ptr cs:[eax], eax", "add dword ptr [rax], eax"); + TEST3264("\x36\x01\x00", "add dword ptr ss:[eax], eax", "add dword ptr [rax], eax"); + TEST3264("\x3e\x01\x00", "add dword ptr ds:[eax], eax", "add dword ptr [rax], eax"); + TEST("\x64\x01\x00", "add dword ptr fs:[@ax], eax"); + TEST("\x65\x01\x00", "add dword ptr gs:[@ax], eax"); + TEST("\x0f\x10\xc1", "movups xmm0, xmm1"); + TEST("\x66\x0f\x10\xc1", "movupd xmm0, xmm1"); + TEST("\xf2\x66\x0f\x10\xc1", "movsd xmm0, xmm1"); + TEST("\xf3\x66\x0f\x10\xc1", "movss xmm0, xmm1"); + TEST("\xf3\xf2\x66\x0f\x10\xc1", "movsd xmm0, xmm1"); + TEST("\xf2\x66\xf3\x66\x0f\x10\xc1", "movss xmm0, xmm1"); + + TEST64("\x48\x91", "xchg rcx, rax"); + TEST64("\x48\x26\x91", "xchg ecx, eax"); + TEST("\x90", "nop"); + TEST("\xf2\x90", "nop"); + TEST("\x66\x90", "nop"); // NB: could be xchg ax, ax + TEST("\x66\xf2\x90", "nop"); // NB: could be xchg ax, ax + TEST64("\x41\x90", "xchg r8d, eax"); + TEST64("\xf2\x41\x90", "xchg r8d, eax"); + TEST64("\x66\x41\x90", "xchg r8w, ax"); + TEST64("\x66\xf2\x41\x90", "xchg r8w, ax"); + TEST64("\x48\x90", "nop"); // NB: could be xchg rax, rax + TEST64("\xf2\x48\x90", "nop"); // NB: could be xchg rax, rax + TEST64("\x66\x48\x90", "nop"); // NB: could be xchg rax, rax + TEST64("\x66\xf2\x48\x90", "nop"); // NB: could be xchg rax, rax + TEST64("\x49\x90", "xchg r8, rax"); + TEST64("\xf2\x49\x90", "xchg r8, rax"); + TEST64("\x66\x49\x90", "xchg r8, rax"); + TEST64("\x66\xf2\x49\x90", "xchg r8, rax"); + TEST("\xf3\x90", "pause"); + TEST("\x66\xf3\x90", "pause"); + TEST64("\xf3\x41\x90", "pause"); // NB: xchg for AMD + TEST64("\x66\xf3\x41\x90", "pause"); // NB: xchg for AMD + TEST64("\xf3\x48\x90", "pause"); + TEST64("\x66\xf3\x48\x90", "pause"); + TEST64("\xf3\x49\x90", "pause"); // NB: xchg for AMD + TEST64("\x66\xf3\x49\x90", "pause"); // NB: xchg for AMD + TEST("\xf3\x91", "xchg ecx, eax"); + + TEST("\x0f\xc7\x0f", "cmpxchg8b qword ptr [@di]"); + TEST("\x66\x0f\xc7\x0f", "cmpxchg8b qword ptr [@di]"); // 66h is ignored + TEST64("\x48\x0f\xc7\x0f", "cmpxchg16b xmmword ptr [rdi]"); + TEST("\xf2\x0f\xc7\x0f", "cmpxchg8b qword ptr [@di]"); + TEST("\xf3\x0f\xc7\x0f", "cmpxchg8b qword ptr [@di]"); + TEST("\xf2\xf0\x0f\xc7\x0f", "xacquire lock cmpxchg8b qword ptr [@di]"); + TEST("\xf3\xf0\x0f\xc7\x0f", "xrelease lock cmpxchg8b qword ptr [@di]"); + TEST("\x87\x0f", "xchg dword ptr [@di], ecx"); + TEST("\xf2\x87\x0f", "xacquire xchg dword ptr [@di], ecx"); + TEST("\xf3\x87\x0f", "xrelease xchg dword ptr [@di], ecx"); + TEST("\xf2\xf0\x87\x0f", "xacquire lock xchg dword ptr [@di], ecx"); + TEST("\xf3\xf0\x87\x0f", "xrelease lock xchg dword ptr [@di], ecx"); + TEST("\xc6\x07\x12", "mov byte ptr [@di], 0x12"); + TEST("\xf2\xc6\x07\x12", "mov byte ptr [@di], 0x12"); // no xacquire + TEST("\xf3\xc6\x07\x12", "xrelease mov byte ptr [@di], 0x12"); + TEST("\x66\xc7\x07\x34\x12", "mov word ptr [@di], 0x1234"); + TEST("\x66\xf2\xc7\x07\x34\x12", "mov word ptr [@di], 0x1234"); // no xacquire + TEST("\x66\xf3\xc7\x07\x34\x12", "xrelease mov word ptr [@di], 0x1234"); + TEST64("\xf0\xff\xc0", "UD"); // lock with register operand is UD + TEST64("\xf0\xd0\x00", "UD"); // lock with rol is UD + TEST("\x66", "PARTIAL"); + TEST("\xf0", "PARTIAL"); + TEST("\x0f", "PARTIAL"); + TEST("\x0f\x38", "PARTIAL"); + TEST("\x0f\x3a", "PARTIAL"); + TEST("\x80", "PARTIAL"); + TEST("\x80\x04", "PARTIAL"); + TEST("\x80\x40", "PARTIAL"); + TEST("\x80\x80\x00\x00\x00", "PARTIAL"); + TEST("\xb0", "PARTIAL"); + TEST("\xb8", "PARTIAL"); + TEST("\xb8\x00", "PARTIAL"); + TEST("\xb8\x00\x00", "PARTIAL"); + TEST("\xb8\x00\x00\x00", "PARTIAL"); + TEST("\x0F\x01\x22", "smsw word ptr [@dx]"); + TEST64("\x48\x0F\x01\x22", "smsw word ptr [rdx]"); + TEST("\x66\x0F\x01\x22", "smsw word ptr [@dx]"); + TEST("\x0F\x01\xE2", "smsw edx"); + TEST("\x66\x0F\x01\xE2", "smsw dx"); + TEST64("\x66\x48\x0F\x01\xE2", "smsw rdx"); + TEST64("\xf2\x66\x0f\x01\x23", "smsw word ptr [rbx]"); + TEST("\x66\x0f\x20\x00", "mov @ax, cr0"); // mod=0, 66h + TEST("\xf3\x0f\x20\x00", "mov @ax, cr0"); // REP + TEST("\x0f\x20\xc8", "UD"); // cr1 + TEST("\x0f\x20\xd0", "mov @ax, cr2"); // cr2 + TEST64("\x48\x0f\x20\xd0", "mov rax, cr2"); // cr2 + REX.W + TEST("\x0f\x20\xd8", "mov @ax, cr3"); // cr3 + TEST("\x0f\x20\xe0", "mov @ax, cr4"); // cr4 + TEST3264("\x0f\x20\xe8", "UD", "UD"); // cr5 + TEST64("\x44\x0f\x20\x00", "mov rax, cr8"); // cr8 + TEST64("\x45\x0f\x20\x00", "mov r8, cr8"); // cr8 + TEST64("\x44\x0f\x20\x08", "UD"); // cr9 + TEST64("\x44\x0f\x21\x00", "UD"); // dr8 + TEST32("\xf0\x0f\x20\x00", "UD"); // LOCK + TEST("\x8c\xc0", "mov ax, es"); + TEST64("\x44\x8c\xc0", "mov ax, es"); + TEST64("\x44\x8c\xf0", "UD"); // no segment register 6 + TEST64("\x44\x8c\xf8", "UD"); // no segment register 7 + TEST("\x8e\xc0", "mov es, ax"); + TEST("\x8e\xc8", "UD"); // No mov cs, eax + TEST("\x0f\x1e\xc0", "nop eax, eax"); // reserved nop + TEST("\x0f\x1e\x04\x25\x01\x00\x00\x00", "nop dword ptr [0x1], eax"); // reserved nop + TEST64("\xf3\x4f\x0f\x1e\xfc", "nop r12, r15"); // reserved nop + TEST("\xd8\xc1", "fadd st(0), st(1)"); + TEST("\xdc\xc1", "fadd st(1), st(0)"); + TEST64("\x41\xd8\xc1", "fadd st(0), st(1)"); // REX.B ignored + TEST64("\xd9\xc9", "fxch st(1)"); + TEST64("\xd9\xd0", "fnop"); + TEST("\xdf\xe0", "fstsw ax"); + TEST64("\x41\xdf\xe0", "fstsw ax"); + + // ModRM Test cases + // reg + TEST("\x01\xc0", "add eax, eax"); + TEST("\x01\xc1", "add ecx, eax"); + TEST("\x01\xd0", "add eax, edx"); + TEST("\x01\xff", "add edi, edi"); + TEST64("\x41\x01\xd0", "add r8d, edx"); + TEST64("\x45\x01\xd0", "add r8d, r10d"); + TEST64("\x45\x01\xff", "add r15d, r15d"); + // [reg] + TEST("\x01\x00", "add dword ptr [@ax], eax"); + TEST("\x01\x08", "add dword ptr [@ax], ecx"); + TEST("\x01\x01", "add dword ptr [@cx], eax"); + TEST("\x01\x07", "add dword ptr [@di], eax"); + TEST("\x01\x38", "add dword ptr [@ax], edi"); + TEST("\x01\x04\x24", "add dword ptr [@sp], eax"); + TEST64("\x41\x01\x00", "add dword ptr [r8], eax"); + TEST64("\x44\x01\x08", "add dword ptr [rax], r9d"); + TEST64("\x45\x01\x00", "add dword ptr [r8], r8d"); + TEST64("\x41\x01\x07", "add dword ptr [r15], eax"); + TEST64("\x41\x01\x04\x24", "add dword ptr [r12], eax"); + // [disp32] + TEST32("\x01\x05\x01\x00\x00\x00", "add dword ptr [0x1], eax"); + TEST32("\x01\x05\xff\xff\xff\xff", "add dword ptr [0xffffffff], eax"); + TEST("\x01\x04\x25\x01\x00\x00\x00", "add dword ptr [0x1], eax"); + TEST3264("\x01\x04\x25\x00\x00\x00\x80", "add dword ptr [0x80000000], eax", "add dword ptr [0xffffffff80000000], eax"); + TEST64("\x41\x01\x04\x25\x01\x00\x00\x00", "add dword ptr [0x1], eax"); + TEST("\x01\x04\x25\x00\x00\x00\x00", "add dword ptr [0x0], eax"); + // [rip+disp32] + TEST64("\x01\x05\x01\x00\x00\x00", "add dword ptr [rip+0x1], eax"); + TEST64("\x41\x01\x05\x01\x00\x00\x00", "add dword ptr [rip+0x1], eax"); + TEST64("\x67\x01\x05\x01\x00\x00\x00", "add dword ptr [eip+0x1], eax"); + TEST64("\x67\x41\x01\x05\x01\x00\x00\x00", "add dword ptr [eip+0x1], eax"); + // [reg+disp32] + TEST("\x01\x80\x01\x00\x00\x00", "add dword ptr [@ax+0x1], eax"); + TEST("\x01\x80\x00\x00\x00\x80", "add dword ptr [@ax-0x80000000], eax"); + // [reg+eiz+disp32] + TEST("\x01\x84\x25\x01\x00\x00\x00", "add dword ptr [@bp+0x1], eax"); + // [reg+s*reg+disp32] + TEST64("\x42\x01\x84\x25\x01\x00\x00\x00", "add dword ptr [rbp+1*r12+0x1], eax"); + // [s*reg] + TEST("\x01\x04\x8d\x00\x00\x00\x00", "add dword ptr [4*@cx], eax"); + + // 32-bit+67 ModRM cases. reg=0 + TEST32("\x67\x01\x00", "add dword ptr [bx+1*si], eax"); + TEST32("\x67\x01\x01", "add dword ptr [bx+1*di], eax"); + TEST32("\x67\x01\x02", "add dword ptr [bp+1*si], eax"); + TEST32("\x67\x01\x03", "add dword ptr [bp+1*di], eax"); + TEST32("\x67\x01\x04", "add dword ptr [1*si], eax"); + TEST32("\x67\x01\x05", "add dword ptr [1*di], eax"); + TEST32("\x67\x01\x06\x11\x22", "add dword ptr [0x2211], eax"); + TEST32("\x67\x01\x06\xf0\xff", "add dword ptr [0xfff0], eax"); + TEST32("\x67\x01\x07", "add dword ptr [bx], eax"); + TEST32("\x67\x01\x40\x12", "add dword ptr [bx+1*si+0x12], eax"); + TEST32("\x67\x01\x40\x99", "add dword ptr [bx+1*si-0x67], eax"); + TEST32("\x67\x01\x41\x12", "add dword ptr [bx+1*di+0x12], eax"); + TEST32("\x67\x01\x41\x99", "add dword ptr [bx+1*di-0x67], eax"); + TEST32("\x67\x01\x42\x12", "add dword ptr [bp+1*si+0x12], eax"); + TEST32("\x67\x01\x42\x99", "add dword ptr [bp+1*si-0x67], eax"); + TEST32("\x67\x01\x43\x12", "add dword ptr [bp+1*di+0x12], eax"); + TEST32("\x67\x01\x43\x99", "add dword ptr [bp+1*di-0x67], eax"); + TEST32("\x67\x01\x44\x12", "add dword ptr [1*si+0x12], eax"); + TEST32("\x67\x01\x44\x99", "add dword ptr [1*si-0x67], eax"); + TEST32("\x67\x01\x45\x12", "add dword ptr [1*di+0x12], eax"); + TEST32("\x67\x01\x45\x99", "add dword ptr [1*di-0x67], eax"); + TEST32("\x67\x01\x46\x12", "add dword ptr [bp+0x12], eax"); + TEST32("\x67\x01\x46\x99", "add dword ptr [bp-0x67], eax"); + TEST32("\x67\x01\x47\x12", "add dword ptr [bx+0x12], eax"); + TEST32("\x67\x01\x47\x99", "add dword ptr [bx-0x67], eax"); + TEST32("\x67\x01\x80\x11\x22", "add dword ptr [bx+1*si+0x2211], eax"); + TEST32("\x67\x01\x80\xf0\xff", "add dword ptr [bx+1*si-0x10], eax"); + TEST32("\x67\x01\x81\x11\x22", "add dword ptr [bx+1*di+0x2211], eax"); + TEST32("\x67\x01\x81\xf0\xff", "add dword ptr [bx+1*di-0x10], eax"); + TEST32("\x67\x01\x82\x11\x22", "add dword ptr [bp+1*si+0x2211], eax"); + TEST32("\x67\x01\x82\xf0\xff", "add dword ptr [bp+1*si-0x10], eax"); + TEST32("\x67\x01\x83\x11\x22", "add dword ptr [bp+1*di+0x2211], eax"); + TEST32("\x67\x01\x83\xf0\xff", "add dword ptr [bp+1*di-0x10], eax"); + TEST32("\x67\x01\x84\x11\x22", "add dword ptr [1*si+0x2211], eax"); + TEST32("\x67\x01\x84\xf0\xff", "add dword ptr [1*si-0x10], eax"); + TEST32("\x67\x01\x85\x11\x22", "add dword ptr [1*di+0x2211], eax"); + TEST32("\x67\x01\x85\xf0\xff", "add dword ptr [1*di-0x10], eax"); + TEST32("\x67\x01\x86\x11\x22", "add dword ptr [bp+0x2211], eax"); + TEST32("\x67\x01\x86\xf0\xff", "add dword ptr [bp-0x10], eax"); + TEST32("\x67\x01\x87\x11\x22", "add dword ptr [bx+0x2211], eax"); + TEST32("\x67\x01\x87\xf0\xff", "add dword ptr [bx-0x10], eax"); + TEST32("\x67\x01", "PARTIAL"); + TEST32("\x67\x01\x47", "PARTIAL"); + TEST32("\x67\x01\x80", "PARTIAL"); + TEST32("\x67\x01\x80\x11", "PARTIAL"); + + // 32-bit, 64-bit and 64-bit+67 ModRM+SIB cases. scale=2, reg=0 + TEST("\x01\x00", "add dword ptr [@ax], eax"); + TEST64("\x67\x01\x00", "add dword ptr [eax], eax"); + TEST("\x01\x01", "add dword ptr [@cx], eax"); + TEST64("\x67\x01\x01", "add dword ptr [ecx], eax"); + TEST("\x01\x02", "add dword ptr [@dx], eax"); + TEST64("\x67\x01\x02", "add dword ptr [edx], eax"); + TEST("\x01\x03", "add dword ptr [@bx], eax"); + TEST64("\x67\x01\x03", "add dword ptr [ebx], eax"); + TEST("\x01\x04\x80", "add dword ptr [@ax+4*@ax], eax"); + TEST64("\x67\x01\x04\x80", "add dword ptr [eax+4*eax], eax"); + TEST("\x01\x04\x81", "add dword ptr [@cx+4*@ax], eax"); + TEST64("\x67\x01\x04\x81", "add dword ptr [ecx+4*eax], eax"); + TEST("\x01\x04\x82", "add dword ptr [@dx+4*@ax], eax"); + TEST64("\x67\x01\x04\x82", "add dword ptr [edx+4*eax], eax"); + TEST("\x01\x04\x83", "add dword ptr [@bx+4*@ax], eax"); + TEST64("\x67\x01\x04\x83", "add dword ptr [ebx+4*eax], eax"); + TEST("\x01\x04\x84", "add dword ptr [@sp+4*@ax], eax"); + TEST64("\x67\x01\x04\x84", "add dword ptr [esp+4*eax], eax"); + TEST("\x01\x04\x85\x11\x22\x33\x44", "add dword ptr [4*@ax+0x44332211], eax"); + TEST64("\x67\x01\x04\x85\x11\x22\x33\x44", "add dword ptr [4*eax+0x44332211], eax"); + TEST("\x01\x04\x86", "add dword ptr [@si+4*@ax], eax"); + TEST64("\x67\x01\x04\x86", "add dword ptr [esi+4*eax], eax"); + TEST("\x01\x04\x87", "add dword ptr [@di+4*@ax], eax"); + TEST64("\x67\x01\x04\x87", "add dword ptr [edi+4*eax], eax"); + TEST("\x01\x04\x88", "add dword ptr [@ax+4*@cx], eax"); + TEST64("\x67\x01\x04\x88", "add dword ptr [eax+4*ecx], eax"); + TEST("\x01\x04\x89", "add dword ptr [@cx+4*@cx], eax"); + TEST64("\x67\x01\x04\x89", "add dword ptr [ecx+4*ecx], eax"); + TEST("\x01\x04\x8a", "add dword ptr [@dx+4*@cx], eax"); + TEST64("\x67\x01\x04\x8a", "add dword ptr [edx+4*ecx], eax"); + TEST("\x01\x04\x8b", "add dword ptr [@bx+4*@cx], eax"); + TEST64("\x67\x01\x04\x8b", "add dword ptr [ebx+4*ecx], eax"); + TEST("\x01\x04\x8c", "add dword ptr [@sp+4*@cx], eax"); + TEST64("\x67\x01\x04\x8c", "add dword ptr [esp+4*ecx], eax"); + TEST("\x01\x04\x8d\x11\x22\x33\x44", "add dword ptr [4*@cx+0x44332211], eax"); + TEST64("\x67\x01\x04\x8d\x11\x22\x33\x44", "add dword ptr [4*ecx+0x44332211], eax"); + TEST("\x01\x04\x8e", "add dword ptr [@si+4*@cx], eax"); + TEST64("\x67\x01\x04\x8e", "add dword ptr [esi+4*ecx], eax"); + TEST("\x01\x04\x8f", "add dword ptr [@di+4*@cx], eax"); + TEST64("\x67\x01\x04\x8f", "add dword ptr [edi+4*ecx], eax"); + TEST("\x01\x04\x90", "add dword ptr [@ax+4*@dx], eax"); + TEST64("\x67\x01\x04\x90", "add dword ptr [eax+4*edx], eax"); + TEST("\x01\x04\x91", "add dword ptr [@cx+4*@dx], eax"); + TEST64("\x67\x01\x04\x91", "add dword ptr [ecx+4*edx], eax"); + TEST("\x01\x04\x92", "add dword ptr [@dx+4*@dx], eax"); + TEST64("\x67\x01\x04\x92", "add dword ptr [edx+4*edx], eax"); + TEST("\x01\x04\x93", "add dword ptr [@bx+4*@dx], eax"); + TEST64("\x67\x01\x04\x93", "add dword ptr [ebx+4*edx], eax"); + TEST("\x01\x04\x94", "add dword ptr [@sp+4*@dx], eax"); + TEST64("\x67\x01\x04\x94", "add dword ptr [esp+4*edx], eax"); + TEST("\x01\x04\x95\x11\x22\x33\x44", "add dword ptr [4*@dx+0x44332211], eax"); + TEST64("\x67\x01\x04\x95\x11\x22\x33\x44", "add dword ptr [4*edx+0x44332211], eax"); + TEST("\x01\x04\x96", "add dword ptr [@si+4*@dx], eax"); + TEST64("\x67\x01\x04\x96", "add dword ptr [esi+4*edx], eax"); + TEST("\x01\x04\x97", "add dword ptr [@di+4*@dx], eax"); + TEST64("\x67\x01\x04\x97", "add dword ptr [edi+4*edx], eax"); + TEST("\x01\x04\x98", "add dword ptr [@ax+4*@bx], eax"); + TEST64("\x67\x01\x04\x98", "add dword ptr [eax+4*ebx], eax"); + TEST("\x01\x04\x99", "add dword ptr [@cx+4*@bx], eax"); + TEST64("\x67\x01\x04\x99", "add dword ptr [ecx+4*ebx], eax"); + TEST("\x01\x04\x9a", "add dword ptr [@dx+4*@bx], eax"); + TEST64("\x67\x01\x04\x9a", "add dword ptr [edx+4*ebx], eax"); + TEST("\x01\x04\x9b", "add dword ptr [@bx+4*@bx], eax"); + TEST64("\x67\x01\x04\x9b", "add dword ptr [ebx+4*ebx], eax"); + TEST("\x01\x04\x9c", "add dword ptr [@sp+4*@bx], eax"); + TEST64("\x67\x01\x04\x9c", "add dword ptr [esp+4*ebx], eax"); + TEST("\x01\x04\x9d\x11\x22\x33\x44", "add dword ptr [4*@bx+0x44332211], eax"); + TEST64("\x67\x01\x04\x9d\x11\x22\x33\x44", "add dword ptr [4*ebx+0x44332211], eax"); + TEST("\x01\x04\x9e", "add dword ptr [@si+4*@bx], eax"); + TEST64("\x67\x01\x04\x9e", "add dword ptr [esi+4*ebx], eax"); + TEST("\x01\x04\x9f", "add dword ptr [@di+4*@bx], eax"); + TEST64("\x67\x01\x04\x9f", "add dword ptr [edi+4*ebx], eax"); + TEST("\x01\x04\xa0", "add dword ptr [@ax], eax"); + TEST64("\x67\x01\x04\xa0", "add dword ptr [eax], eax"); + TEST("\x01\x04\xa1", "add dword ptr [@cx], eax"); + TEST64("\x67\x01\x04\xa1", "add dword ptr [ecx], eax"); + TEST("\x01\x04\xa2", "add dword ptr [@dx], eax"); + TEST64("\x67\x01\x04\xa2", "add dword ptr [edx], eax"); + TEST("\x01\x04\xa3", "add dword ptr [@bx], eax"); + TEST64("\x67\x01\x04\xa3", "add dword ptr [ebx], eax"); + TEST("\x01\x04\xa4", "add dword ptr [@sp], eax"); + TEST64("\x67\x01\x04\xa4", "add dword ptr [esp], eax"); + TEST3264("\x01\x04\xa5\x11\x22\x33\x44", "add dword ptr [0x44332211], eax", "add dword ptr [0x44332211], eax"); + TEST64("\x67\x01\x04\xa5\x11\x22\x33\x44", "add dword ptr [0x44332211], eax"); + TEST("\x01\x04\xa6", "add dword ptr [@si], eax"); + TEST64("\x67\x01\x04\xa6", "add dword ptr [esi], eax"); + TEST("\x01\x04\xa7", "add dword ptr [@di], eax"); + TEST64("\x67\x01\x04\xa7", "add dword ptr [edi], eax"); + TEST("\x01\x04\xa8", "add dword ptr [@ax+4*@bp], eax"); + TEST64("\x67\x01\x04\xa8", "add dword ptr [eax+4*ebp], eax"); + TEST("\x01\x04\xa9", "add dword ptr [@cx+4*@bp], eax"); + TEST64("\x67\x01\x04\xa9", "add dword ptr [ecx+4*ebp], eax"); + TEST("\x01\x04\xaa", "add dword ptr [@dx+4*@bp], eax"); + TEST64("\x67\x01\x04\xaa", "add dword ptr [edx+4*ebp], eax"); + TEST("\x01\x04\xab", "add dword ptr [@bx+4*@bp], eax"); + TEST64("\x67\x01\x04\xab", "add dword ptr [ebx+4*ebp], eax"); + TEST("\x01\x04\xac", "add dword ptr [@sp+4*@bp], eax"); + TEST64("\x67\x01\x04\xac", "add dword ptr [esp+4*ebp], eax"); + TEST("\x01\x04\xad\x11\x22\x33\x44", "add dword ptr [4*@bp+0x44332211], eax"); + TEST64("\x67\x01\x04\xad\x11\x22\x33\x44", "add dword ptr [4*ebp+0x44332211], eax"); + TEST("\x01\x04\xae", "add dword ptr [@si+4*@bp], eax"); + TEST64("\x67\x01\x04\xae", "add dword ptr [esi+4*ebp], eax"); + TEST("\x01\x04\xaf", "add dword ptr [@di+4*@bp], eax"); + TEST64("\x67\x01\x04\xaf", "add dword ptr [edi+4*ebp], eax"); + TEST("\x01\x04\xb0", "add dword ptr [@ax+4*@si], eax"); + TEST64("\x67\x01\x04\xb0", "add dword ptr [eax+4*esi], eax"); + TEST("\x01\x04\xb1", "add dword ptr [@cx+4*@si], eax"); + TEST64("\x67\x01\x04\xb1", "add dword ptr [ecx+4*esi], eax"); + TEST("\x01\x04\xb2", "add dword ptr [@dx+4*@si], eax"); + TEST64("\x67\x01\x04\xb2", "add dword ptr [edx+4*esi], eax"); + TEST("\x01\x04\xb3", "add dword ptr [@bx+4*@si], eax"); + TEST64("\x67\x01\x04\xb3", "add dword ptr [ebx+4*esi], eax"); + TEST("\x01\x04\xb4", "add dword ptr [@sp+4*@si], eax"); + TEST64("\x67\x01\x04\xb4", "add dword ptr [esp+4*esi], eax"); + TEST("\x01\x04\xb5\x11\x22\x33\x44", "add dword ptr [4*@si+0x44332211], eax"); + TEST64("\x67\x01\x04\xb5\x11\x22\x33\x44", "add dword ptr [4*esi+0x44332211], eax"); + TEST("\x01\x04\xb6", "add dword ptr [@si+4*@si], eax"); + TEST64("\x67\x01\x04\xb6", "add dword ptr [esi+4*esi], eax"); + TEST("\x01\x04\xb7", "add dword ptr [@di+4*@si], eax"); + TEST64("\x67\x01\x04\xb7", "add dword ptr [edi+4*esi], eax"); + TEST("\x01\x04\xb8", "add dword ptr [@ax+4*@di], eax"); + TEST64("\x67\x01\x04\xb8", "add dword ptr [eax+4*edi], eax"); + TEST("\x01\x04\xb9", "add dword ptr [@cx+4*@di], eax"); + TEST64("\x67\x01\x04\xb9", "add dword ptr [ecx+4*edi], eax"); + TEST("\x01\x04\xba", "add dword ptr [@dx+4*@di], eax"); + TEST64("\x67\x01\x04\xba", "add dword ptr [edx+4*edi], eax"); + TEST("\x01\x04\xbb", "add dword ptr [@bx+4*@di], eax"); + TEST64("\x67\x01\x04\xbb", "add dword ptr [ebx+4*edi], eax"); + TEST("\x01\x04\xbc", "add dword ptr [@sp+4*@di], eax"); + TEST64("\x67\x01\x04\xbc", "add dword ptr [esp+4*edi], eax"); + TEST("\x01\x04\xbd\x11\x22\x33\x44", "add dword ptr [4*@di+0x44332211], eax"); + TEST64("\x67\x01\x04\xbd\x11\x22\x33\x44", "add dword ptr [4*edi+0x44332211], eax"); + TEST("\x01\x04\xbe", "add dword ptr [@si+4*@di], eax"); + TEST64("\x67\x01\x04\xbe", "add dword ptr [esi+4*edi], eax"); + TEST("\x01\x04\xbf", "add dword ptr [@di+4*@di], eax"); + TEST64("\x67\x01\x04\xbf", "add dword ptr [edi+4*edi], eax"); + TEST3264("\x01\x05\x11\x22\x33\x44", "add dword ptr [0x44332211], eax", "add dword ptr [rip+0x44332211], eax"); + TEST64("\x67\x01\x05\x11\x22\x33\x44", "add dword ptr [eip+0x44332211], eax"); + TEST("\x01\x06", "add dword ptr [@si], eax"); + TEST64("\x67\x01\x06", "add dword ptr [esi], eax"); + TEST("\x01\x07", "add dword ptr [@di], eax"); + TEST64("\x67\x01\x07", "add dword ptr [edi], eax"); + TEST("\x01\x40\x99", "add dword ptr [@ax-0x67], eax"); + TEST64("\x67\x01\x40\x99", "add dword ptr [eax-0x67], eax"); + TEST("\x01\x41\x99", "add dword ptr [@cx-0x67], eax"); + TEST64("\x67\x01\x41\x99", "add dword ptr [ecx-0x67], eax"); + TEST("\x01\x42\x99", "add dword ptr [@dx-0x67], eax"); + TEST64("\x67\x01\x42\x99", "add dword ptr [edx-0x67], eax"); + TEST("\x01\x43\x99", "add dword ptr [@bx-0x67], eax"); + TEST64("\x67\x01\x43\x99", "add dword ptr [ebx-0x67], eax"); + TEST("\x01\x44\x80\x99", "add dword ptr [@ax+4*@ax-0x67], eax"); + TEST64("\x67\x01\x44\x80\x99", "add dword ptr [eax+4*eax-0x67], eax"); + TEST("\x01\x44\x81\x99", "add dword ptr [@cx+4*@ax-0x67], eax"); + TEST64("\x67\x01\x44\x81\x99", "add dword ptr [ecx+4*eax-0x67], eax"); + TEST("\x01\x44\x82\x99", "add dword ptr [@dx+4*@ax-0x67], eax"); + TEST64("\x67\x01\x44\x82\x99", "add dword ptr [edx+4*eax-0x67], eax"); + TEST("\x01\x44\x83\x99", "add dword ptr [@bx+4*@ax-0x67], eax"); + TEST64("\x67\x01\x44\x83\x99", "add dword ptr [ebx+4*eax-0x67], eax"); + TEST("\x01\x44\x84\x99", "add dword ptr [@sp+4*@ax-0x67], eax"); + TEST64("\x67\x01\x44\x84\x99", "add dword ptr [esp+4*eax-0x67], eax"); + TEST("\x01\x44\x85\x99", "add dword ptr [@bp+4*@ax-0x67], eax"); + TEST64("\x67\x01\x44\x85\x99", "add dword ptr [ebp+4*eax-0x67], eax"); + TEST("\x01\x44\x86\x99", "add dword ptr [@si+4*@ax-0x67], eax"); + TEST64("\x67\x01\x44\x86\x99", "add dword ptr [esi+4*eax-0x67], eax"); + TEST("\x01\x44\x87\x99", "add dword ptr [@di+4*@ax-0x67], eax"); + TEST64("\x67\x01\x44\x87\x99", "add dword ptr [edi+4*eax-0x67], eax"); + TEST("\x01\x44\x88\x99", "add dword ptr [@ax+4*@cx-0x67], eax"); + TEST64("\x67\x01\x44\x88\x99", "add dword ptr [eax+4*ecx-0x67], eax"); + TEST("\x01\x44\x89\x99", "add dword ptr [@cx+4*@cx-0x67], eax"); + TEST64("\x67\x01\x44\x89\x99", "add dword ptr [ecx+4*ecx-0x67], eax"); + TEST("\x01\x44\x8a\x99", "add dword ptr [@dx+4*@cx-0x67], eax"); + TEST64("\x67\x01\x44\x8a\x99", "add dword ptr [edx+4*ecx-0x67], eax"); + TEST("\x01\x44\x8b\x99", "add dword ptr [@bx+4*@cx-0x67], eax"); + TEST64("\x67\x01\x44\x8b\x99", "add dword ptr [ebx+4*ecx-0x67], eax"); + TEST("\x01\x44\x8c\x99", "add dword ptr [@sp+4*@cx-0x67], eax"); + TEST64("\x67\x01\x44\x8c\x99", "add dword ptr [esp+4*ecx-0x67], eax"); + TEST("\x01\x44\x8d\x99", "add dword ptr [@bp+4*@cx-0x67], eax"); + TEST64("\x67\x01\x44\x8d\x99", "add dword ptr [ebp+4*ecx-0x67], eax"); + TEST("\x01\x44\x8e\x99", "add dword ptr [@si+4*@cx-0x67], eax"); + TEST64("\x67\x01\x44\x8e\x99", "add dword ptr [esi+4*ecx-0x67], eax"); + TEST("\x01\x44\x8f\x99", "add dword ptr [@di+4*@cx-0x67], eax"); + TEST64("\x67\x01\x44\x8f\x99", "add dword ptr [edi+4*ecx-0x67], eax"); + TEST("\x01\x44\x90\x99", "add dword ptr [@ax+4*@dx-0x67], eax"); + TEST64("\x67\x01\x44\x90\x99", "add dword ptr [eax+4*edx-0x67], eax"); + TEST("\x01\x44\x91\x99", "add dword ptr [@cx+4*@dx-0x67], eax"); + TEST64("\x67\x01\x44\x91\x99", "add dword ptr [ecx+4*edx-0x67], eax"); + TEST("\x01\x44\x92\x99", "add dword ptr [@dx+4*@dx-0x67], eax"); + TEST64("\x67\x01\x44\x92\x99", "add dword ptr [edx+4*edx-0x67], eax"); + TEST("\x01\x44\x93\x99", "add dword ptr [@bx+4*@dx-0x67], eax"); + TEST64("\x67\x01\x44\x93\x99", "add dword ptr [ebx+4*edx-0x67], eax"); + TEST("\x01\x44\x94\x99", "add dword ptr [@sp+4*@dx-0x67], eax"); + TEST64("\x67\x01\x44\x94\x99", "add dword ptr [esp+4*edx-0x67], eax"); + TEST("\x01\x44\x95\x99", "add dword ptr [@bp+4*@dx-0x67], eax"); + TEST64("\x67\x01\x44\x95\x99", "add dword ptr [ebp+4*edx-0x67], eax"); + TEST("\x01\x44\x96\x99", "add dword ptr [@si+4*@dx-0x67], eax"); + TEST64("\x67\x01\x44\x96\x99", "add dword ptr [esi+4*edx-0x67], eax"); + TEST("\x01\x44\x97\x99", "add dword ptr [@di+4*@dx-0x67], eax"); + TEST64("\x67\x01\x44\x97\x99", "add dword ptr [edi+4*edx-0x67], eax"); + TEST("\x01\x44\x98\x99", "add dword ptr [@ax+4*@bx-0x67], eax"); + TEST64("\x67\x01\x44\x98\x99", "add dword ptr [eax+4*ebx-0x67], eax"); + TEST("\x01\x44\x99\x99", "add dword ptr [@cx+4*@bx-0x67], eax"); + TEST64("\x67\x01\x44\x99\x99", "add dword ptr [ecx+4*ebx-0x67], eax"); + TEST("\x01\x44\x9a\x99", "add dword ptr [@dx+4*@bx-0x67], eax"); + TEST64("\x67\x01\x44\x9a\x99", "add dword ptr [edx+4*ebx-0x67], eax"); + TEST("\x01\x44\x9b\x99", "add dword ptr [@bx+4*@bx-0x67], eax"); + TEST64("\x67\x01\x44\x9b\x99", "add dword ptr [ebx+4*ebx-0x67], eax"); + TEST("\x01\x44\x9c\x99", "add dword ptr [@sp+4*@bx-0x67], eax"); + TEST64("\x67\x01\x44\x9c\x99", "add dword ptr [esp+4*ebx-0x67], eax"); + TEST("\x01\x44\x9d\x99", "add dword ptr [@bp+4*@bx-0x67], eax"); + TEST64("\x67\x01\x44\x9d\x99", "add dword ptr [ebp+4*ebx-0x67], eax"); + TEST("\x01\x44\x9e\x99", "add dword ptr [@si+4*@bx-0x67], eax"); + TEST64("\x67\x01\x44\x9e\x99", "add dword ptr [esi+4*ebx-0x67], eax"); + TEST("\x01\x44\x9f\x99", "add dword ptr [@di+4*@bx-0x67], eax"); + TEST64("\x67\x01\x44\x9f\x99", "add dword ptr [edi+4*ebx-0x67], eax"); + TEST("\x01\x44\xa0\x99", "add dword ptr [@ax-0x67], eax"); + TEST64("\x67\x01\x44\xa0\x99", "add dword ptr [eax-0x67], eax"); + TEST("\x01\x44\xa1\x99", "add dword ptr [@cx-0x67], eax"); + TEST64("\x67\x01\x44\xa1\x99", "add dword ptr [ecx-0x67], eax"); + TEST("\x01\x44\xa2\x99", "add dword ptr [@dx-0x67], eax"); + TEST64("\x67\x01\x44\xa2\x99", "add dword ptr [edx-0x67], eax"); + TEST("\x01\x44\xa3\x99", "add dword ptr [@bx-0x67], eax"); + TEST64("\x67\x01\x44\xa3\x99", "add dword ptr [ebx-0x67], eax"); + TEST("\x01\x44\xa4\x99", "add dword ptr [@sp-0x67], eax"); + TEST64("\x67\x01\x44\xa4\x99", "add dword ptr [esp-0x67], eax"); + TEST("\x01\x44\xa5\x99", "add dword ptr [@bp-0x67], eax"); + TEST64("\x67\x01\x44\xa5\x99", "add dword ptr [ebp-0x67], eax"); + TEST("\x01\x44\xa6\x99", "add dword ptr [@si-0x67], eax"); + TEST64("\x67\x01\x44\xa6\x99", "add dword ptr [esi-0x67], eax"); + TEST("\x01\x44\xa7\x99", "add dword ptr [@di-0x67], eax"); + TEST64("\x67\x01\x44\xa7\x99", "add dword ptr [edi-0x67], eax"); + TEST("\x01\x44\xa8\x99", "add dword ptr [@ax+4*@bp-0x67], eax"); + TEST64("\x67\x01\x44\xa8\x99", "add dword ptr [eax+4*ebp-0x67], eax"); + TEST("\x01\x44\xa9\x99", "add dword ptr [@cx+4*@bp-0x67], eax"); + TEST64("\x67\x01\x44\xa9\x99", "add dword ptr [ecx+4*ebp-0x67], eax"); + TEST("\x01\x44\xaa\x99", "add dword ptr [@dx+4*@bp-0x67], eax"); + TEST64("\x67\x01\x44\xaa\x99", "add dword ptr [edx+4*ebp-0x67], eax"); + TEST("\x01\x44\xab\x99", "add dword ptr [@bx+4*@bp-0x67], eax"); + TEST64("\x67\x01\x44\xab\x99", "add dword ptr [ebx+4*ebp-0x67], eax"); + TEST("\x01\x44\xac\x99", "add dword ptr [@sp+4*@bp-0x67], eax"); + TEST64("\x67\x01\x44\xac\x99", "add dword ptr [esp+4*ebp-0x67], eax"); + TEST("\x01\x44\xad\x99", "add dword ptr [@bp+4*@bp-0x67], eax"); + TEST64("\x67\x01\x44\xad\x99", "add dword ptr [ebp+4*ebp-0x67], eax"); + TEST("\x01\x44\xae\x99", "add dword ptr [@si+4*@bp-0x67], eax"); + TEST64("\x67\x01\x44\xae\x99", "add dword ptr [esi+4*ebp-0x67], eax"); + TEST("\x01\x44\xaf\x99", "add dword ptr [@di+4*@bp-0x67], eax"); + TEST64("\x67\x01\x44\xaf\x99", "add dword ptr [edi+4*ebp-0x67], eax"); + TEST("\x01\x44\xb0\x99", "add dword ptr [@ax+4*@si-0x67], eax"); + TEST64("\x67\x01\x44\xb0\x99", "add dword ptr [eax+4*esi-0x67], eax"); + TEST("\x01\x44\xb1\x99", "add dword ptr [@cx+4*@si-0x67], eax"); + TEST64("\x67\x01\x44\xb1\x99", "add dword ptr [ecx+4*esi-0x67], eax"); + TEST("\x01\x44\xb2\x99", "add dword ptr [@dx+4*@si-0x67], eax"); + TEST64("\x67\x01\x44\xb2\x99", "add dword ptr [edx+4*esi-0x67], eax"); + TEST("\x01\x44\xb3\x99", "add dword ptr [@bx+4*@si-0x67], eax"); + TEST64("\x67\x01\x44\xb3\x99", "add dword ptr [ebx+4*esi-0x67], eax"); + TEST("\x01\x44\xb4\x99", "add dword ptr [@sp+4*@si-0x67], eax"); + TEST64("\x67\x01\x44\xb4\x99", "add dword ptr [esp+4*esi-0x67], eax"); + TEST("\x01\x44\xb5\x99", "add dword ptr [@bp+4*@si-0x67], eax"); + TEST64("\x67\x01\x44\xb5\x99", "add dword ptr [ebp+4*esi-0x67], eax"); + TEST("\x01\x44\xb6\x99", "add dword ptr [@si+4*@si-0x67], eax"); + TEST64("\x67\x01\x44\xb6\x99", "add dword ptr [esi+4*esi-0x67], eax"); + TEST("\x01\x44\xb7\x99", "add dword ptr [@di+4*@si-0x67], eax"); + TEST64("\x67\x01\x44\xb7\x99", "add dword ptr [edi+4*esi-0x67], eax"); + TEST("\x01\x44\xb8\x99", "add dword ptr [@ax+4*@di-0x67], eax"); + TEST64("\x67\x01\x44\xb8\x99", "add dword ptr [eax+4*edi-0x67], eax"); + TEST("\x01\x44\xb9\x99", "add dword ptr [@cx+4*@di-0x67], eax"); + TEST64("\x67\x01\x44\xb9\x99", "add dword ptr [ecx+4*edi-0x67], eax"); + TEST("\x01\x44\xba\x99", "add dword ptr [@dx+4*@di-0x67], eax"); + TEST64("\x67\x01\x44\xba\x99", "add dword ptr [edx+4*edi-0x67], eax"); + TEST("\x01\x44\xbb\x99", "add dword ptr [@bx+4*@di-0x67], eax"); + TEST64("\x67\x01\x44\xbb\x99", "add dword ptr [ebx+4*edi-0x67], eax"); + TEST("\x01\x44\xbc\x99", "add dword ptr [@sp+4*@di-0x67], eax"); + TEST64("\x67\x01\x44\xbc\x99", "add dword ptr [esp+4*edi-0x67], eax"); + TEST("\x01\x44\xbd\x99", "add dword ptr [@bp+4*@di-0x67], eax"); + TEST64("\x67\x01\x44\xbd\x99", "add dword ptr [ebp+4*edi-0x67], eax"); + TEST("\x01\x44\xbe\x99", "add dword ptr [@si+4*@di-0x67], eax"); + TEST64("\x67\x01\x44\xbe\x99", "add dword ptr [esi+4*edi-0x67], eax"); + TEST("\x01\x44\xbf\x99", "add dword ptr [@di+4*@di-0x67], eax"); + TEST64("\x67\x01\x44\xbf\x99", "add dword ptr [edi+4*edi-0x67], eax"); + TEST("\x01\x45\x99", "add dword ptr [@bp-0x67], eax"); + TEST64("\x67\x01\x45\x99", "add dword ptr [ebp-0x67], eax"); + TEST("\x01\x46\x99", "add dword ptr [@si-0x67], eax"); + TEST64("\x67\x01\x46\x99", "add dword ptr [esi-0x67], eax"); + TEST("\x01\x47\x99", "add dword ptr [@di-0x67], eax"); + TEST64("\x67\x01\x47\x99", "add dword ptr [edi-0x67], eax"); + TEST("\x01\x80\x11\x22\x33\x44", "add dword ptr [@ax+0x44332211], eax"); + TEST64("\x67\x01\x80\x11\x22\x33\x44", "add dword ptr [eax+0x44332211], eax"); + TEST("\x01\x81\x11\x22\x33\x44", "add dword ptr [@cx+0x44332211], eax"); + TEST64("\x67\x01\x81\x11\x22\x33\x44", "add dword ptr [ecx+0x44332211], eax"); + TEST("\x01\x82\x11\x22\x33\x44", "add dword ptr [@dx+0x44332211], eax"); + TEST64("\x67\x01\x82\x11\x22\x33\x44", "add dword ptr [edx+0x44332211], eax"); + TEST("\x01\x83\x11\x22\x33\x44", "add dword ptr [@bx+0x44332211], eax"); + TEST64("\x67\x01\x83\x11\x22\x33\x44", "add dword ptr [ebx+0x44332211], eax"); + TEST("\x01\x84\x80\x11\x22\x33\x44", "add dword ptr [@ax+4*@ax+0x44332211], eax"); + TEST64("\x67\x01\x84\x80\x11\x22\x33\x44", "add dword ptr [eax+4*eax+0x44332211], eax"); + TEST("\x01\x84\x81\x11\x22\x33\x44", "add dword ptr [@cx+4*@ax+0x44332211], eax"); + TEST64("\x67\x01\x84\x81\x11\x22\x33\x44", "add dword ptr [ecx+4*eax+0x44332211], eax"); + TEST("\x01\x84\x82\x11\x22\x33\x44", "add dword ptr [@dx+4*@ax+0x44332211], eax"); + TEST64("\x67\x01\x84\x82\x11\x22\x33\x44", "add dword ptr [edx+4*eax+0x44332211], eax"); + TEST("\x01\x84\x83\x11\x22\x33\x44", "add dword ptr [@bx+4*@ax+0x44332211], eax"); + TEST64("\x67\x01\x84\x83\x11\x22\x33\x44", "add dword ptr [ebx+4*eax+0x44332211], eax"); + TEST("\x01\x84\x84\x11\x22\x33\x44", "add dword ptr [@sp+4*@ax+0x44332211], eax"); + TEST64("\x67\x01\x84\x84\x11\x22\x33\x44", "add dword ptr [esp+4*eax+0x44332211], eax"); + TEST("\x01\x84\x85\x11\x22\x33\x44", "add dword ptr [@bp+4*@ax+0x44332211], eax"); + TEST64("\x67\x01\x84\x85\x11\x22\x33\x44", "add dword ptr [ebp+4*eax+0x44332211], eax"); + TEST("\x01\x84\x86\x11\x22\x33\x44", "add dword ptr [@si+4*@ax+0x44332211], eax"); + TEST64("\x67\x01\x84\x86\x11\x22\x33\x44", "add dword ptr [esi+4*eax+0x44332211], eax"); + TEST("\x01\x84\x87\x11\x22\x33\x44", "add dword ptr [@di+4*@ax+0x44332211], eax"); + TEST64("\x67\x01\x84\x87\x11\x22\x33\x44", "add dword ptr [edi+4*eax+0x44332211], eax"); + TEST("\x01\x84\x88\x11\x22\x33\x44", "add dword ptr [@ax+4*@cx+0x44332211], eax"); + TEST64("\x67\x01\x84\x88\x11\x22\x33\x44", "add dword ptr [eax+4*ecx+0x44332211], eax"); + TEST("\x01\x84\x89\x11\x22\x33\x44", "add dword ptr [@cx+4*@cx+0x44332211], eax"); + TEST64("\x67\x01\x84\x89\x11\x22\x33\x44", "add dword ptr [ecx+4*ecx+0x44332211], eax"); + TEST("\x01\x84\x8a\x11\x22\x33\x44", "add dword ptr [@dx+4*@cx+0x44332211], eax"); + TEST64("\x67\x01\x84\x8a\x11\x22\x33\x44", "add dword ptr [edx+4*ecx+0x44332211], eax"); + TEST("\x01\x84\x8b\x11\x22\x33\x44", "add dword ptr [@bx+4*@cx+0x44332211], eax"); + TEST64("\x67\x01\x84\x8b\x11\x22\x33\x44", "add dword ptr [ebx+4*ecx+0x44332211], eax"); + TEST("\x01\x84\x8c\x11\x22\x33\x44", "add dword ptr [@sp+4*@cx+0x44332211], eax"); + TEST64("\x67\x01\x84\x8c\x11\x22\x33\x44", "add dword ptr [esp+4*ecx+0x44332211], eax"); + TEST("\x01\x84\x8d\x11\x22\x33\x44", "add dword ptr [@bp+4*@cx+0x44332211], eax"); + TEST64("\x67\x01\x84\x8d\x11\x22\x33\x44", "add dword ptr [ebp+4*ecx+0x44332211], eax"); + TEST("\x01\x84\x8e\x11\x22\x33\x44", "add dword ptr [@si+4*@cx+0x44332211], eax"); + TEST64("\x67\x01\x84\x8e\x11\x22\x33\x44", "add dword ptr [esi+4*ecx+0x44332211], eax"); + TEST("\x01\x84\x8f\x11\x22\x33\x44", "add dword ptr [@di+4*@cx+0x44332211], eax"); + TEST64("\x67\x01\x84\x8f\x11\x22\x33\x44", "add dword ptr [edi+4*ecx+0x44332211], eax"); + TEST("\x01\x84\x90\x11\x22\x33\x44", "add dword ptr [@ax+4*@dx+0x44332211], eax"); + TEST64("\x67\x01\x84\x90\x11\x22\x33\x44", "add dword ptr [eax+4*edx+0x44332211], eax"); + TEST("\x01\x84\x91\x11\x22\x33\x44", "add dword ptr [@cx+4*@dx+0x44332211], eax"); + TEST64("\x67\x01\x84\x91\x11\x22\x33\x44", "add dword ptr [ecx+4*edx+0x44332211], eax"); + TEST("\x01\x84\x92\x11\x22\x33\x44", "add dword ptr [@dx+4*@dx+0x44332211], eax"); + TEST64("\x67\x01\x84\x92\x11\x22\x33\x44", "add dword ptr [edx+4*edx+0x44332211], eax"); + TEST("\x01\x84\x93\x11\x22\x33\x44", "add dword ptr [@bx+4*@dx+0x44332211], eax"); + TEST64("\x67\x01\x84\x93\x11\x22\x33\x44", "add dword ptr [ebx+4*edx+0x44332211], eax"); + TEST("\x01\x84\x94\x11\x22\x33\x44", "add dword ptr [@sp+4*@dx+0x44332211], eax"); + TEST64("\x67\x01\x84\x94\x11\x22\x33\x44", "add dword ptr [esp+4*edx+0x44332211], eax"); + TEST("\x01\x84\x95\x11\x22\x33\x44", "add dword ptr [@bp+4*@dx+0x44332211], eax"); + TEST64("\x67\x01\x84\x95\x11\x22\x33\x44", "add dword ptr [ebp+4*edx+0x44332211], eax"); + TEST("\x01\x84\x96\x11\x22\x33\x44", "add dword ptr [@si+4*@dx+0x44332211], eax"); + TEST64("\x67\x01\x84\x96\x11\x22\x33\x44", "add dword ptr [esi+4*edx+0x44332211], eax"); + TEST("\x01\x84\x97\x11\x22\x33\x44", "add dword ptr [@di+4*@dx+0x44332211], eax"); + TEST64("\x67\x01\x84\x97\x11\x22\x33\x44", "add dword ptr [edi+4*edx+0x44332211], eax"); + TEST("\x01\x84\x98\x11\x22\x33\x44", "add dword ptr [@ax+4*@bx+0x44332211], eax"); + TEST64("\x67\x01\x84\x98\x11\x22\x33\x44", "add dword ptr [eax+4*ebx+0x44332211], eax"); + TEST("\x01\x84\x99\x11\x22\x33\x44", "add dword ptr [@cx+4*@bx+0x44332211], eax"); + TEST64("\x67\x01\x84\x99\x11\x22\x33\x44", "add dword ptr [ecx+4*ebx+0x44332211], eax"); + TEST("\x01\x84\x9a\x11\x22\x33\x44", "add dword ptr [@dx+4*@bx+0x44332211], eax"); + TEST64("\x67\x01\x84\x9a\x11\x22\x33\x44", "add dword ptr [edx+4*ebx+0x44332211], eax"); + TEST("\x01\x84\x9b\x11\x22\x33\x44", "add dword ptr [@bx+4*@bx+0x44332211], eax"); + TEST64("\x67\x01\x84\x9b\x11\x22\x33\x44", "add dword ptr [ebx+4*ebx+0x44332211], eax"); + TEST("\x01\x84\x9c\x11\x22\x33\x44", "add dword ptr [@sp+4*@bx+0x44332211], eax"); + TEST64("\x67\x01\x84\x9c\x11\x22\x33\x44", "add dword ptr [esp+4*ebx+0x44332211], eax"); + TEST("\x01\x84\x9d\x11\x22\x33\x44", "add dword ptr [@bp+4*@bx+0x44332211], eax"); + TEST64("\x67\x01\x84\x9d\x11\x22\x33\x44", "add dword ptr [ebp+4*ebx+0x44332211], eax"); + TEST("\x01\x84\x9e\x11\x22\x33\x44", "add dword ptr [@si+4*@bx+0x44332211], eax"); + TEST64("\x67\x01\x84\x9e\x11\x22\x33\x44", "add dword ptr [esi+4*ebx+0x44332211], eax"); + TEST("\x01\x84\x9f\x11\x22\x33\x44", "add dword ptr [@di+4*@bx+0x44332211], eax"); + TEST64("\x67\x01\x84\x9f\x11\x22\x33\x44", "add dword ptr [edi+4*ebx+0x44332211], eax"); + TEST("\x01\x84\xa0\x11\x22\x33\x44", "add dword ptr [@ax+0x44332211], eax"); + TEST64("\x67\x01\x84\xa0\x11\x22\x33\x44", "add dword ptr [eax+0x44332211], eax"); + TEST("\x01\x84\xa1\x11\x22\x33\x44", "add dword ptr [@cx+0x44332211], eax"); + TEST64("\x67\x01\x84\xa1\x11\x22\x33\x44", "add dword ptr [ecx+0x44332211], eax"); + TEST("\x01\x84\xa2\x11\x22\x33\x44", "add dword ptr [@dx+0x44332211], eax"); + TEST64("\x67\x01\x84\xa2\x11\x22\x33\x44", "add dword ptr [edx+0x44332211], eax"); + TEST("\x01\x84\xa3\x11\x22\x33\x44", "add dword ptr [@bx+0x44332211], eax"); + TEST64("\x67\x01\x84\xa3\x11\x22\x33\x44", "add dword ptr [ebx+0x44332211], eax"); + TEST("\x01\x84\xa4\x11\x22\x33\x44", "add dword ptr [@sp+0x44332211], eax"); + TEST64("\x67\x01\x84\xa4\x11\x22\x33\x44", "add dword ptr [esp+0x44332211], eax"); + TEST("\x01\x84\xa5\x11\x22\x33\x44", "add dword ptr [@bp+0x44332211], eax"); + TEST64("\x67\x01\x84\xa5\x11\x22\x33\x44", "add dword ptr [ebp+0x44332211], eax"); + TEST("\x01\x84\xa6\x11\x22\x33\x44", "add dword ptr [@si+0x44332211], eax"); + TEST64("\x67\x01\x84\xa6\x11\x22\x33\x44", "add dword ptr [esi+0x44332211], eax"); + TEST("\x01\x84\xa7\x11\x22\x33\x44", "add dword ptr [@di+0x44332211], eax"); + TEST64("\x67\x01\x84\xa7\x11\x22\x33\x44", "add dword ptr [edi+0x44332211], eax"); + TEST("\x01\x84\xa8\x11\x22\x33\x44", "add dword ptr [@ax+4*@bp+0x44332211], eax"); + TEST64("\x67\x01\x84\xa8\x11\x22\x33\x44", "add dword ptr [eax+4*ebp+0x44332211], eax"); + TEST("\x01\x84\xa9\x11\x22\x33\x44", "add dword ptr [@cx+4*@bp+0x44332211], eax"); + TEST64("\x67\x01\x84\xa9\x11\x22\x33\x44", "add dword ptr [ecx+4*ebp+0x44332211], eax"); + TEST("\x01\x84\xaa\x11\x22\x33\x44", "add dword ptr [@dx+4*@bp+0x44332211], eax"); + TEST64("\x67\x01\x84\xaa\x11\x22\x33\x44", "add dword ptr [edx+4*ebp+0x44332211], eax"); + TEST("\x01\x84\xab\x11\x22\x33\x44", "add dword ptr [@bx+4*@bp+0x44332211], eax"); + TEST64("\x67\x01\x84\xab\x11\x22\x33\x44", "add dword ptr [ebx+4*ebp+0x44332211], eax"); + TEST("\x01\x84\xac\x11\x22\x33\x44", "add dword ptr [@sp+4*@bp+0x44332211], eax"); + TEST64("\x67\x01\x84\xac\x11\x22\x33\x44", "add dword ptr [esp+4*ebp+0x44332211], eax"); + TEST("\x01\x84\xad\x11\x22\x33\x44", "add dword ptr [@bp+4*@bp+0x44332211], eax"); + TEST64("\x67\x01\x84\xad\x11\x22\x33\x44", "add dword ptr [ebp+4*ebp+0x44332211], eax"); + TEST("\x01\x84\xae\x11\x22\x33\x44", "add dword ptr [@si+4*@bp+0x44332211], eax"); + TEST64("\x67\x01\x84\xae\x11\x22\x33\x44", "add dword ptr [esi+4*ebp+0x44332211], eax"); + TEST("\x01\x84\xaf\x11\x22\x33\x44", "add dword ptr [@di+4*@bp+0x44332211], eax"); + TEST64("\x67\x01\x84\xaf\x11\x22\x33\x44", "add dword ptr [edi+4*ebp+0x44332211], eax"); + TEST("\x01\x84\xb0\x11\x22\x33\x44", "add dword ptr [@ax+4*@si+0x44332211], eax"); + TEST64("\x67\x01\x84\xb0\x11\x22\x33\x44", "add dword ptr [eax+4*esi+0x44332211], eax"); + TEST("\x01\x84\xb1\x11\x22\x33\x44", "add dword ptr [@cx+4*@si+0x44332211], eax"); + TEST64("\x67\x01\x84\xb1\x11\x22\x33\x44", "add dword ptr [ecx+4*esi+0x44332211], eax"); + TEST("\x01\x84\xb2\x11\x22\x33\x44", "add dword ptr [@dx+4*@si+0x44332211], eax"); + TEST64("\x67\x01\x84\xb2\x11\x22\x33\x44", "add dword ptr [edx+4*esi+0x44332211], eax"); + TEST("\x01\x84\xb3\x11\x22\x33\x44", "add dword ptr [@bx+4*@si+0x44332211], eax"); + TEST64("\x67\x01\x84\xb3\x11\x22\x33\x44", "add dword ptr [ebx+4*esi+0x44332211], eax"); + TEST("\x01\x84\xb4\x11\x22\x33\x44", "add dword ptr [@sp+4*@si+0x44332211], eax"); + TEST64("\x67\x01\x84\xb4\x11\x22\x33\x44", "add dword ptr [esp+4*esi+0x44332211], eax"); + TEST("\x01\x84\xb5\x11\x22\x33\x44", "add dword ptr [@bp+4*@si+0x44332211], eax"); + TEST64("\x67\x01\x84\xb5\x11\x22\x33\x44", "add dword ptr [ebp+4*esi+0x44332211], eax"); + TEST("\x01\x84\xb6\x11\x22\x33\x44", "add dword ptr [@si+4*@si+0x44332211], eax"); + TEST64("\x67\x01\x84\xb6\x11\x22\x33\x44", "add dword ptr [esi+4*esi+0x44332211], eax"); + TEST("\x01\x84\xb7\x11\x22\x33\x44", "add dword ptr [@di+4*@si+0x44332211], eax"); + TEST64("\x67\x01\x84\xb7\x11\x22\x33\x44", "add dword ptr [edi+4*esi+0x44332211], eax"); + TEST("\x01\x84\xb8\x11\x22\x33\x44", "add dword ptr [@ax+4*@di+0x44332211], eax"); + TEST64("\x67\x01\x84\xb8\x11\x22\x33\x44", "add dword ptr [eax+4*edi+0x44332211], eax"); + TEST("\x01\x84\xb9\x11\x22\x33\x44", "add dword ptr [@cx+4*@di+0x44332211], eax"); + TEST64("\x67\x01\x84\xb9\x11\x22\x33\x44", "add dword ptr [ecx+4*edi+0x44332211], eax"); + TEST("\x01\x84\xba\x11\x22\x33\x44", "add dword ptr [@dx+4*@di+0x44332211], eax"); + TEST64("\x67\x01\x84\xba\x11\x22\x33\x44", "add dword ptr [edx+4*edi+0x44332211], eax"); + TEST("\x01\x84\xbb\x11\x22\x33\x44", "add dword ptr [@bx+4*@di+0x44332211], eax"); + TEST64("\x67\x01\x84\xbb\x11\x22\x33\x44", "add dword ptr [ebx+4*edi+0x44332211], eax"); + TEST("\x01\x84\xbc\x11\x22\x33\x44", "add dword ptr [@sp+4*@di+0x44332211], eax"); + TEST64("\x67\x01\x84\xbc\x11\x22\x33\x44", "add dword ptr [esp+4*edi+0x44332211], eax"); + TEST("\x01\x84\xbd\x11\x22\x33\x44", "add dword ptr [@bp+4*@di+0x44332211], eax"); + TEST64("\x67\x01\x84\xbd\x11\x22\x33\x44", "add dword ptr [ebp+4*edi+0x44332211], eax"); + TEST("\x01\x84\xbe\x11\x22\x33\x44", "add dword ptr [@si+4*@di+0x44332211], eax"); + TEST64("\x67\x01\x84\xbe\x11\x22\x33\x44", "add dword ptr [esi+4*edi+0x44332211], eax"); + TEST("\x01\x84\xbf\x11\x22\x33\x44", "add dword ptr [@di+4*@di+0x44332211], eax"); + TEST64("\x67\x01\x84\xbf\x11\x22\x33\x44", "add dword ptr [edi+4*edi+0x44332211], eax"); + TEST("\x01\x85\x11\x22\x33\x44", "add dword ptr [@bp+0x44332211], eax"); + TEST64("\x67\x01\x85\x11\x22\x33\x44", "add dword ptr [ebp+0x44332211], eax"); + TEST("\x01\x86\x11\x22\x33\x44", "add dword ptr [@si+0x44332211], eax"); + TEST64("\x67\x01\x86\x11\x22\x33\x44", "add dword ptr [esi+0x44332211], eax"); + TEST("\x01\x87\x11\x22\x33\x44", "add dword ptr [@di+0x44332211], eax"); + TEST64("\x67\x01\x87\x11\x22\x33\x44", "add dword ptr [edi+0x44332211], eax"); + TEST("\x01\xc0", "add eax, eax"); + TEST("\x01\xc1", "add ecx, eax"); + TEST("\x01\xc2", "add edx, eax"); + TEST("\x01\xc3", "add ebx, eax"); + TEST("\x01\xc4", "add esp, eax"); + TEST("\x01\xc5", "add ebp, eax"); + TEST("\x01\xc6", "add esi, eax"); + TEST("\x01\xc7", "add edi, eax"); + + TEST("\x0f\xbc\xc0", "bsf eax, eax"); + TEST("\x66\x0f\xbc\xc0", "bsf ax, ax"); + TEST("\xf2\x0f\xbc\xc0", "bsf eax, eax"); + TEST("\x66\xf2\x0f\xbc\xc0", "bsf ax, ax"); + TEST("\x0f\x01\x00", "sgdt [@ax]"); + TEST("\x66\x0f\x01\x00", "sgdt [@ax]"); + TEST("\xf2\x0f\x01\x00", "sgdt [@ax]"); + TEST("\xf3\x0f\x01\x00", "sgdt [@ax]"); + TEST("\x04\x01", "add al, 0x1"); + TEST("\x66\x50", "push ax"); + TEST("\x50", "push @ax"); + TEST("\x66\x68\xff\xad", "pushw 0xadff"); + TEST3264("\x68\xff\xad\x90\xbc", "push 0xbc90adff", "push 0xffffffffbc90adff"); + TEST("\x66\x6a\xff", "pushw 0xffff"); + TEST3264("\x6a\xff", "push 0xffffffff", "push 0xffffffffffffffff"); + TEST32("\x60", "pushad"); + TEST32("\x66\x60", "pushaw"); + TEST("\xb0\xf0", "mov al, 0xf0"); + TEST("\xb1\xda", "mov cl, 0xda"); + TEST("\xb2\xff", "mov dl, 0xff"); + TEST("\xb3\x8d", "mov bl, 0x8d"); + TEST("\xb4\x5e", "mov ah, 0x5e"); + TEST64("\x40\xb4\x00", "mov spl, 0x0"); + TEST("\xb5\x74", "mov ch, 0x74"); + TEST64("\x40\xb5\xd0", "mov bpl, 0xd0"); + TEST("\xb6\xe5", "mov dh, 0xe5"); + TEST64("\x40\xb6\xf1", "mov sil, 0xf1"); + TEST("\xb7\xe8", "mov bh, 0xe8"); + TEST64("\x40\xb7\x31", "mov dil, 0x31"); + TEST("\x66\xb8\xf0\xf0", "mov ax, 0xf0f0"); + TEST("\xb8\xf0\xf0\xab\xff", "mov eax, 0xffabf0f0"); + TEST64("\x48\xb8\xf0\xf0\xab\xff\x00\x12\x12\xcd", "mov rax, 0xcd121200ffabf0f0"); + TEST64("\xcd\x80", "int 0x80"); + + // Test FD/TD encoding + TEST32("\xa0\x44\x33\x22\x11", "mov al, byte ptr [0x11223344]"); + TEST64("\xa0\x88\x77\x66\x55\x44\x33\x22\x11", "mov al, byte ptr [0x1122334455667788]"); + TEST32("\x67\xa0\x22\x11", "mov al, byte ptr [0x1122]"); + TEST64("\x67\xa0\x44\x33\x22\x11", "mov al, byte ptr [0x11223344]"); + TEST32("\xa1\x44\x33\x22\x11", "mov eax, dword ptr [0x11223344]"); + TEST64("\xa1\x88\x77\x66\x55\x44\x33\x22\x11", "mov eax, dword ptr [0x1122334455667788]"); + TEST32("\x67\xa1\x22\x11", "mov eax, dword ptr [0x1122]"); + TEST64("\x67\xa1\x44\x33\x22\x11", "mov eax, dword ptr [0x11223344]"); + TEST32("\x66\xa1\x44\x33\x22\x11", "mov ax, word ptr [0x11223344]"); + TEST64("\x66\xa1\x88\x77\x66\x55\x44\x33\x22\x11", "mov ax, word ptr [0x1122334455667788]"); + TEST32("\x66\x67\xa1\x22\x11", "mov ax, word ptr [0x1122]"); + TEST64("\x66\x67\xa1\x44\x33\x22\x11", "mov ax, word ptr [0x11223344]"); + TEST64("\x48\xa1\x88\x77\x66\x55\x44\x33\x22\x11", "mov rax, qword ptr [0x1122334455667788]"); + TEST64("\x67\x48\xa1\x44\x33\x22\x11", "mov rax, qword ptr [0x11223344]"); + TEST32("\xa2\x44\x33\x22\x11", "mov byte ptr [0x11223344], al"); + TEST64("\xa2\x88\x77\x66\x55\x44\x33\x22\x11", "mov byte ptr [0x1122334455667788], al"); + TEST32("\x67\xa2\x22\x11", "mov byte ptr [0x1122], al"); + TEST64("\x67\xa2\x44\x33\x22\x11", "mov byte ptr [0x11223344], al"); + TEST32("\xa3\x44\x33\x22\x11", "mov dword ptr [0x11223344], eax"); + TEST64("\xa3\x88\x77\x66\x55\x44\x33\x22\x11", "mov dword ptr [0x1122334455667788], eax"); + TEST32("\x67\xa3\x22\x11", "mov dword ptr [0x1122], eax"); + TEST64("\x67\xa3\x44\x33\x22\x11", "mov dword ptr [0x11223344], eax"); + TEST32("\x66\xa3\x44\x33\x22\x11", "mov word ptr [0x11223344], ax"); + TEST64("\x66\xa3\x88\x77\x66\x55\x44\x33\x22\x11", "mov word ptr [0x1122334455667788], ax"); + TEST32("\x66\x67\xa3\x22\x11", "mov word ptr [0x1122], ax"); + TEST64("\x66\x67\xa3\x44\x33\x22\x11", "mov word ptr [0x11223344], ax"); + TEST64("\x48\xa3\x88\x77\x66\x55\x44\x33\x22\x11", "mov qword ptr [0x1122334455667788], rax"); + TEST64("\x67\x48\xa3\x44\x33\x22\x11", "mov qword ptr [0x11223344], rax"); + TEST32("\xa0\x44\x33\x22", "PARTIAL"); + TEST64("\xa0\x88\x77\x66\x55\x44\x33\x22", "PARTIAL"); + TEST32("\x67\xa0\x22", "PARTIAL"); + TEST64("\x67\xa0\x44\x33\x22", "PARTIAL"); + + TEST("\x66\xc8\x00\x00\x00", "enterw 0x0, 0x0"); + TEST("\x66\xc8\x00\x0f\x00", "enterw 0xf00, 0x0"); + TEST("\x66\xc8\x00\x00\x01", "enterw 0x0, 0x1"); + TEST32("\xc8\x00\x00\x00", "enter 0x0, 0x0"); + TEST32("\xc8\x00\x0f\x00", "enter 0xf00, 0x0"); + TEST32("\xc8\x00\x00\x01", "enter 0x0, 0x1"); + TEST64("\xc8\x00\x00\x00", "enter 0x0, 0x0"); + TEST64("\xc8\x00\x0f\x00", "enter 0xf00, 0x0"); + TEST64("\xc8\x00\x00\x01", "enter 0x0, 0x1"); + + TEST64("\xd3\xe0", "shl eax, cl"); + TEST64("\xd0\x3e", "sar byte ptr [rsi], 0x1"); + TEST64("\x0f\xa5\xd0", "shld eax, edx, cl"); + + TEST("\x69\xC7\x08\x01\x00\x00", "imul eax, edi, 0x108"); + TEST("\x6B\xC7\x08", "imul eax, edi, 0x8"); + TEST("\x6B\xC7\xff", "imul eax, edi, 0xffffffff"); + + TEST("\x0f\x38\xf0\xd1", "UD"); // MOVBE doesn't allow register moves + TEST("\x0f\x38\xf0\x11", "movbe edx, dword ptr [@cx]"); + TEST("\x66\x0f\x38\xf0\x11", "movbe dx, word ptr [@cx]"); + TEST64("\x48\x0f\x38\xf0\x01", "movbe rax, qword ptr [rcx]"); + TEST("\xf2\x0f\x38\xf0\xd1", "crc32 edx, cl"); + TEST("\xf2\x66\x0f\x38\xf1\xd1", "crc32 edx, cx"); + TEST("\xf2\x0f\x38\xf1\xd1", "crc32 edx, ecx"); + TEST64("\xf2\x48\x0f\x38\xf1\xd1", "crc32 edx, rcx"); + TEST64("\xf2\x4c\x0f\x38\xf1\xd1", "crc32 r10d, rcx"); + + TEST("\x8d\x00", "lea eax, [@ax]"); + TEST("\x8d\xc0", "UD"); + + TEST("\x00\xc0", "add al, al"); + TEST("\x00\xc1", "add cl, al"); + TEST("\x00\xd0", "add al, dl"); + TEST("\x00\xff", "add bh, bh"); + TEST("\x01\xc0", "add eax, eax"); + TEST("\x01\xc1", "add ecx, eax"); + TEST("\x01\xd0", "add eax, edx"); + TEST("\x01\xff", "add edi, edi"); + TEST("\x02\xc0", "add al, al"); + TEST("\x02\xc1", "add al, cl"); + TEST("\x02\xd0", "add dl, al"); + TEST("\x02\xff", "add bh, bh"); + TEST("\x03\xc0", "add eax, eax"); + TEST("\x03\xc1", "add eax, ecx"); + TEST("\x03\xd0", "add edx, eax"); + TEST("\x03\xff", "add edi, edi"); + TEST("\x05\x01\x00\x00\x80", "add eax, 0x80000001"); + TEST64("\x48\x05\x01\x00\x00\x80", "add rax, 0xffffffff80000001"); + + TEST32("\x40", "inc eax"); + TEST32("\x43", "inc ebx"); + TEST32("\x66\x47", "inc di"); + TEST("\xfe\xc0", "inc al"); + TEST("\xfe\xc4", "inc ah"); + TEST("\xff\xc0", "inc eax"); + TEST("\xff\xc4", "inc esp"); + TEST("\xff\x00", "inc dword ptr [@ax]"); + TEST("\xf0\xff\x00", "lock inc dword ptr [@ax]"); + TEST("\x66\xff\xc0", "inc ax"); + TEST("\x66\xff\xc4", "inc sp"); + TEST64("\x48\xff\xc0", "inc rax"); + TEST64("\x48\xff\xc4", "inc rsp"); + TEST64("\x49\xff\xc7", "inc r15"); + + TEST32("\xe9\x00\x00\x00\x00", "jmp 0x5"); + TEST32("\x66\xe9\x01\x00", "jmpw 0x5"); + TEST64("\xe9\x00\x00\x00\x00", "jmp 0x5"); + TEST64("\x66\xe9\x00\x00\x00\x00", "jmp 0x6"); + TEST64("\x66\xeb\x00", "jmp 0x3"); + TEST64("\x66\xeb\xff", "jmp 0x2"); + TEST("\x66\xe9\x00", "PARTIAL"); + TEST("\x66\xe9", "PARTIAL"); + TEST32("\xc7\xf8\xd3\x9c\xff\xff", "xbegin 0xffff9cd9"); + TEST32("\x66\xc7\xf8\xd3\x9c", "xbegin 0xffff9cd8"); + TEST64("\xc7\xf8\xd3\x9c\xff\xff", "xbegin 0xffffffffffff9cd9"); + TEST64("\x66\xc7\xf8\xd3\x9c", "xbegin 0xffffffffffff9cd8"); + + + TEST("\xa5", "movsd"); + TEST("\x66\xa5", "movsw"); + TEST("\xf3\xa5", "rep movsd"); + TEST("\xf3\x66\xa5", "rep movsw"); + TEST("\xf3\xae", "rep scasb"); + TEST("\xf2\xae", "repnz scasb"); + TEST("\xf3\x66\xae", "rep scasb"); + TEST("\xf2\x66\xae", "repnz scasb"); + TEST("\xf3\xaf", "rep scasd"); + TEST("\xf2\xaf", "repnz scasd"); + TEST("\xf3\x66\xaf", "rep scasw"); + TEST("\xf2\x66\xaf", "repnz scasw"); + TEST64("\xf3\x48\xaf", "rep scasq"); + TEST64("\xf2\x48\xaf", "repnz scasq"); + TEST64("\xf3\x66\x48\xaf", "rep scasq"); + TEST64("\xf2\x66\x48\xaf", "repnz scasq"); + + TEST("\x66\x0f\xbe\xc2", "movsx ax, dl"); + TEST("\x0f\xbe\xc2", "movsx eax, dl"); + TEST("\x0f\xbe\xc4", "movsx eax, ah"); + TEST64("\x40\x0f\xbe\xc4", "movsx eax, spl"); + TEST("\x0f\xbf\xc2", "movsx eax, dx"); + TEST64("\x48\x0f\xbf\xc2", "movsx rax, dx"); + TEST64("\x48\x63\xc2", "movsx rax, edx"); + + TEST32("\x66\xc3", "retw"); + TEST32("\x66\xc2\x00\x00", "retw 0x0"); + TEST32("\x66\xc2\x0d\x00", "retw 0xd"); + TEST32("\x66\xc2\x0d\xff", "retw 0xff0d"); + TEST64("\x66\xc3", "ret"); + TEST64("\x66\xc2\x00\x00", "ret 0x0"); + TEST64("\x66\xc2\x0d\x00", "ret 0xd"); + TEST64("\x66\xc2\x0d\xff", "ret 0xff0d"); + TEST32("\xc3", "ret"); + TEST32("\xc2\x00\x00", "ret 0x0"); + TEST32("\xc2\x0d\x00", "ret 0xd"); + TEST32("\xc2\x0d\xff", "ret 0xff0d"); + TEST64("\xc3", "ret"); + TEST64("\xc2\x00\x00", "ret 0x0"); + TEST64("\xc2\x0d\x00", "ret 0xd"); + TEST64("\xc2\x0d\xff", "ret 0xff0d"); + TEST("\xca\x00\x00", "retfd 0x0"); + TEST("\xca\x0d\x00", "retfd 0xd"); + TEST("\xca\x0d\xff", "retfd 0xff0d"); + TEST("\xcb", "retfd"); + TEST("\x66\xca\x00\x00", "retfw 0x0"); + TEST("\x66\xca\x0d\x00", "retfw 0xd"); + TEST("\x66\xca\x0d\xff", "retfw 0xff0d"); + TEST("\x66\xcb", "retfw"); + TEST64("\x48\xca\x00\x00", "retfq 0x0"); + TEST64("\x48\xca\x0d\x00", "retfq 0xd"); + TEST64("\x48\xca\x0d\xff", "retfq 0xff0d"); + TEST64("\x48\xcb", "retfq"); + + // BMI1 + TEST("\xf3\x0f\xbc\xc0", "tzcnt eax, eax"); + TEST("\x66\xf3\x0f\xbc\xc0", "tzcnt ax, ax"); + TEST64("\xf3\x48\x0f\xbc\xc0", "tzcnt rax, rax"); + TEST("\xf3\x0f\xbd\xc0", "lzcnt eax, eax"); + TEST("\x66\xf3\x0f\xbd\xc0", "lzcnt ax, ax"); + TEST64("\xf3\x48\x0f\xbd\xc0", "lzcnt rax, rax"); + TEST3264("\xc4\xc2\x18\xf2\xc7", "andn eax, esp, edi", "andn eax, r12d, r15d"); + TEST3264("\xc4\xc2\x98\xf2\xc7", "andn eax, esp, edi", "andn rax, r12, r15"); + TEST64("\xc4\x42\x18\xf2\xc7", "andn r8d, r12d, r15d"); + TEST64("\xc4\x42\x98\xf2\xc7", "andn r8, r12, r15"); + TEST("\xc4\xe2\x78\xf3\xca", "blsr eax, edx"); + TEST("\xc4\xe2\x78\xf3\x08", "blsr eax, dword ptr [@ax]"); + TEST("\xc4\xe2\xf8\xf3\xca", "blsr @ax, @dx"); + TEST3264("\xc4\xe2\xf8\xf3\x08", "blsr eax, dword ptr [eax]", "blsr rax, qword ptr [rax]"); + TEST3264("\xc4\xc2\x38\xf3\xc9", "blsr eax, ecx", "blsr r8d, r9d"); + TEST3264("\xc4\xc2\xb8\xf3\xc9", "blsr eax, ecx", "blsr r8, r9"); + TEST3264("\xc4\xe2\x38\xf3\xc9", "blsr eax, ecx", "blsr r8d, ecx"); + TEST3264("\xc4\xe2\xb8\xf3\xc9", "blsr eax, ecx", "blsr r8, rcx"); + TEST3264("\xc4\xc2\x78\xf3\xc9", "blsr eax, ecx", "blsr eax, r9d"); + TEST3264("\xc4\xc2\xf8\xf3\xc9", "blsr eax, ecx", "blsr rax, r9"); + TEST("\xc4\xe2\x78\xf3\xd2", "blsmsk eax, edx"); + TEST("\xc4\xe2\x78\xf3\x10", "blsmsk eax, dword ptr [@ax]"); + TEST("\xc4\xe2\xf8\xf3\xd2", "blsmsk @ax, @dx"); + TEST3264("\xc4\xe2\xf8\xf3\x10", "blsmsk eax, dword ptr [eax]", "blsmsk rax, qword ptr [rax]"); + TEST("\xc4\xe2\x78\xf3\xda", "blsi eax, edx"); + TEST("\xc4\xe2\x78\xf3\x18", "blsi eax, dword ptr [@ax]"); + TEST("\xc4\xe2\xf8\xf3\xda", "blsi @ax, @dx"); + TEST3264("\xc4\xe2\xf8\xf3\x18", "blsi eax, dword ptr [eax]", "blsi rax, qword ptr [rax]"); + TEST3264("\xc4\xc2\x18\xf7\xc7", "bextr eax, edi, esp", "bextr eax, r15d, r12d"); + TEST3264("\xc4\xc2\x98\xf7\xc7", "bextr eax, edi, esp", "bextr rax, r15, r12"); + TEST64("\xc4\x42\x18\xf7\xc7", "bextr r8d, r15d, r12d"); + TEST64("\xc4\x42\x98\xf7\xc7", "bextr r8, r15, r12"); + + // NFx/66+F2/F3 combinations + TEST("\x0f\xc7\xf0", "rdrand eax"); + TEST64("\x48\x0f\xc7\xf0", "rdrand rax"); + TEST("\x66\x0f\xc7\xf0", "rdrand ax"); + TEST64("\x66\x48\x0f\xc7\xf0", "rdrand rax"); + TEST("\x0f\xc7\xf8", "rdseed eax"); + TEST64("\x48\x0f\xc7\xf8", "rdseed rax"); + TEST("\x66\x0f\xc7\xf8", "rdseed ax"); + TEST64("\x66\x48\x0f\xc7\xf8", "rdseed rax"); + TEST32("\xf3\x0f\xc7\xf8", "rdpid eax"); + TEST32("\x66\xf3\x0f\xc7\xf8", "rdpid eax"); + TEST32("\xf3\x66\x0f\xc7\xf8", "rdpid eax"); + TEST64("\xf3\x0f\xc7\xf8", "rdpid rax"); + TEST64("\x66\xf3\x0f\xc7\xf8", "rdpid rax"); + TEST64("\xf3\x66\x0f\xc7\xf8", "rdpid rax"); + TEST64("\xf3\x0f\xc7\x00", "UD"); + TEST64("\x0f\xc7\x30", "vmptrld qword ptr [rax]"); + TEST64("\x66\x0f\xc7\x30", "vmclear qword ptr [rax]"); + TEST64("\xf3\x0f\xc7\x30", "vmxon qword ptr [rax]"); + TEST("\x0f\x78\xc1", "vmread @cx, @ax"); + TEST("\x0f\x79\xc1", "vmwrite @ax, @cx"); + + TEST64("\x0f\x09", "wbinvd"); + TEST64("\xf3\x0f\x09", "wbnoinvd"); + TEST("\x66\x0f\x38\x82\x01", "invpcid @ax, xmmword ptr [@cx]"); + TEST("\x66\x0f\x38\x80\x02", "invept @ax, xmmword ptr [@dx]"); + TEST("\x66\x0f\x38\x81\x02", "invvpid @ax, xmmword ptr [@dx]"); + TEST("\x66\x0f\x38\xf8\x01", "movdir64b @ax, zmmword ptr [@cx]"); + // TODO: MOVDIR64B first operand has address size. + // TEST32("\x67\x66\x0f\x38\xf8\x01", "movdir64b ax, zmmword ptr [cx]"); + // TEST64("\x67\x66\x0f\x38\xf8\x01", "movdir64b eax, zmmword ptr [ecx]"); + TEST("\x0f\x30", "wrmsr"); + TEST("\x0f\x32", "rdmsr"); + TEST("\x0f\x01\xc6", "wrmsrns"); + TEST3264("\xf2\x0f\x01\xc6", "UD", "rdmsrlist"); + TEST3264("\xf3\x0f\x01\xc6", "UD", "wrmsrlist"); + TEST3264("\xc4\xe7\x7b\xf6\xc1\x10\x20\x30\x40", "UD", "rdmsr rcx, 0x40302010"); + TEST3264("\xc4\xe7\x7a\xf6\xc1\x10\x20\x30\x40", "UD", "wrmsrns 0x40302010, rcx"); + TEST3264("\xf2\x0f\x38\xf8\xc1", "UD", "urdmsr rcx, rax"); + TEST3264("\xf3\x0f\x38\xf8\xc1", "UD", "uwrmsr rcx, rax"); + TEST3264("\xc4\xe7\x7b\xf8\xc1\x10\x20\x30\x40", "UD", "urdmsr rcx, 0x40302010"); + TEST3264("\xc4\xe7\x7a\xf8\xc1\x10\x20\x30\x40", "UD", "uwrmsr 0x40302010, rcx"); + + TEST("\x0f\x38\xfc\xc1", "UD"); // Must be memory operand + TEST("\x0f\x38\xfc\x01", "aadd dword ptr [@cx], eax"); + TEST64("\x48\x0f\x38\xfc\x01", "aadd qword ptr [rcx], rax"); + TEST("\x66\x0f\x38\xfc\xc1", "UD"); // Must be memory operand + TEST("\x66\x0f\x38\xfc\x01", "aand dword ptr [@cx], eax"); + TEST64("\x66\x48\x0f\x38\xfc\x01", "aand qword ptr [rcx], rax"); + TEST("\xf3\x0f\x38\xfc\xc1", "UD"); // Must be memory operand + TEST("\xf3\x0f\x38\xfc\x01", "axor dword ptr [@cx], eax"); + TEST64("\xf3\x48\x0f\x38\xfc\x01", "axor qword ptr [rcx], rax"); + TEST("\xf2\x0f\x38\xfc\xc1", "UD"); // Must be memory operand + TEST("\xf2\x0f\x38\xfc\x01", "aor dword ptr [@cx], eax"); + TEST64("\xf2\x48\x0f\x38\xfc\x01", "aor qword ptr [rcx], rax"); + + TEST64("\xc4\xe2\x61\xe0\x08", "cmpoxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe0\x08", "cmpoxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xe1\x08", "cmpnoxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe1\x08", "cmpnoxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xe2\x08", "cmpbxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe2\x08", "cmpbxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xe3\x08", "cmpnbxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe3\x08", "cmpnbxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xe4\x08", "cmpzxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe4\x08", "cmpzxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xe5\x08", "cmpnzxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe5\x08", "cmpnzxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xe6\x08", "cmpbexadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe6\x08", "cmpbexadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xe7\x08", "cmpnbexadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe7\x08", "cmpnbexadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xe8\x08", "cmpsxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe8\x08", "cmpsxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xe9\x08", "cmpnsxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xe9\x08", "cmpnsxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xea\x08", "cmppxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xea\x08", "cmppxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xeb\x08", "cmpnpxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xeb\x08", "cmpnpxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xec\x08", "cmplxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xec\x08", "cmplxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xed\x08", "cmpnlxadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xed\x08", "cmpnlxadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xee\x08", "cmplexadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xee\x08", "cmplexadd qword ptr [rax], rcx, rbx"); + TEST64("\xc4\xe2\x61\xef\x08", "cmpnlexadd dword ptr [rax], ecx, ebx"); + TEST64("\xc4\xe2\xe1\xef\x08", "cmpnlexadd qword ptr [rax], rcx, rbx"); + + TEST("\x0f\xae\xe8", "lfence"); + TEST("\x0f\xae\xe9", "lfence"); + TEST("\x0f\xae\xef", "lfence"); + TEST("\x0f\xae\xf0", "mfence"); + TEST("\x0f\xae\xf7", "mfence"); + TEST("\x0f\xae\xf8", "sfence"); + TEST("\x0f\xae\xf9", "sfence"); + TEST("\x0f\xae\xff", "sfence"); + + TEST("\x0f\x6e\xc0", "movd mm0, eax"); + TEST64("\x48\x0f\x6e\xc0", "movq mm0, rax"); + TEST("\x0f\x70\xc0\x85", "pshufw mm0, mm0, 0x85"); + + TEST("\x0f\x58\xc1", "addps xmm0, xmm1"); + TEST64("\x40\x0f\x58\xc1", "addps xmm0, xmm1"); + TEST64("\x41\x0f\x58\xc1", "addps xmm0, xmm9"); + TEST64("\x42\x0f\x58\xc1", "addps xmm0, xmm1"); // REX.X ignored + TEST64("\x43\x0f\x58\xc1", "addps xmm0, xmm9"); // REX.X ignored + TEST64("\x44\x0f\x58\xc1", "addps xmm8, xmm1"); + TEST64("\x45\x0f\x58\xc1", "addps xmm8, xmm9"); + TEST64("\x46\x0f\x58\xc1", "addps xmm8, xmm1"); // REX.X ignored + TEST64("\x47\x0f\x58\xc1", "addps xmm8, xmm9"); // REX.X ignored + TEST("\xf3\x0f\x2a\xc1", "cvtsi2ss xmm0, ecx"); + TEST("\xf3\x66\x0f\x2a\xc1", "cvtsi2ss xmm0, ecx"); + TEST("\x66\xf3\x0f\x2a\xc1", "cvtsi2ss xmm0, ecx"); + TEST64("\xf3\x48\x0f\x2a\xc1", "cvtsi2ss xmm0, rcx"); + TEST64("\x66\xf3\x48\x0f\x2a\xc1", "cvtsi2ss xmm0, rcx"); + TEST64("\x66\x0f\x50\xc1", "movmskpd rax, xmm1"); + TEST("\x66\x0f\xc6\xc0\x01", "shufpd xmm0, xmm0, 0x1"); + TEST("\x66\x0f\x71\xd0\x01", "psrlw xmm0, 0x1"); + TEST("\x66\x0f\x3a\x20\xc4\x01", "pinsrb xmm0, spl, 0x1"); + TEST("\x66\x0f\x71\x10\x01", "UD"); + TEST("\x66\x0f\x78\xc0\xab\xcd", "extrq xmm0, 0xab, 0xcd"); + TEST("\xf2\x0f\x78\xc1\xab\xcd", "insertq xmm0, xmm1, 0xab, 0xcd"); + TEST("\x66\x0f\x38\x20\xc1", "pmovsxbw xmm0, xmm1"); + TEST("\x66\x0f\x38\x20\x00", "pmovsxbw xmm0, qword ptr [@ax]"); + TEST("\x66\x0f\x38\x21\xc1", "pmovsxbd xmm0, xmm1"); + TEST("\x66\x0f\x38\x21\x00", "pmovsxbd xmm0, dword ptr [@ax]"); + TEST("\x66\x0f\x38\x22\xc1", "pmovsxbq xmm0, xmm1"); + TEST("\x66\x0f\x38\x22\x00", "pmovsxbq xmm0, word ptr [@ax]"); + TEST("\x66\x0f\x38\x23\xc1", "pmovsxwd xmm0, xmm1"); + TEST("\x66\x0f\x38\x23\x00", "pmovsxwd xmm0, qword ptr [@ax]"); + TEST("\x66\x0f\x38\x24\xc1", "pmovsxwq xmm0, xmm1"); + TEST("\x66\x0f\x38\x24\x00", "pmovsxwq xmm0, dword ptr [@ax]"); + TEST("\x66\x0f\x38\x25\xc1", "pmovsxdq xmm0, xmm1"); + TEST("\x66\x0f\x38\x25\x00", "pmovsxdq xmm0, qword ptr [@ax]"); + TEST("\x66\x0f\x38\x30\xc1", "pmovzxbw xmm0, xmm1"); + TEST("\x66\x0f\x38\x30\x00", "pmovzxbw xmm0, qword ptr [@ax]"); + TEST("\x66\x0f\x38\x31\xc1", "pmovzxbd xmm0, xmm1"); + TEST("\x66\x0f\x38\x31\x00", "pmovzxbd xmm0, dword ptr [@ax]"); + TEST("\x66\x0f\x38\x32\xc1", "pmovzxbq xmm0, xmm1"); + TEST("\x66\x0f\x38\x32\x00", "pmovzxbq xmm0, word ptr [@ax]"); + TEST("\x66\x0f\x38\x33\xc1", "pmovzxwd xmm0, xmm1"); + TEST("\x66\x0f\x38\x33\x00", "pmovzxwd xmm0, qword ptr [@ax]"); + TEST("\x66\x0f\x38\x34\xc1", "pmovzxwq xmm0, xmm1"); + TEST("\x66\x0f\x38\x34\x00", "pmovzxwq xmm0, dword ptr [@ax]"); + TEST("\x66\x0f\x38\x35\xc1", "pmovzxdq xmm0, xmm1"); + TEST("\x66\x0f\x38\x35\x00", "pmovzxdq xmm0, qword ptr [@ax]"); + + TEST("\xc4", "PARTIAL"); + TEST("\xc5", "PARTIAL"); + TEST32("\xc4\xc0", "PARTIAL"); + TEST64("\xc4\x00", "PARTIAL"); + TEST32("\xc5\xc0", "PARTIAL"); + TEST64("\xc5\x00", "PARTIAL"); + TEST("\xc4\xe0\x78\x10\xc0", "UD"); // VEX map 0 + TEST("\xc4\xe1\x78\x10\xc0", "vmovups xmm0, xmm0"); // VEX map 1 + TEST("\xc4\xe2\x78\x10\xc0", "UD"); // VEX map 2 + TEST("\xc4\xe3\x78\x10\xc0\x00", "UD"); // VEX map 3 + TEST("\xc4\xe4\x78\x10\xc0", "UD"); // VEX map 4 + TEST("\xc4\xe5\x78\x10\xc0", "UD"); // VEX map 5 + TEST("\xc4\xe6\x78\x10\xc0", "UD"); // VEX map 6 + TEST("\xc4\xe7\x78\x10\xc0", "UD"); // VEX map 7 + TEST("\xc4\xe8\x78\x10\xc0", "UD"); // VEX map 8 + TEST("\xc4\xe9\x78\x10\xc0", "UD"); // VEX map 9 + TEST("\xc4\xea\x78\x10\xc0", "UD"); // VEX map 10 + TEST("\xc4\xeb\x78\x10\xc0", "UD"); // VEX map 11 + TEST("\xc4\xec\x78\x10\xc0", "UD"); // VEX map 12 + TEST("\xc4\xed\x78\x10\xc0", "UD"); // VEX map 13 + TEST("\xc4\xee\x78\x10\xc0", "UD"); // VEX map 14 + TEST("\xc4\xef\x78\x10\xc0", "UD"); // VEX map 15 + TEST("\xc4\xf0\x78\x10\xc0", "UD"); // VEX map 16 + TEST("\xc4\xf1\x78\x10\xc0", "UD"); // VEX map 17 + TEST("\xc4\xf2\x78\x10\xc0", "UD"); // VEX map 18 + TEST("\xc4\xf3\x78\x10\xc0", "UD"); // VEX map 19 + TEST("\xc4\xf4\x78\x10\xc0", "UD"); // VEX map 20 + TEST("\xc4\xf5\x78\x10\xc0", "UD"); // VEX map 21 + TEST("\xc4\xf6\x78\x10\xc0", "UD"); // VEX map 22 + TEST("\xc4\xf7\x78\x10\xc0", "UD"); // VEX map 23 + TEST("\xc4\xf8\x78\x10\xc0", "UD"); // VEX map 24 + TEST("\xc4\xf9\x78\x10\xc0", "UD"); // VEX map 25 + TEST("\xc4\xfa\x78\x10\xc0", "UD"); // VEX map 26 + TEST("\xc4\xfb\x78\x10\xc0", "UD"); // VEX map 27 + TEST("\xc4\xfc\x78\x10\xc0", "UD"); // VEX map 28 + TEST("\xc4\xfd\x78\x10\xc0", "UD"); // VEX map 29 + TEST("\xc4\xfe\x78\x10\xc0", "UD"); // VEX map 30 + TEST("\xc4\xff\x78\x10\xc0", "UD"); // VEX map 31 + TEST32("\xc4\x00", "les eax, fword ptr [eax]"); + TEST32("\xc5\x00", "lds eax, fword ptr [eax]"); + TEST("\x0f\xb2\x00", "lss eax, fword ptr [@ax]"); + TEST64("\x48\x0f\xb2\x00", "lss rax, tbyte ptr [rax]"); + TEST("\x0f\xb4\x00", "lfs eax, fword ptr [@ax]"); + TEST64("\x48\x0f\xb4\x00", "lfs rax, tbyte ptr [rax]"); + TEST("\x0f\xb5\x00", "lgs eax, fword ptr [@ax]"); + TEST64("\x48\x0f\xb5\x00", "lgs rax, tbyte ptr [rax]"); + TEST("\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); + TEST("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, @ax"); // VEX.W ignored + TEST("\xf3\xc5\xf2\x2a\xc0", "UD"); // VEX+REP + TEST("\xf2\xc5\xf2\x2a\xc0", "UD"); // VEX+REPNZ + TEST("\xf2\xf3\xc5\xf2\x2a\xc0", "UD"); // VEX+REP+REPNZ + TEST("\x66\xc5\xf2\x2a\xc0", "UD"); // VEX+66 + TEST("\xf0\xc5\xf2\x2a\xc0", "UD"); // VEX+LOCK + TEST64("\x40\xc5\xf2\x2a\xc0", "UD"); // VEX+REX + TEST64("\x40\x26\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); // VEX+REX, but REX doesn't precede VEX + + TEST("\xd9\x00", "fld dword ptr [@ax]"); + TEST("\xdd\x00", "fld qword ptr [@ax]"); + TEST("\xdb\x28", "fld tbyte ptr [@ax]"); + TEST("\xd9\xc1", "fld st(1)"); + TEST("\xdf\xe9", "fucomip st(0), st(1)"); + TEST64("\x45\xdf\xe9", "fucomip st(0), st(1)"); // REX.RB are ignored. + + TEST("\xf3\x0f\x7e\x5c\x24\x08", "movq xmm3, qword ptr [@sp+0x8]"); + TEST3264("\xc4\xe1\x00\x58\xc1", "vaddps xmm0, xmm7, xmm1", "vaddps xmm0, xmm15, xmm1"); // MSB in vvvv ignored + TEST3264("\xc4\xc1\x78\x58\xc0", "vaddps xmm0, xmm0, xmm0", "vaddps xmm0, xmm0, xmm8"); // VEX.B ignored in 32-bit + TEST("\xc5\xf9\x6e\xc8", "vmovd xmm1, eax"); + TEST64("\xc4\xe1\xf9\x6e\xc8", "vmovq xmm1, rax"); + TEST32("\xc4\xe1\xf9\x6e\xc8", "vmovd xmm1, eax"); + TEST("\xc5\xf9\x7e\xc8", "vmovd eax, xmm1"); + TEST64("\xc4\xe1\xf9\x7e\xc8", "vmovq rax, xmm1"); + TEST32("\xc4\xe1\xf9\x7e\xc8", "vmovd eax, xmm1"); + TEST("\xc5\xf2\x10\xc2", "vmovss xmm0, xmm1, xmm2"); + TEST("\xc5\xf6\x10\xc2", "vmovss xmm0, xmm1, xmm2"); // VEX.L=1 + TEST("\xc5\xfa\x10\x04\x25\x34\x12\x00\x00", "vmovss xmm0, dword ptr [0x1234]"); + TEST("\xc5\xf2\x10\x04\x25\x34\x12\x00\x00", "UD"); // VEX.vvvv != 0 + TEST("\xc5\xfa\x11\x04\x25\x34\x12\x00\x00", "vmovss dword ptr [0x1234], xmm0"); + TEST("\xc5\xf2\x11\x04\x25\x34\x12\x00\x00", "UD"); // VEX.vvvv != 0 + TEST("\xc5\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, eax"); + TEST("\xc4\xe1\xf2\x2a\xc0", "vcvtsi2ss xmm0, xmm1, @ax"); + TEST("\xc5\xf8\x53\xc0", "vrcpps xmm0, xmm0"); + TEST("\xc5\xf9\xf7\xc1", "vmaskmovdqu xmm0, xmm1"); + TEST("\xc5\xf9\xf7\x00", "UD"); // must have memory operand + TEST("\xc5\xfd\xf7\xc1", "UD"); // VEX.L != 0 + TEST64("\xc5\x07\xd0\x02", "vaddsubps ymm8, ymm15, ymmword ptr [rdx]"); + TEST("\xc4\xc3\x6d\x09\xd9\x85", "UD"); // VEX.vvvv != 0 + TEST3264("\xc4\xc3\x7d\x09\xd9\x85", "vroundpd ymm3, ymm1, 0x85", "vroundpd ymm3, ymm9, 0x85"); + TEST("\xc5\xff\xf0\xd1", "UD"); // must have memory operand + TEST("\xc5\xff\xf0\x11", "vlddqu ymm2, ymmword ptr [@cx]"); + + // VMOVDDUP with L0 has smaller second operand size. + TEST("\xf2\x0f\x12\x08", "movddup xmm1, qword ptr [@ax]"); + TEST("\xf2\x0f\x12\xc8", "movddup xmm1, xmm0"); + TEST("\xc5\xfb\x12\x08", "vmovddup xmm1, qword ptr [@ax]"); + TEST("\xc5\xfb\x12\xc8", "vmovddup xmm1, xmm0"); + TEST("\xc5\xff\x12\x08", "vmovddup ymm1, ymmword ptr [@ax]"); + TEST("\xc5\xff\x12\xc8", "vmovddup ymm1, ymm0"); + + TEST("\xc5\xf1\xe1\xc2", "vpsraw xmm0, xmm1, xmm2"); + TEST("\xc5\xf1\xe1\x00", "vpsraw xmm0, xmm1, xmmword ptr [@ax]"); + TEST("\xc5\xf5\xe1\xc2", "vpsraw ymm0, ymm1, xmm2"); + TEST("\xc5\xf5\xe1\x00", "vpsraw ymm0, ymm1, xmmword ptr [@ax]"); + TEST("\xc5\xf1\xe2\xc2", "vpsrad xmm0, xmm1, xmm2"); + TEST("\xc5\xf1\xe2\x00", "vpsrad xmm0, xmm1, xmmword ptr [@ax]"); + TEST("\xc5\xf5\xe2\xc2", "vpsrad ymm0, ymm1, xmm2"); + TEST("\xc5\xf5\xe2\x00", "vpsrad ymm0, ymm1, xmmword ptr [@ax]"); + TEST("\xc5\xf1\xd1\xc2", "vpsrlw xmm0, xmm1, xmm2"); + TEST("\xc5\xf1\xd1\x00", "vpsrlw xmm0, xmm1, xmmword ptr [@ax]"); + TEST("\xc5\xf5\xd1\xc2", "vpsrlw ymm0, ymm1, xmm2"); + TEST("\xc5\xf5\xd1\x00", "vpsrlw ymm0, ymm1, xmmword ptr [@ax]"); + TEST("\xc5\xf1\xd2\xc2", "vpsrld xmm0, xmm1, xmm2"); + TEST("\xc5\xf1\xd2\x00", "vpsrld xmm0, xmm1, xmmword ptr [@ax]"); + TEST("\xc5\xf5\xd2\xc2", "vpsrld ymm0, ymm1, xmm2"); + TEST("\xc5\xf5\xd2\x00", "vpsrld ymm0, ymm1, xmmword ptr [@ax]"); + TEST("\xc5\xf1\xd3\xc2", "vpsrlq xmm0, xmm1, xmm2"); + TEST("\xc5\xf1\xd3\x00", "vpsrlq xmm0, xmm1, xmmword ptr [@ax]"); + TEST("\xc5\xf5\xd3\xc2", "vpsrlq ymm0, ymm1, xmm2"); + TEST("\xc5\xf5\xd3\x00", "vpsrlq ymm0, ymm1, xmmword ptr [@ax]"); + TEST("\xc5\xf1\xf1\xc2", "vpsllw xmm0, xmm1, xmm2"); + TEST("\xc5\xf1\xf1\x00", "vpsllw xmm0, xmm1, xmmword ptr [@ax]"); + TEST("\xc5\xf5\xf1\xc2", "vpsllw ymm0, ymm1, xmm2"); + TEST("\xc5\xf5\xf1\x00", "vpsllw ymm0, ymm1, xmmword ptr [@ax]"); + TEST("\xc5\xf1\xf2\xc2", "vpslld xmm0, xmm1, xmm2"); + TEST("\xc5\xf1\xf2\x00", "vpslld xmm0, xmm1, xmmword ptr [@ax]"); + TEST("\xc5\xf5\xf2\xc2", "vpslld ymm0, ymm1, xmm2"); + TEST("\xc5\xf5\xf2\x00", "vpslld ymm0, ymm1, xmmword ptr [@ax]"); + TEST("\xc5\xf1\xf3\xc2", "vpsllq xmm0, xmm1, xmm2"); + TEST("\xc5\xf1\xf3\x00", "vpsllq xmm0, xmm1, xmmword ptr [@ax]"); + TEST("\xc5\xf5\xf3\xc2", "vpsllq ymm0, ymm1, xmm2"); + TEST("\xc5\xf5\xf3\x00", "vpsllq ymm0, ymm1, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x71\x47\xc2", "vpsllvd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x47\xc2", "vpsllvq xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x45\xc2", "vpsrlvd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x45\xc2", "vpsrlvq xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x46\xc2", "vpsravd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x46\xc2", "UD"); // VEX-encoded VPSRAVQ doesn't exist + + TEST("\xc4\xe3\x79\x14\xc0\x00", "vpextrb eax, xmm0, 0x0"); + TEST("\xc4\xe3\xf9\x14\xc0\x00", "vpextrb eax, xmm0, 0x0"); + TEST("\xc4\xe3\x79\x15\xc0\x00", "vpextrw eax, xmm0, 0x0"); + TEST("\xc4\xe3\xf9\x15\xc0\x00", "vpextrw eax, xmm0, 0x0"); + TEST("\xc4\xe1\x79\xc5\xc0\x00", "vpextrw eax, xmm0, 0x0"); + TEST("\xc4\xe3\x79\x16\xc0\x00", "vpextrd eax, xmm0, 0x0"); + TEST3264("\xc4\xe3\xf9\x16\xc0\x00", "vpextrd eax, xmm0, 0x0", "vpextrq rax, xmm0, 0x0"); + + TEST("\xc4\xe3\x71\x20\xc0\x00", "vpinsrb xmm0, xmm1, al, 0x0"); + TEST("\xc4\xe3\xf1\x20\xc0\x00", "vpinsrb xmm0, xmm1, al, 0x0"); + TEST("\xc4\xe3\x71\x20\xc6\x00", "vpinsrb xmm0, xmm1, sil, 0x0"); + TEST("\xc4\xe1\x71\xc4\xc0\x00", "vpinsrw xmm0, xmm1, ax, 0x0"); + TEST("\xc4\xe1\xf1\xc4\xc0\x00", "vpinsrw xmm0, xmm1, ax, 0x0"); + TEST("\xc4\xe3\x71\x22\xc0\x00", "vpinsrd xmm0, xmm1, eax, 0x0"); + TEST3264("\xc4\xe3\xf1\x22\xc0\x00", "vpinsrd xmm0, xmm1, eax, 0x0", "vpinsrq xmm0, xmm1, rax, 0x0"); + TEST("\xc4\xe3\x75\x20\xc0\x00", "UD"); // VEX.L != 0 + TEST("\xc4\xe1\x75\xc4\xc0\x00", "UD"); // VEX.L != 0 + TEST("\xc4\xe1\xf5\xc4\xc0\x00", "UD"); // VEX.L != 0 + TEST("\xc4\xe3\x75\x22\xc0\x00", "UD"); // VEX.L != 0 + TEST("\xc4\xe3\xf5\x22\xc0\x00", "UD"); // VEX.L != 0 + + TEST("\xc5\xf1\x71\xd7\x02", "vpsrlw xmm1, xmm7, 0x2"); + TEST("\xc5\xf5\x71\xd7\x02", "vpsrlw ymm1, ymm7, 0x2"); + TEST("\xc5\xf5\x71\x00\x02", "UD"); // Must have register operand + TEST("\xc4\xe2\x71\x45\xc2", "vpsrlvd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x75\x45\xc2", "vpsrlvd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf1\x45\xc2", "vpsrlvq xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf5\x45\xc2", "vpsrlvq ymm0, ymm1, ymm2"); + + TEST("\xc4\xe2\x79\x20\xc1", "vpmovsxbw xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x20\xc1", "vpmovsxbw ymm0, xmm1"); + TEST("\xc4\xe2\x79\x20\x00", "vpmovsxbw xmm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x20\x00", "vpmovsxbw ymm0, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x79\x21\xc1", "vpmovsxbd xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x21\xc1", "vpmovsxbd ymm0, xmm1"); + TEST("\xc4\xe2\x79\x21\x00", "vpmovsxbd xmm0, dword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x21\x00", "vpmovsxbd ymm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x79\x22\xc1", "vpmovsxbq xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x22\xc1", "vpmovsxbq ymm0, xmm1"); + TEST("\xc4\xe2\x79\x22\x00", "vpmovsxbq xmm0, word ptr [@ax]"); + TEST("\xc4\xe2\x7d\x22\x00", "vpmovsxbq ymm0, dword ptr [@ax]"); + TEST("\xc4\xe2\x79\x23\xc1", "vpmovsxwd xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x23\xc1", "vpmovsxwd ymm0, xmm1"); + TEST("\xc4\xe2\x79\x23\x00", "vpmovsxwd xmm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x23\x00", "vpmovsxwd ymm0, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x79\x24\xc1", "vpmovsxwq xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x24\xc1", "vpmovsxwq ymm0, xmm1"); + TEST("\xc4\xe2\x79\x24\x00", "vpmovsxwq xmm0, dword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x24\x00", "vpmovsxwq ymm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x79\x25\xc1", "vpmovsxdq xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x25\xc1", "vpmovsxdq ymm0, xmm1"); + TEST("\xc4\xe2\x79\x25\x00", "vpmovsxdq xmm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x25\x00", "vpmovsxdq ymm0, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x79\x30\xc1", "vpmovzxbw xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x30\xc1", "vpmovzxbw ymm0, xmm1"); + TEST("\xc4\xe2\x79\x30\x00", "vpmovzxbw xmm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x30\x00", "vpmovzxbw ymm0, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x79\x31\xc1", "vpmovzxbd xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x31\xc1", "vpmovzxbd ymm0, xmm1"); + TEST("\xc4\xe2\x79\x31\x00", "vpmovzxbd xmm0, dword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x31\x00", "vpmovzxbd ymm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x79\x32\xc1", "vpmovzxbq xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x32\xc1", "vpmovzxbq ymm0, xmm1"); + TEST("\xc4\xe2\x79\x32\x00", "vpmovzxbq xmm0, word ptr [@ax]"); + TEST("\xc4\xe2\x7d\x32\x00", "vpmovzxbq ymm0, dword ptr [@ax]"); + TEST("\xc4\xe2\x79\x33\xc1", "vpmovzxwd xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x33\xc1", "vpmovzxwd ymm0, xmm1"); + TEST("\xc4\xe2\x79\x33\x00", "vpmovzxwd xmm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x33\x00", "vpmovzxwd ymm0, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x79\x34\xc1", "vpmovzxwq xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x34\xc1", "vpmovzxwq ymm0, xmm1"); + TEST("\xc4\xe2\x79\x34\x00", "vpmovzxwq xmm0, dword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x34\x00", "vpmovzxwq ymm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x79\x35\xc1", "vpmovzxdq xmm0, xmm1"); + TEST("\xc4\xe2\x7d\x35\xc1", "vpmovzxdq ymm0, xmm1"); + TEST("\xc4\xe2\x79\x35\x00", "vpmovzxdq xmm0, qword ptr [@ax]"); + TEST("\xc4\xe2\x7d\x35\x00", "vpmovzxdq ymm0, xmmword ptr [@ax]"); + + TEST("\xc4\xe3\x71\x4a\xc2", "PARTIAL"); + TEST("\xc4\xe3\x71\x4a\xc2\x30", "vblendvps xmm0, xmm1, xmm2, xmm3"); + TEST3264("\xc4\xe3\x75\x4a\xc2\xf0", "vblendvps ymm0, ymm1, ymm2, ymm7", "vblendvps ymm0, ymm1, ymm2, ymm15"); // Bit 7 is ignored + TEST("\xc4\xe3\x71\x4b\xc2\x70", "vblendvpd xmm0, xmm1, xmm2, xmm7"); + TEST3264("\xc4\xe3\x75\x4b\xc2\x80", "vblendvpd ymm0, ymm1, ymm2, ymm0", "vblendvpd ymm0, ymm1, ymm2, ymm8"); // Bit 7 is ignored + TEST3264("\xc4\xc3\xfd\x00\xc9\x12", "vpermq ymm1, ymm1, 0x12", "vpermq ymm1, ymm9, 0x12"); // VEX.B ignored + TEST("\xc4\xc3\x7d\x00\xc9\x12", "UD"); // VEX.W = 0 is UD + TEST("\xc4\xe3\xfd\x01\xcf\x12", "vpermpd ymm1, ymm7, 0x12"); + + TEST("\xc4\xe2\x71\x96\xc2", "vfmaddsub132ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x96\x06", "vfmaddsub132ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\x96\xc2", "vfmaddsub132ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\x96\x06", "vfmaddsub132ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\x96\xc2", "vfmaddsub132pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x96\x06", "vfmaddsub132pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\x96\xc2", "vfmaddsub132pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\x96\x06", "vfmaddsub132pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\x97\xc2", "vfmsubadd132ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x97\x06", "vfmsubadd132ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\x97\xc2", "vfmsubadd132ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\x97\x06", "vfmsubadd132ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\x97\xc2", "vfmsubadd132pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x97\x06", "vfmsubadd132pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\x97\xc2", "vfmsubadd132pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\x97\x06", "vfmsubadd132pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\x98\xc2", "vfmadd132ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x98\x06", "vfmadd132ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\x98\xc2", "vfmadd132ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\x98\x06", "vfmadd132ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\x98\xc2", "vfmadd132pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x98\x06", "vfmadd132pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\x98\xc2", "vfmadd132pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\x98\x06", "vfmadd132pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\x99\xc2", "vfmadd132ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x99\x06", "vfmadd132ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\x99\xc2", "vfmadd132sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x99\x06", "vfmadd132sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\x9a\xc2", "vfmsub132ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x9a\x06", "vfmsub132ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\x9a\xc2", "vfmsub132ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\x9a\x06", "vfmsub132ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\x9a\xc2", "vfmsub132pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x9a\x06", "vfmsub132pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\x9a\xc2", "vfmsub132pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\x9a\x06", "vfmsub132pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\x9b\xc2", "vfmsub132ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x9b\x06", "vfmsub132ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\x9b\xc2", "vfmsub132sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x9b\x06", "vfmsub132sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\x9c\xc2", "vfnmadd132ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x9c\x06", "vfnmadd132ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\x9c\xc2", "vfnmadd132ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\x9c\x06", "vfnmadd132ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\x9c\xc2", "vfnmadd132pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x9c\x06", "vfnmadd132pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\x9c\xc2", "vfnmadd132pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\x9c\x06", "vfnmadd132pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\x9d\xc2", "vfnmadd132ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x9d\x06", "vfnmadd132ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\x9d\xc2", "vfnmadd132sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x9d\x06", "vfnmadd132sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\x9e\xc2", "vfnmsub132ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x9e\x06", "vfnmsub132ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\x9e\xc2", "vfnmsub132ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\x9e\x06", "vfnmsub132ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\x9e\xc2", "vfnmsub132pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x9e\x06", "vfnmsub132pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\x9e\xc2", "vfnmsub132pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\x9e\x06", "vfnmsub132pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\x9f\xc2", "vfnmsub132ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\x9f\x06", "vfnmsub132ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\x9f\xc2", "vfnmsub132sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\x9f\x06", "vfnmsub132sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\xa6\xc2", "vfmaddsub213ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xa6\x06", "vfmaddsub213ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xa6\xc2", "vfmaddsub213ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xa6\x06", "vfmaddsub213ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xa6\xc2", "vfmaddsub213pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xa6\x06", "vfmaddsub213pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xa6\xc2", "vfmaddsub213pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xa6\x06", "vfmaddsub213pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xa7\xc2", "vfmsubadd213ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xa7\x06", "vfmsubadd213ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xa7\xc2", "vfmsubadd213ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xa7\x06", "vfmsubadd213ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xa7\xc2", "vfmsubadd213pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xa7\x06", "vfmsubadd213pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xa7\xc2", "vfmsubadd213pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xa7\x06", "vfmsubadd213pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xa8\xc2", "vfmadd213ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xa8\x06", "vfmadd213ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xa8\xc2", "vfmadd213ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xa8\x06", "vfmadd213ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xa8\xc2", "vfmadd213pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xa8\x06", "vfmadd213pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xa8\xc2", "vfmadd213pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xa8\x06", "vfmadd213pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xa9\xc2", "vfmadd213ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xa9\x06", "vfmadd213ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\xa9\xc2", "vfmadd213sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xa9\x06", "vfmadd213sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\xaa\xc2", "vfmsub213ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xaa\x06", "vfmsub213ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xaa\xc2", "vfmsub213ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xaa\x06", "vfmsub213ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xaa\xc2", "vfmsub213pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xaa\x06", "vfmsub213pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xaa\xc2", "vfmsub213pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xaa\x06", "vfmsub213pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xab\xc2", "vfmsub213ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xab\x06", "vfmsub213ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\xab\xc2", "vfmsub213sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xab\x06", "vfmsub213sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\xac\xc2", "vfnmadd213ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xac\x06", "vfnmadd213ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xac\xc2", "vfnmadd213ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xac\x06", "vfnmadd213ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xac\xc2", "vfnmadd213pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xac\x06", "vfnmadd213pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xac\xc2", "vfnmadd213pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xac\x06", "vfnmadd213pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xad\xc2", "vfnmadd213ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xad\x06", "vfnmadd213ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\xad\xc2", "vfnmadd213sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xad\x06", "vfnmadd213sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\xae\xc2", "vfnmsub213ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xae\x06", "vfnmsub213ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xae\xc2", "vfnmsub213ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xae\x06", "vfnmsub213ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xae\xc2", "vfnmsub213pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xae\x06", "vfnmsub213pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xae\xc2", "vfnmsub213pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xae\x06", "vfnmsub213pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xaf\xc2", "vfnmsub213ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xaf\x06", "vfnmsub213ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\xaf\xc2", "vfnmsub213sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xaf\x06", "vfnmsub213sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\xb6\xc2", "vfmaddsub231ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xb6\x06", "vfmaddsub231ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xb6\xc2", "vfmaddsub231ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xb6\x06", "vfmaddsub231ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xb6\xc2", "vfmaddsub231pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xb6\x06", "vfmaddsub231pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xb6\xc2", "vfmaddsub231pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xb6\x06", "vfmaddsub231pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xb7\xc2", "vfmsubadd231ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xb7\x06", "vfmsubadd231ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xb7\xc2", "vfmsubadd231ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xb7\x06", "vfmsubadd231ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xb7\xc2", "vfmsubadd231pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xb7\x06", "vfmsubadd231pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xb7\xc2", "vfmsubadd231pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xb7\x06", "vfmsubadd231pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xb8\xc2", "vfmadd231ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xb8\x06", "vfmadd231ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xb8\xc2", "vfmadd231ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xb8\x06", "vfmadd231ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xb8\xc2", "vfmadd231pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xb8\x06", "vfmadd231pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xb8\xc2", "vfmadd231pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xb8\x06", "vfmadd231pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xb9\xc2", "vfmadd231ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xb9\x06", "vfmadd231ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\xb9\xc2", "vfmadd231sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xb9\x06", "vfmadd231sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\xba\xc2", "vfmsub231ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xba\x06", "vfmsub231ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xba\xc2", "vfmsub231ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xba\x06", "vfmsub231ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xba\xc2", "vfmsub231pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xba\x06", "vfmsub231pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xba\xc2", "vfmsub231pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xba\x06", "vfmsub231pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xbb\xc2", "vfmsub231ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xbb\x06", "vfmsub231ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\xbb\xc2", "vfmsub231sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xbb\x06", "vfmsub231sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\xbc\xc2", "vfnmadd231ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xbc\x06", "vfnmadd231ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xbc\xc2", "vfnmadd231ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xbc\x06", "vfnmadd231ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xbc\xc2", "vfnmadd231pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xbc\x06", "vfnmadd231pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xbc\xc2", "vfnmadd231pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xbc\x06", "vfnmadd231pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xbd\xc2", "vfnmadd231ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xbd\x06", "vfnmadd231ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\xbd\xc2", "vfnmadd231sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xbd\x06", "vfnmadd231sd xmm0, xmm1, qword ptr [@si]"); + TEST("\xc4\xe2\x71\xbe\xc2", "vfnmsub231ps xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xbe\x06", "vfnmsub231ps xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\x75\xbe\xc2", "vfnmsub231ps ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x75\xbe\x06", "vfnmsub231ps ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\xf1\xbe\xc2", "vfnmsub231pd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xbe\x06", "vfnmsub231pd xmm0, xmm1, xmmword ptr [@si]"); + TEST("\xc4\xe2\xf5\xbe\xc2", "vfnmsub231pd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf5\xbe\x06", "vfnmsub231pd ymm0, ymm1, ymmword ptr [@si]"); + TEST("\xc4\xe2\x71\xbf\xc2", "vfnmsub231ss xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x71\xbf\x06", "vfnmsub231ss xmm0, xmm1, dword ptr [@si]"); + TEST("\xc4\xe2\xf1\xbf\xc2", "vfnmsub231sd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf1\xbf\x06", "vfnmsub231sd xmm0, xmm1, qword ptr [@si]"); + + TEST("\xc4\xe2\x79\xdb\xc1", "vaesimc xmm0, xmm1"); + TEST("\xc4\xe2\x7d\xdb\xc1", "UD"); // VEX.L != 0 + TEST("\xc4\xe3\x79\xdf\xc1\xae", "vaeskeygenassist xmm0, xmm1, 0xae"); + TEST("\xc4\xe3\x7d\xdf\xc1\xae", "UD"); // VEX.L != 0 + TEST("\xc4\xe2\x71\xdc\xc2", "vaesenc xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x75\xdc\xc2", "vaesenc ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x71\xdd\xc2", "vaesenclast xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x75\xdd\xc2", "vaesenclast ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x71\xde\xc2", "vaesdec xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x75\xde\xc2", "vaesdec ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x71\xdf\xc2", "vaesdeclast xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x75\xdf\xc2", "vaesdeclast ymm0, ymm1, ymm2"); + + TEST("\xc4\xe2\x70\x50\xc2", "vpdpbuud xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x74\x50\xc2", "vpdpbuud ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x71\x50\xc2", "vpdpbusd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x75\x50\xc2", "vpdpbusd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x72\x50\xc2", "vpdpbsud xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x76\x50\xc2", "vpdpbsud ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x73\x50\xc2", "vpdpbssd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x77\x50\xc2", "vpdpbssd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x70\x51\xc2", "vpdpbuuds xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x74\x51\xc2", "vpdpbuuds ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x71\x51\xc2", "vpdpbusds xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x75\x51\xc2", "vpdpbusds ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x72\x51\xc2", "vpdpbsuds xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x76\x51\xc2", "vpdpbsuds ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x73\x51\xc2", "vpdpbssds xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x77\x51\xc2", "vpdpbssds ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x71\x52\xc2", "vpdpwssd xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x75\x52\xc2", "vpdpwssd ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\x71\x53\xc2", "vpdpwssds xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\x75\x53\xc2", "vpdpwssds ymm0, ymm1, ymm2"); + + TEST("\xc4\xe2\x78\xb0\xc8", "UD"); // Must have memory operand + TEST("\xc4\xe2\x78\xb0\x08", "vcvtneoph2ps xmm1, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x7c\xb0\x08", "vcvtneoph2ps ymm1, ymmword ptr [@ax]"); + TEST("\xc4\xe2\x79\xb0\xc8", "UD"); // Must have memory operand + TEST("\xc4\xe2\x79\xb0\x08", "vcvtneeph2ps xmm1, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x7d\xb0\x08", "vcvtneeph2ps ymm1, ymmword ptr [@ax]"); + TEST("\xc4\xe2\x7a\xb0\xc8", "UD"); // Must have memory operand + TEST("\xc4\xe2\x7a\xb0\x08", "vcvtneebf162ps xmm1, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x7e\xb0\x08", "vcvtneebf162ps ymm1, ymmword ptr [@ax]"); + TEST("\xc4\xe2\x7b\xb0\xc8", "UD"); // Must have memory operand + TEST("\xc4\xe2\x7b\xb0\x08", "vcvtneobf162ps xmm1, xmmword ptr [@ax]"); + TEST("\xc4\xe2\x7f\xb0\x08", "vcvtneobf162ps ymm1, ymmword ptr [@ax]"); + TEST("\xc4\xe2\x79\xb1\xc8", "UD"); // Must have memory operand + TEST("\xc4\xe2\x79\xb1\x08", "vbcstnesh2ps xmm1, word ptr [@ax]"); + TEST("\xc4\xe2\x7d\xb1\x08", "vbcstnesh2ps ymm1, word ptr [@ax]"); + TEST("\xc4\xe2\x7a\xb1\xc8", "UD"); // Must have memory operand + TEST("\xc4\xe2\x7a\xb1\x08", "vbcstnebf162ps xmm1, word ptr [@ax]"); + TEST("\xc4\xe2\x7e\xb1\x08", "vbcstnebf162ps ymm1, word ptr [@ax]"); + TEST("\xc4\xe2\x7a\x72\xc1", "vcvtneps2bf16 xmm0, xmm1"); + TEST("\xc4\xe2\x7e\x72\xc1", "vcvtneps2bf16 xmm0, ymm1"); + + TEST("\xc4\xe2\xf1\xb4\xc2", "vpmadd52luq xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf5\xb4\xc2", "vpmadd52luq ymm0, ymm1, ymm2"); + TEST("\xc4\xe2\xf1\xb5\xc2", "vpmadd52huq xmm0, xmm1, xmm2"); + TEST("\xc4\xe2\xf5\xb5\xc2", "vpmadd52huq ymm0, ymm1, ymm2"); + + TEST("\xc4\xe2\x71\x92\xc0", "UD"); // Must have memory operand + TEST("\xc4\xe2\x71\x92\x00", "UD"); // Must have SIB byte + TEST("\xc4\xe2\x71\x92\x05\x00\x00\x00\x00", "UD"); // Must have SIB byte + TEST3264("\x67\xc4\xe2\x71\x92\x04\xe7", "UD", "vgatherdps xmm0, dword ptr [edi+8*xmm4], xmm1"); // VSIB + 16-bit addrsize is UD + TEST("\xc4\xe2\x71\x92\x04\xe7", "vgatherdps xmm0, dword ptr [@di+8*xmm4], xmm1"); + TEST("\xc4\xe2\x75\x92\x04\xe7", "vgatherdps ymm0, dword ptr [@di+8*ymm4], ymm1"); + TEST("\xc4\xe2\x71\x93\x04\xe7", "vgatherqps xmm0, dword ptr [@di+8*xmm4], xmm1"); + TEST("\xc4\xe2\x75\x93\x04\xe7", "vgatherqps xmm0, dword ptr [@di+8*ymm4], xmm1"); + TEST("\xc4\xe2\xf1\x92\x04\xe7", "vgatherdpd xmm0, qword ptr [@di+8*xmm4], xmm1"); + TEST("\xc4\xe2\xf5\x92\x04\xe7", "vgatherdpd ymm0, qword ptr [@di+8*xmm4], ymm1"); + TEST("\xc4\xe2\xf1\x93\x04\xe7", "vgatherqpd xmm0, qword ptr [@di+8*xmm4], xmm1"); + TEST("\xc4\xe2\xf5\x93\x04\xe7", "vgatherqpd ymm0, qword ptr [@di+8*ymm4], ymm1"); + TEST("\xc4\xe2\x71\x90\x04\xe7", "vpgatherdd xmm0, dword ptr [@di+8*xmm4], xmm1"); + TEST("\xc4\xe2\x75\x90\x04\xe7", "vpgatherdd ymm0, dword ptr [@di+8*ymm4], ymm1"); + TEST("\xc4\xe2\x71\x91\x04\xe7", "vpgatherqd xmm0, dword ptr [@di+8*xmm4], xmm1"); + TEST("\xc4\xe2\x75\x91\x04\xe7", "vpgatherqd xmm0, dword ptr [@di+8*ymm4], xmm1"); + TEST("\xc4\xe2\xf1\x90\x04\xe7", "vpgatherdq xmm0, qword ptr [@di+8*xmm4], xmm1"); + TEST("\xc4\xe2\xf5\x90\x04\xe7", "vpgatherdq ymm0, qword ptr [@di+8*xmm4], ymm1"); + TEST("\xc4\xe2\xf1\x91\x04\xe7", "vpgatherqq xmm0, qword ptr [@di+8*xmm4], xmm1"); + TEST("\xc4\xe2\xf5\x91\x04\xe7", "vpgatherqq ymm0, qword ptr [@di+8*ymm4], ymm1"); + + TEST("\xc4\xe2\x7d\x5a\x20", "vbroadcasti128 ymm4, xmmword ptr [@ax]"); + TEST64("\xc4\x62\x7d\x5a\x20", "vbroadcasti128 ymm12, xmmword ptr [rax]"); + TEST("\xc4\xe2\x75\x5a\x20", "UD"); // VEX.vvvv != 1111 + TEST("\xc4\xe2\x7d\x5a\xc0", "UD"); // ModRM.mod != 11 + TEST("\xc4\xe2\x79\x5a\x20", "UD"); // VEX.L != 1 + TEST("\xc4\xe2\xfd\x5a\x20", "UD"); // VEX.W != 0 + + // Intel-Syntax special cases + TEST("\x66\x98", "cbw"); + TEST("\x98", "cwde"); + TEST64("\x48\x98", "cdqe"); + TEST("\x66\x99", "cwd"); + TEST("\x99", "cdq"); + TEST64("\x48\x99", "cqo"); + + TEST("\x0f\xae\x00", "fxsave [@ax]"); + TEST64("\x48\x0f\xae\x00", "fxsave64 [rax]"); + TEST("\x0f\xae\x08", "fxrstor [@ax]"); + TEST64("\x48\x0f\xae\x08", "fxrstor64 [rax]"); + TEST("\x0f\xae\x20", "xsave [@ax]"); + TEST64("\x48\x0f\xae\x20", "xsave64 [rax]"); + TEST("\x0f\xc7\x20", "xsavec [@ax]"); + TEST64("\x48\x0f\xc7\x20", "xsavec64 [rax]"); + TEST("\x0f\xae\x30", "xsaveopt [@ax]"); + TEST64("\x48\x0f\xae\x30", "xsaveopt64 [rax]"); + TEST("\x0f\xc7\x28", "xsaves [@ax]"); + TEST64("\x48\x0f\xc7\x28", "xsaves64 [rax]"); + TEST("\x0f\xae\x28", "xrstor [@ax]"); + TEST64("\x48\x0f\xae\x28", "xrstor64 [rax]"); + TEST("\x0f\xc7\x18", "xrstors [@ax]"); + TEST64("\x48\x0f\xc7\x18", "xrstors64 [rax]"); + TEST("\xff\xe0", "jmp @ax"); + TEST3264("\x66\xff\xe0", "jmp ax", "jmp rax"); + TEST64("\x48\xff\xe0", "jmp rax"); + TEST("\xff\xd0", "call @ax"); + TEST3264("\x66\xff\xd0", "call ax", "call rax"); + TEST64("\x48\xff\xd0", "call rax"); + TEST3264("\x66\x70\x00", "jow 0x3", "jo 0x3"); + TEST("\xe3\xfe", "j@cxz 0x0"); + TEST3264("\x67\xe3\xfd", "jcxz 0x0", "jecxz 0x0"); + TEST3264("\xff\x20", "jmp dword ptr [eax]", "jmp qword ptr [rax]"); + TEST3264("\x66\xff\x20", "jmp word ptr [eax]", "jmp qword ptr [rax]"); + TEST64("\x48\xff\x20", "jmp qword ptr [rax]"); + TEST("\xff\x28", "jmp far fword ptr [@ax]"); + TEST("\x66\xff\x28", "jmp far dword ptr [@ax]"); + TEST64("\x48\xff\x28", "jmp far tbyte ptr [rax]"); + TEST3264("\xea\x11\x22\x33\x44\x55\x66", "jmp far 0x6655:0x44332211", "UD"); + TEST3264("\x66\xea\x11\x22\x33\x44", "jmp far 0x4433:0x2211", "UD"); + TEST32("\x66\x9a\x23\x01\x23\x00", "call far 0x23:0x123"); + TEST32("\x9a\x67\x45\x23\x01\x23\x00", "call far 0x23:0x1234567"); + TEST32("\x9a\xff\xff\xff\xff\xff\xff", "call far 0xffff:0xffffffff"); + TEST("\x66\xff\x1f", "call far dword ptr [@di]"); + TEST("\xff\x1f", "call far fword ptr [@di]"); + TEST64("\x48\xff\x1f", "call far tbyte ptr [rdi]"); + TEST("\x0f\xb4", "PARTIAL"); + TEST("\x66\x0f\xb4\x07", "lfs ax, dword ptr [@di]"); + TEST("\x0f\xb4\x07", "lfs eax, fword ptr [@di]"); + TEST64("\x48\x0f\xb4\x07", "lfs rax, tbyte ptr [rdi]"); + TEST("\xa5", "movsd"); + TEST("\x64\xa5", "fs movsd"); + TEST3264("\x2e\xa5", "cs movsd", "movsd"); + TEST3264("\x67\xa5", "addr16 movsd", "addr32 movsd"); + TEST("\xaf", "scasd"); + TEST("\x64\xaf", "scasd"); // SCAS doesn't use segment overrides + TEST("\xec", "inb"); + TEST("\x66\xed", "inw"); + TEST("\xed", "ind"); + // TEST64("\x48\xed", "ind"); // TODO + // TEST64("\x66\x48\xed", "ind"); // TODO + TEST("\xee", "outb"); + TEST("\x66\xef", "outw"); + TEST("\xef", "outd"); + // TEST64("\x48\xef", "outd"); // TODO + // TEST64("\x66\x48\xef", "outd"); // TODO + TEST("\xe4\x00", "in al, 0x0"); + TEST("\xe4\xff", "in al, 0xff"); + TEST("\x66\xe5\xff", "in ax, 0xff"); + TEST("\xe5\xff", "in eax, 0xff"); + // TEST64("\x66\x48\xe5\xff", "in eax, 0xff"); // TODO + // TEST64("\x48\xe5\xff", "in eax, 0xff"); // TODO + TEST("\xe6\x00", "out al, 0x0"); + TEST("\xe6\xff", "out al, 0xff"); + TEST("\x66\xe7\xff", "out ax, 0xff"); + TEST("\xe7\xff", "out eax, 0xff"); + // TEST64("\x66\x48\xe7\xff", "out eax, 0xff"); // TODO + // TEST64("\x48\xe7\xff", "out eax, 0xff"); // TODO + TEST32("\x66\x61", "popaw"); + TEST32("\x61", "popad"); + TEST("\x66\x9c", "pushfw"); + TEST3264("\x9c", "pushfd", "pushfq"); + TEST("\x66\x9d", "popfw"); + TEST3264("\x9d", "popfd", "popfq"); + TEST("\x66\xcf", "iretw"); + TEST("\xcf", "iretd"); + TEST64("\x48\xcf", "iretq"); + TEST32("\x06", "push es"); + TEST32("\x66\x06", "pushw es"); + TEST32("\x07", "pop es"); + TEST32("\x66\x07", "popw es"); + TEST32("\x0e", "push cs"); + TEST32("\x66\x0e", "pushw cs"); + TEST32("\x16", "push ss"); + TEST32("\x66\x16", "pushw ss"); + TEST32("\x17", "pop ss"); + TEST32("\x66\x17", "popw ss"); + TEST("\x0f\xa8", "push gs"); + TEST("\x66\x0f\xa8", "pushw gs"); + TEST("\x0f\xa9", "pop gs"); + TEST("\x66\x0f\xa9", "popw gs"); + TEST("\x0f\x21\xd0", "mov @ax, dr2"); + TEST32("\x62\x00", "bound eax, qword ptr [eax]"); + TEST32("\x66\x62\x00", "bound ax, dword ptr [eax]"); + TEST("\x0f\xae\x38", "clflush byte ptr [@ax]"); + TEST("\xdd\x00", "fld qword ptr [@ax]"); + TEST("\xdb\x28", "fld tbyte ptr [@ax]"); + TEST("\xd9\x20", "fldenv [@ax]"); + + // MPX +#if 0 + TEST("\x66\x0f\x1a\xc1", "bndmov bnd0, bnd1"); + TEST("\x66\x0f\x1a\xc4", "UD"); // ModRM bnd4 is undefined + TEST64("\x41\x66\x0f\x1a\xc0", "UD"); // ModRM bnd8 is undefined + TEST("\xf3\x0f\x1b\x00", "bndmk bnd0, [@ax]"); + TEST64("\x0f\x1a\x05\x00\x00\x00\x00", "UD"); // BNDSTX+RIP-rel = UD + TEST64("\x0f\x1b\x05\x00\x00\x00\x00", "UD"); // BNDLDX+RIP-rel = UD + TEST64("\xf3\x0f\x1b\x05\x00\x00\x00\x00", "UD"); // BNDMK+RIP-rel = UD +#endif + TEST("\xf3\x0f\x1b\xc0", "nop eax, eax"); // BNDMK with reg/reg remains NOP + + // 3DNow! + TEST("\x0f\x0f\xc0\x00", "UD"); + TEST("\x0f\x0f\xc0\x0c", "3dnow mm0, mm0, 0xc"); // PI2FW + TEST("\x0f\x0f\xc0\x0d", "3dnow mm0, mm0, 0xd"); // PI2FD + TEST("\x0f\x0f\xc0\x0e", "UD"); + TEST("\x0f\x0f\xc0\x1c", "3dnow mm0, mm0, 0x1c"); // PF2IW + TEST("\x0f\x0f\xc0\x1d", "3dnow mm0, mm0, 0x1d"); // PF2ID + TEST("\x0f\x0f\xc0\x42", "UD"); + TEST("\x0f\x0f\xc0\x80", "UD"); + TEST("\x0f\x0f\xc0\x8a", "3dnow mm0, mm0, 0x8a"); // PFNACC + TEST("\x0f\x0f\xc0\xa0", "3dnow mm0, mm0, 0xa0"); // PFCMPGT + TEST("\x0f\x0f\xc0\xb6", "3dnow mm0, mm0, 0xb6"); // PFRCPIT2 + TEST("\x0f\x0f\xc0\xbf", "3dnow mm0, mm0, 0xbf"); // PAVGUSB + + TEST("\x0f\x01\xfc", "clzero eax"); + TEST("\x66\x0f\x01\xfc", "clzero ax"); + TEST64("\x48\x0f\x01\xfc", "clzero rax"); + + // VIA PadLock + TEST("\x0f\xa7\xc0", "xstore"); + TEST("\xf3\x0f\xa7\xc0", "rep xstore"); + TEST("\xf2\x0f\xa7\xc0", "UD"); + TEST("\x0f\xa7\xe8 ", "UD"); + TEST("\xf2\x0f\xa7\xe8", "UD"); + TEST("\xf3\x0f\xa7\xe8", "rep xcryptofb"); + + // Maximum instruction length is 15 bytes. + TEST("\x66\x66\x66\x66\x66\x66\x66\x66\x66\x66\x66\x66\x66\x66\x66\x90", "PARTIAL"); + + // AMX + TEST64("\xc4\xe2\x78\x49\x00", "ldtilecfg [rax]"); + TEST64("\xc4\xe2\x79\x49\x00", "sttilecfg [rax]"); + TEST64("\xc4\xe2\x78\x49\xc0", "tilerelease"); + TEST64("\xc4\xe2\x7b\x49\x00", "UD"); // ModRM.mod != 11 + TEST64("\xc4\xe2\x7b\x49\xc0", "tilezero tmm0"); + TEST64("\xc4\xe2\x7b\x49\xc1", "UD"); // ModRM.rm != 0 + TEST64("\xc4\xe2\x7b\x49\xc7", "UD"); // ModRM.rm != 0 + TEST64("\xc4\xe2\x7b\x49\xc8", "tilezero tmm1"); + TEST64("\xc4\xe2\x7b\x49\xf8", "tilezero tmm7"); + TEST64("\xc4\x02\x7b\x49\xf8", "tilezero tmm7"); // VEX.RXB ignored + TEST64("\xc4\xe2\x7b\x4b\x04\x10", "tileloadd tmm0, [rax+1*rdx]"); + TEST64("\xc4\xe2\x7b\x4b\x04\x20", "tileloadd tmm0, [rax]"); // riz + TEST64("\xc4\x02\x7b\x4b\x3c\x10", "tileloadd tmm7, [r8+1*r10]"); // VEX.R ignored + TEST64("\xc4\xe2\x7b\x4b\x00", "UD"); // must have SIB byte + TEST64("\xc4\xe2\x7b\x4b\xff", "UD"); // must have memory operand + TEST64("\xc4\xe2\x79\x4b\x04\x10", "tileloaddt1 tmm0, [rax+1*rdx]"); + TEST64("\xc4\xe2\x79\x4b\x04\x20", "tileloaddt1 tmm0, [rax]"); // riz + TEST64("\xc4\x02\x79\x4b\x3c\x10", "tileloaddt1 tmm7, [r8+1*r10]"); // VEX.R ignored + TEST64("\xc4\xe2\x79\x4b\x00", "UD"); // must have SIB byte + TEST64("\xc4\xe2\x79\x4b\xff", "UD"); // must have memory operand + TEST64("\xc4\xe2\x7a\x4b\x04\x10", "tilestored [rax+1*rdx], tmm0"); + TEST64("\xc4\xe2\x7a\x4b\x04\x20", "tilestored [rax], tmm0"); // riz + TEST64("\xc4\x02\x7a\x4b\x3c\x10", "tilestored [r8+1*r10], tmm7"); // VEX.R ignored + TEST64("\xc4\xe2\x7a\x4b\x00", "UD"); // must have SIB byte + TEST64("\xc4\xe2\x7a\x4b\xff", "UD"); // must have memory operand + TEST64("\xc4\xe2\x68\x5e\x00", "UD"); // must have register operand + TEST64("\xc4\xe2\x68\x5e\xc8", "tdpbuud tmm1, tmm0, tmm2"); + TEST64("\xc4\x02\x28\x5e\xc8", "tdpbuud tmm1, tmm0, tmm2"); // VEX.RBV3 ignored + // TODO: enforce that all registers must be different + //TEST64("\xc4\xe2\x68\x5e\xc0", "UD"); // ModRM.rm == ModRM.reg + //TEST64("\xc4\xe2\x68\x5e\xca", "UD"); // ModRM.rm == VEX.vvvv + //TEST64("\xc4\xe2\x68\x5e\xd0", "UD"); // ModRM.reg == VEX.vvvv + TEST64("\xc4\xe2\x6a\x5c\xc8", "tdpbf16ps tmm1, tmm0, tmm2"); + TEST64("\xc4\xe2\x6b\x5c\xc8", "tdpfp16ps tmm1, tmm0, tmm2"); + TEST64("\xc4\xe2\x68\x5e\xc8", "tdpbuud tmm1, tmm0, tmm2"); + TEST64("\xc4\xe2\x69\x5e\xc8", "tdpbusd tmm1, tmm0, tmm2"); + TEST64("\xc4\xe2\x6a\x5e\xc8", "tdpbsud tmm1, tmm0, tmm2"); + TEST64("\xc4\xe2\x6b\x5e\xc8", "tdpbssd tmm1, tmm0, tmm2"); + TEST64("\xc4\xe2\x68\x6c\xc8", "tcmmrlfp16ps tmm1, tmm0, tmm2"); + TEST64("\xc4\xe2\x69\x6c\xc8", "tcmmimfp16ps tmm1, tmm0, tmm2"); + + // Complete test of VADDPS and all encoding options + TEST("\x62", "PARTIAL"); + TEST("\x62\xf1", "PARTIAL"); + TEST("\x62\xf1\x74", "PARTIAL"); + TEST("\x62\xf1\x74\x18", "PARTIAL"); + TEST("\x62\xf1\x74\x18\x58", "PARTIAL"); + TEST("\x62\xf1\x74\x18\x58\xc2", "vaddps zmm0, zmm1, zmm2, {rn-sae}"); + TEST("\x62\xf1\x74\x38\x58\xc2", "vaddps zmm0, zmm1, zmm2, {rd-sae}"); + TEST("\x62\xf1\x74\x58\x58\xc2", "vaddps zmm0, zmm1, zmm2, {ru-sae}"); + TEST("\x62\xf1\x74\x78\x58\xc2", "vaddps zmm0, zmm1, zmm2, {rz-sae}"); + TEST("\x62\xf1\x74\x08\x58\xc2", "vaddps xmm0, xmm1, xmm2"); + TEST("\x62\xf1\x74\x09\x58\xc2", "vaddps xmm0{k1}, xmm1, xmm2"); + TEST("\x62\xf1\x74\x89\x58\xc2", "vaddps xmm0{k1}{z}, xmm1, xmm2"); + TEST("\x62\xf1\x74\x88\x58\xc2", "UD"); // EVEX.z = 1 + TEST("\x62\xf1\x74\x28\x58\xc2", "vaddps ymm0, ymm1, ymm2"); + TEST("\x62\xf1\x74\x29\x58\xc2", "vaddps ymm0{k1}, ymm1, ymm2"); + TEST("\x62\xf1\x74\xa9\x58\xc2", "vaddps ymm0{k1}{z}, ymm1, ymm2"); + TEST("\x62\xf1\x74\xa8\x58\xc2", "UD"); // EVEX.z = 1 + TEST("\x62\xf1\x74\x48\x58\xc2", "vaddps zmm0, zmm1, zmm2"); + TEST("\x62\xf1\x74\x49\x58\xc2", "vaddps zmm0{k1}, zmm1, zmm2"); + TEST("\x62\xf1\x74\xc9\x58\xc2", "vaddps zmm0{k1}{z}, zmm1, zmm2"); + TEST("\x62\xf1\x74\xc8\x58\xc2", "UD"); // EVEX.z = 1 + TEST("\x62\xf1\x74\x68\x58\xc2", "UD"); // EVEX.L'Lb = 110 TEST32("\x62\xf1\x74\x08\x58\x00", "vaddps xmm0, xmm1, xmmword ptr [eax]"); + TEST32("\x67\x62\xf1\x74\x08\x58\x00", "vaddps xmm0, xmm1, xmmword ptr [bx+1*si]"); + TEST64("\x62\xf1\x74\x08\x58\x00", "vaddps xmm0, xmm1, xmmword ptr [rax]"); + TEST64("\x67\x62\xf1\x74\x08\x58\x00", "vaddps xmm0, xmm1, xmmword ptr [eax]"); + TEST32("\x62\xf1\x74\x0a\x58\x00", "vaddps xmm0{k2}, xmm1, xmmword ptr [eax]"); + TEST32("\x67\x62\xf1\x74\x0a\x58\x00", "vaddps xmm0{k2}, xmm1, xmmword ptr [bx+1*si]"); + TEST64("\x62\xf1\x74\x0a\x58\x00", "vaddps xmm0{k2}, xmm1, xmmword ptr [rax]"); + TEST64("\x67\x62\xf1\x74\x0a\x58\x00", "vaddps xmm0{k2}, xmm1, xmmword ptr [eax]"); + TEST32("\x62\xf1\x74\x8a\x58\x00", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [eax]"); + TEST32("\x67\x62\xf1\x74\x8a\x58\x00", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [bx+1*si]"); + TEST64("\x62\xf1\x74\x8a\x58\x00", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [rax]"); + TEST64("\x67\x62\xf1\x74\x8a\x58\x00", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [eax]"); + TEST32("\x62\xf1\x74\x88\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\x88\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\x88\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\x88\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x18\x58\x00", "vaddps xmm0, xmm1, dword ptr [eax]{1to4}"); + TEST32("\x67\x62\xf1\x74\x18\x58\x00", "vaddps xmm0, xmm1, dword ptr [bx+1*si]{1to4}"); + TEST64("\x62\xf1\x74\x18\x58\x00", "vaddps xmm0, xmm1, dword ptr [rax]{1to4}"); + TEST64("\x67\x62\xf1\x74\x18\x58\x00", "vaddps xmm0, xmm1, dword ptr [eax]{1to4}"); + TEST32("\x62\xf1\x74\x1a\x58\x00", "vaddps xmm0{k2}, xmm1, dword ptr [eax]{1to4}"); + TEST32("\x67\x62\xf1\x74\x1a\x58\x00", "vaddps xmm0{k2}, xmm1, dword ptr [bx+1*si]{1to4}"); + TEST64("\x62\xf1\x74\x1a\x58\x00", "vaddps xmm0{k2}, xmm1, dword ptr [rax]{1to4}"); + TEST64("\x67\x62\xf1\x74\x1a\x58\x00", "vaddps xmm0{k2}, xmm1, dword ptr [eax]{1to4}"); + TEST32("\x62\xf1\x74\x9a\x58\x00", "vaddps xmm0{k2}{z}, xmm1, dword ptr [eax]{1to4}"); + TEST32("\x67\x62\xf1\x74\x9a\x58\x00", "vaddps xmm0{k2}{z}, xmm1, dword ptr [bx+1*si]{1to4}"); + TEST64("\x62\xf1\x74\x9a\x58\x00", "vaddps xmm0{k2}{z}, xmm1, dword ptr [rax]{1to4}"); + TEST64("\x67\x62\xf1\x74\x9a\x58\x00", "vaddps xmm0{k2}{z}, xmm1, dword ptr [eax]{1to4}"); + TEST32("\x62\xf1\x74\x98\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\x98\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\x98\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\x98\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x28\x58\x00", "vaddps ymm0, ymm1, ymmword ptr [eax]"); + TEST32("\x67\x62\xf1\x74\x28\x58\x00", "vaddps ymm0, ymm1, ymmword ptr [bx+1*si]"); + TEST64("\x62\xf1\x74\x28\x58\x00", "vaddps ymm0, ymm1, ymmword ptr [rax]"); + TEST64("\x67\x62\xf1\x74\x28\x58\x00", "vaddps ymm0, ymm1, ymmword ptr [eax]"); + TEST32("\x62\xf1\x74\x2a\x58\x00", "vaddps ymm0{k2}, ymm1, ymmword ptr [eax]"); + TEST32("\x67\x62\xf1\x74\x2a\x58\x00", "vaddps ymm0{k2}, ymm1, ymmword ptr [bx+1*si]"); + TEST64("\x62\xf1\x74\x2a\x58\x00", "vaddps ymm0{k2}, ymm1, ymmword ptr [rax]"); + TEST64("\x67\x62\xf1\x74\x2a\x58\x00", "vaddps ymm0{k2}, ymm1, ymmword ptr [eax]"); + TEST32("\x62\xf1\x74\xaa\x58\x00", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [eax]"); + TEST32("\x67\x62\xf1\x74\xaa\x58\x00", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [bx+1*si]"); + TEST64("\x62\xf1\x74\xaa\x58\x00", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [rax]"); + TEST64("\x67\x62\xf1\x74\xaa\x58\x00", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [eax]"); + TEST32("\x62\xf1\x74\xa8\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xa8\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xa8\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xa8\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x38\x58\x00", "vaddps ymm0, ymm1, dword ptr [eax]{1to8}"); + TEST32("\x67\x62\xf1\x74\x38\x58\x00", "vaddps ymm0, ymm1, dword ptr [bx+1*si]{1to8}"); + TEST64("\x62\xf1\x74\x38\x58\x00", "vaddps ymm0, ymm1, dword ptr [rax]{1to8}"); + TEST64("\x67\x62\xf1\x74\x38\x58\x00", "vaddps ymm0, ymm1, dword ptr [eax]{1to8}"); + TEST32("\x62\xf1\x74\x3a\x58\x00", "vaddps ymm0{k2}, ymm1, dword ptr [eax]{1to8}"); + TEST32("\x67\x62\xf1\x74\x3a\x58\x00", "vaddps ymm0{k2}, ymm1, dword ptr [bx+1*si]{1to8}"); + TEST64("\x62\xf1\x74\x3a\x58\x00", "vaddps ymm0{k2}, ymm1, dword ptr [rax]{1to8}"); + TEST64("\x67\x62\xf1\x74\x3a\x58\x00", "vaddps ymm0{k2}, ymm1, dword ptr [eax]{1to8}"); + TEST32("\x62\xf1\x74\xba\x58\x00", "vaddps ymm0{k2}{z}, ymm1, dword ptr [eax]{1to8}"); + TEST32("\x67\x62\xf1\x74\xba\x58\x00", "vaddps ymm0{k2}{z}, ymm1, dword ptr [bx+1*si]{1to8}"); + TEST64("\x62\xf1\x74\xba\x58\x00", "vaddps ymm0{k2}{z}, ymm1, dword ptr [rax]{1to8}"); + TEST64("\x67\x62\xf1\x74\xba\x58\x00", "vaddps ymm0{k2}{z}, ymm1, dword ptr [eax]{1to8}"); + TEST32("\x62\xf1\x74\xb8\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xb8\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xb8\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xb8\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x48\x58\x00", "vaddps zmm0, zmm1, zmmword ptr [eax]"); + TEST32("\x67\x62\xf1\x74\x48\x58\x00", "vaddps zmm0, zmm1, zmmword ptr [bx+1*si]"); + TEST64("\x62\xf1\x74\x48\x58\x00", "vaddps zmm0, zmm1, zmmword ptr [rax]"); + TEST64("\x67\x62\xf1\x74\x48\x58\x00", "vaddps zmm0, zmm1, zmmword ptr [eax]"); + TEST32("\x62\xf1\x74\x4a\x58\x00", "vaddps zmm0{k2}, zmm1, zmmword ptr [eax]"); + TEST32("\x67\x62\xf1\x74\x4a\x58\x00", "vaddps zmm0{k2}, zmm1, zmmword ptr [bx+1*si]"); + TEST64("\x62\xf1\x74\x4a\x58\x00", "vaddps zmm0{k2}, zmm1, zmmword ptr [rax]"); + TEST64("\x67\x62\xf1\x74\x4a\x58\x00", "vaddps zmm0{k2}, zmm1, zmmword ptr [eax]"); + TEST32("\x62\xf1\x74\xca\x58\x00", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [eax]"); + TEST32("\x67\x62\xf1\x74\xca\x58\x00", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [bx+1*si]"); + TEST64("\x62\xf1\x74\xca\x58\x00", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [rax]"); + TEST64("\x67\x62\xf1\x74\xca\x58\x00", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [eax]"); + TEST32("\x62\xf1\x74\xc8\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xc8\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xc8\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xc8\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x58\x58\x00", "vaddps zmm0, zmm1, dword ptr [eax]{1to16}"); + TEST32("\x67\x62\xf1\x74\x58\x58\x00", "vaddps zmm0, zmm1, dword ptr [bx+1*si]{1to16}"); + TEST64("\x62\xf1\x74\x58\x58\x00", "vaddps zmm0, zmm1, dword ptr [rax]{1to16}"); + TEST64("\x67\x62\xf1\x74\x58\x58\x00", "vaddps zmm0, zmm1, dword ptr [eax]{1to16}"); + TEST32("\x62\xf1\x74\x5a\x58\x00", "vaddps zmm0{k2}, zmm1, dword ptr [eax]{1to16}"); + TEST32("\x67\x62\xf1\x74\x5a\x58\x00", "vaddps zmm0{k2}, zmm1, dword ptr [bx+1*si]{1to16}"); + TEST64("\x62\xf1\x74\x5a\x58\x00", "vaddps zmm0{k2}, zmm1, dword ptr [rax]{1to16}"); + TEST64("\x67\x62\xf1\x74\x5a\x58\x00", "vaddps zmm0{k2}, zmm1, dword ptr [eax]{1to16}"); + TEST32("\x62\xf1\x74\xda\x58\x00", "vaddps zmm0{k2}{z}, zmm1, dword ptr [eax]{1to16}"); + TEST32("\x67\x62\xf1\x74\xda\x58\x00", "vaddps zmm0{k2}{z}, zmm1, dword ptr [bx+1*si]{1to16}"); + TEST64("\x62\xf1\x74\xda\x58\x00", "vaddps zmm0{k2}{z}, zmm1, dword ptr [rax]{1to16}"); + TEST64("\x67\x62\xf1\x74\xda\x58\x00", "vaddps zmm0{k2}{z}, zmm1, dword ptr [eax]{1to16}"); + TEST32("\x62\xf1\x74\xd8\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xd8\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xd8\x58\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xd8\x58\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x68\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x68\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x68\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x68\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x6a\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x6a\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x6a\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x6a\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xea\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xea\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xea\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xea\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xe8\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xe8\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xe8\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xe8\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x78\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x78\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x78\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x78\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x7a\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x7a\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x7a\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x7a\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xfa\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xfa\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xfa\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xfa\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xf8\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xf8\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xf8\x58\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xf8\x58\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x08\x58\x40\x01", "vaddps xmm0, xmm1, xmmword ptr [eax+0x10]"); + TEST32("\x67\x62\xf1\x74\x08\x58\x40\x01", "vaddps xmm0, xmm1, xmmword ptr [bx+1*si+0x10]"); + TEST64("\x62\xf1\x74\x08\x58\x40\x01", "vaddps xmm0, xmm1, xmmword ptr [rax+0x10]"); + TEST64("\x67\x62\xf1\x74\x08\x58\x40\x01", "vaddps xmm0, xmm1, xmmword ptr [eax+0x10]"); + TEST32("\x62\xf1\x74\x0a\x58\x40\x01", "vaddps xmm0{k2}, xmm1, xmmword ptr [eax+0x10]"); + TEST32("\x67\x62\xf1\x74\x0a\x58\x40\x01", "vaddps xmm0{k2}, xmm1, xmmword ptr [bx+1*si+0x10]"); + TEST64("\x62\xf1\x74\x0a\x58\x40\x01", "vaddps xmm0{k2}, xmm1, xmmword ptr [rax+0x10]"); + TEST64("\x67\x62\xf1\x74\x0a\x58\x40\x01", "vaddps xmm0{k2}, xmm1, xmmword ptr [eax+0x10]"); + TEST32("\x62\xf1\x74\x8a\x58\x40\x01", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [eax+0x10]"); + TEST32("\x67\x62\xf1\x74\x8a\x58\x40\x01", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [bx+1*si+0x10]"); + TEST64("\x62\xf1\x74\x8a\x58\x40\x01", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [rax+0x10]"); + TEST64("\x67\x62\xf1\x74\x8a\x58\x40\x01", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [eax+0x10]"); + TEST32("\x62\xf1\x74\x88\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\x88\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\x88\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\x88\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x18\x58\x40\x01", "vaddps xmm0, xmm1, dword ptr [eax+0x4]{1to4}"); + TEST32("\x67\x62\xf1\x74\x18\x58\x40\x01", "vaddps xmm0, xmm1, dword ptr [bx+1*si+0x4]{1to4}"); + TEST64("\x62\xf1\x74\x18\x58\x40\x01", "vaddps xmm0, xmm1, dword ptr [rax+0x4]{1to4}"); + TEST64("\x67\x62\xf1\x74\x18\x58\x40\x01", "vaddps xmm0, xmm1, dword ptr [eax+0x4]{1to4}"); + TEST32("\x62\xf1\x74\x1a\x58\x40\x01", "vaddps xmm0{k2}, xmm1, dword ptr [eax+0x4]{1to4}"); + TEST32("\x67\x62\xf1\x74\x1a\x58\x40\x01", "vaddps xmm0{k2}, xmm1, dword ptr [bx+1*si+0x4]{1to4}"); + TEST64("\x62\xf1\x74\x1a\x58\x40\x01", "vaddps xmm0{k2}, xmm1, dword ptr [rax+0x4]{1to4}"); + TEST64("\x67\x62\xf1\x74\x1a\x58\x40\x01", "vaddps xmm0{k2}, xmm1, dword ptr [eax+0x4]{1to4}"); + TEST32("\x62\xf1\x74\x9a\x58\x40\x01", "vaddps xmm0{k2}{z}, xmm1, dword ptr [eax+0x4]{1to4}"); + TEST32("\x67\x62\xf1\x74\x9a\x58\x40\x01", "vaddps xmm0{k2}{z}, xmm1, dword ptr [bx+1*si+0x4]{1to4}"); + TEST64("\x62\xf1\x74\x9a\x58\x40\x01", "vaddps xmm0{k2}{z}, xmm1, dword ptr [rax+0x4]{1to4}"); + TEST64("\x67\x62\xf1\x74\x9a\x58\x40\x01", "vaddps xmm0{k2}{z}, xmm1, dword ptr [eax+0x4]{1to4}"); + TEST32("\x62\xf1\x74\x98\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\x98\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\x98\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\x98\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x28\x58\x40\x01", "vaddps ymm0, ymm1, ymmword ptr [eax+0x20]"); + TEST32("\x67\x62\xf1\x74\x28\x58\x40\x01", "vaddps ymm0, ymm1, ymmword ptr [bx+1*si+0x20]"); + TEST64("\x62\xf1\x74\x28\x58\x40\x01", "vaddps ymm0, ymm1, ymmword ptr [rax+0x20]"); + TEST64("\x67\x62\xf1\x74\x28\x58\x40\x01", "vaddps ymm0, ymm1, ymmword ptr [eax+0x20]"); + TEST32("\x62\xf1\x74\x2a\x58\x40\x01", "vaddps ymm0{k2}, ymm1, ymmword ptr [eax+0x20]"); + TEST32("\x67\x62\xf1\x74\x2a\x58\x40\x01", "vaddps ymm0{k2}, ymm1, ymmword ptr [bx+1*si+0x20]"); + TEST64("\x62\xf1\x74\x2a\x58\x40\x01", "vaddps ymm0{k2}, ymm1, ymmword ptr [rax+0x20]"); + TEST64("\x67\x62\xf1\x74\x2a\x58\x40\x01", "vaddps ymm0{k2}, ymm1, ymmword ptr [eax+0x20]"); + TEST32("\x62\xf1\x74\xaa\x58\x40\x01", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [eax+0x20]"); + TEST32("\x67\x62\xf1\x74\xaa\x58\x40\x01", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [bx+1*si+0x20]"); + TEST64("\x62\xf1\x74\xaa\x58\x40\x01", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [rax+0x20]"); + TEST64("\x67\x62\xf1\x74\xaa\x58\x40\x01", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [eax+0x20]"); + TEST32("\x62\xf1\x74\xa8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xa8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xa8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xa8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x38\x58\x40\x01", "vaddps ymm0, ymm1, dword ptr [eax+0x4]{1to8}"); + TEST32("\x67\x62\xf1\x74\x38\x58\x40\x01", "vaddps ymm0, ymm1, dword ptr [bx+1*si+0x4]{1to8}"); + TEST64("\x62\xf1\x74\x38\x58\x40\x01", "vaddps ymm0, ymm1, dword ptr [rax+0x4]{1to8}"); + TEST64("\x67\x62\xf1\x74\x38\x58\x40\x01", "vaddps ymm0, ymm1, dword ptr [eax+0x4]{1to8}"); + TEST32("\x62\xf1\x74\x3a\x58\x40\x01", "vaddps ymm0{k2}, ymm1, dword ptr [eax+0x4]{1to8}"); + TEST32("\x67\x62\xf1\x74\x3a\x58\x40\x01", "vaddps ymm0{k2}, ymm1, dword ptr [bx+1*si+0x4]{1to8}"); + TEST64("\x62\xf1\x74\x3a\x58\x40\x01", "vaddps ymm0{k2}, ymm1, dword ptr [rax+0x4]{1to8}"); + TEST64("\x67\x62\xf1\x74\x3a\x58\x40\x01", "vaddps ymm0{k2}, ymm1, dword ptr [eax+0x4]{1to8}"); + TEST32("\x62\xf1\x74\xba\x58\x40\x01", "vaddps ymm0{k2}{z}, ymm1, dword ptr [eax+0x4]{1to8}"); + TEST32("\x67\x62\xf1\x74\xba\x58\x40\x01", "vaddps ymm0{k2}{z}, ymm1, dword ptr [bx+1*si+0x4]{1to8}"); + TEST64("\x62\xf1\x74\xba\x58\x40\x01", "vaddps ymm0{k2}{z}, ymm1, dword ptr [rax+0x4]{1to8}"); + TEST64("\x67\x62\xf1\x74\xba\x58\x40\x01", "vaddps ymm0{k2}{z}, ymm1, dword ptr [eax+0x4]{1to8}"); + TEST32("\x62\xf1\x74\xb8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xb8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xb8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xb8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x48\x58\x40\x01", "vaddps zmm0, zmm1, zmmword ptr [eax+0x40]"); + TEST32("\x67\x62\xf1\x74\x48\x58\x40\x01", "vaddps zmm0, zmm1, zmmword ptr [bx+1*si+0x40]"); + TEST64("\x62\xf1\x74\x48\x58\x40\x01", "vaddps zmm0, zmm1, zmmword ptr [rax+0x40]"); + TEST64("\x67\x62\xf1\x74\x48\x58\x40\x01", "vaddps zmm0, zmm1, zmmword ptr [eax+0x40]"); + TEST32("\x62\xf1\x74\x4a\x58\x40\x01", "vaddps zmm0{k2}, zmm1, zmmword ptr [eax+0x40]"); + TEST32("\x67\x62\xf1\x74\x4a\x58\x40\x01", "vaddps zmm0{k2}, zmm1, zmmword ptr [bx+1*si+0x40]"); + TEST64("\x62\xf1\x74\x4a\x58\x40\x01", "vaddps zmm0{k2}, zmm1, zmmword ptr [rax+0x40]"); + TEST64("\x67\x62\xf1\x74\x4a\x58\x40\x01", "vaddps zmm0{k2}, zmm1, zmmword ptr [eax+0x40]"); + TEST32("\x62\xf1\x74\xca\x58\x40\x01", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [eax+0x40]"); + TEST32("\x67\x62\xf1\x74\xca\x58\x40\x01", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [bx+1*si+0x40]"); + TEST64("\x62\xf1\x74\xca\x58\x40\x01", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [rax+0x40]"); + TEST64("\x67\x62\xf1\x74\xca\x58\x40\x01", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [eax+0x40]"); + TEST32("\x62\xf1\x74\xc8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xc8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xc8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xc8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x58\x58\x40\x01", "vaddps zmm0, zmm1, dword ptr [eax+0x4]{1to16}"); + TEST32("\x67\x62\xf1\x74\x58\x58\x40\x01", "vaddps zmm0, zmm1, dword ptr [bx+1*si+0x4]{1to16}"); + TEST64("\x62\xf1\x74\x58\x58\x40\x01", "vaddps zmm0, zmm1, dword ptr [rax+0x4]{1to16}"); + TEST64("\x67\x62\xf1\x74\x58\x58\x40\x01", "vaddps zmm0, zmm1, dword ptr [eax+0x4]{1to16}"); + TEST32("\x62\xf1\x74\x5a\x58\x40\x01", "vaddps zmm0{k2}, zmm1, dword ptr [eax+0x4]{1to16}"); + TEST32("\x67\x62\xf1\x74\x5a\x58\x40\x01", "vaddps zmm0{k2}, zmm1, dword ptr [bx+1*si+0x4]{1to16}"); + TEST64("\x62\xf1\x74\x5a\x58\x40\x01", "vaddps zmm0{k2}, zmm1, dword ptr [rax+0x4]{1to16}"); + TEST64("\x67\x62\xf1\x74\x5a\x58\x40\x01", "vaddps zmm0{k2}, zmm1, dword ptr [eax+0x4]{1to16}"); + TEST32("\x62\xf1\x74\xda\x58\x40\x01", "vaddps zmm0{k2}{z}, zmm1, dword ptr [eax+0x4]{1to16}"); + TEST32("\x67\x62\xf1\x74\xda\x58\x40\x01", "vaddps zmm0{k2}{z}, zmm1, dword ptr [bx+1*si+0x4]{1to16}"); + TEST64("\x62\xf1\x74\xda\x58\x40\x01", "vaddps zmm0{k2}{z}, zmm1, dword ptr [rax+0x4]{1to16}"); + TEST64("\x67\x62\xf1\x74\xda\x58\x40\x01", "vaddps zmm0{k2}{z}, zmm1, dword ptr [eax+0x4]{1to16}"); + TEST32("\x62\xf1\x74\xd8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xd8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xd8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xd8\x58\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x68\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x68\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x68\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x68\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x6a\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x6a\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x6a\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x6a\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xea\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xea\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xea\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xea\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xe8\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xe8\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xe8\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xe8\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x78\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x78\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x78\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x78\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x7a\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x7a\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x7a\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x7a\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xfa\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xfa\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xfa\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xfa\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xf8\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xf8\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xf8\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xf8\x58\x40\x01", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x08\x58\x40\xff", "vaddps xmm0, xmm1, xmmword ptr [eax-0x10]"); + TEST32("\x67\x62\xf1\x74\x08\x58\x40\xff", "vaddps xmm0, xmm1, xmmword ptr [bx+1*si-0x10]"); + TEST64("\x62\xf1\x74\x08\x58\x40\xff", "vaddps xmm0, xmm1, xmmword ptr [rax-0x10]"); + TEST64("\x67\x62\xf1\x74\x08\x58\x40\xff", "vaddps xmm0, xmm1, xmmword ptr [eax-0x10]"); + TEST32("\x62\xf1\x74\x0a\x58\x40\xff", "vaddps xmm0{k2}, xmm1, xmmword ptr [eax-0x10]"); + TEST32("\x67\x62\xf1\x74\x0a\x58\x40\xff", "vaddps xmm0{k2}, xmm1, xmmword ptr [bx+1*si-0x10]"); + TEST64("\x62\xf1\x74\x0a\x58\x40\xff", "vaddps xmm0{k2}, xmm1, xmmword ptr [rax-0x10]"); + TEST64("\x67\x62\xf1\x74\x0a\x58\x40\xff", "vaddps xmm0{k2}, xmm1, xmmword ptr [eax-0x10]"); + TEST32("\x62\xf1\x74\x8a\x58\x40\xff", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [eax-0x10]"); + TEST32("\x67\x62\xf1\x74\x8a\x58\x40\xff", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [bx+1*si-0x10]"); + TEST64("\x62\xf1\x74\x8a\x58\x40\xff", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [rax-0x10]"); + TEST64("\x67\x62\xf1\x74\x8a\x58\x40\xff", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [eax-0x10]"); + TEST32("\x62\xf1\x74\x88\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\x88\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\x88\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\x88\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x18\x58\x40\xff", "vaddps xmm0, xmm1, dword ptr [eax-0x4]{1to4}"); + TEST32("\x67\x62\xf1\x74\x18\x58\x40\xff", "vaddps xmm0, xmm1, dword ptr [bx+1*si-0x4]{1to4}"); + TEST64("\x62\xf1\x74\x18\x58\x40\xff", "vaddps xmm0, xmm1, dword ptr [rax-0x4]{1to4}"); + TEST64("\x67\x62\xf1\x74\x18\x58\x40\xff", "vaddps xmm0, xmm1, dword ptr [eax-0x4]{1to4}"); + TEST32("\x62\xf1\x74\x1a\x58\x40\xff", "vaddps xmm0{k2}, xmm1, dword ptr [eax-0x4]{1to4}"); + TEST32("\x67\x62\xf1\x74\x1a\x58\x40\xff", "vaddps xmm0{k2}, xmm1, dword ptr [bx+1*si-0x4]{1to4}"); + TEST64("\x62\xf1\x74\x1a\x58\x40\xff", "vaddps xmm0{k2}, xmm1, dword ptr [rax-0x4]{1to4}"); + TEST64("\x67\x62\xf1\x74\x1a\x58\x40\xff", "vaddps xmm0{k2}, xmm1, dword ptr [eax-0x4]{1to4}"); + TEST32("\x62\xf1\x74\x9a\x58\x40\xff", "vaddps xmm0{k2}{z}, xmm1, dword ptr [eax-0x4]{1to4}"); + TEST32("\x67\x62\xf1\x74\x9a\x58\x40\xff", "vaddps xmm0{k2}{z}, xmm1, dword ptr [bx+1*si-0x4]{1to4}"); + TEST64("\x62\xf1\x74\x9a\x58\x40\xff", "vaddps xmm0{k2}{z}, xmm1, dword ptr [rax-0x4]{1to4}"); + TEST64("\x67\x62\xf1\x74\x9a\x58\x40\xff", "vaddps xmm0{k2}{z}, xmm1, dword ptr [eax-0x4]{1to4}"); + TEST32("\x62\xf1\x74\x98\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\x98\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\x98\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\x98\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x28\x58\x40\xff", "vaddps ymm0, ymm1, ymmword ptr [eax-0x20]"); + TEST32("\x67\x62\xf1\x74\x28\x58\x40\xff", "vaddps ymm0, ymm1, ymmword ptr [bx+1*si-0x20]"); + TEST64("\x62\xf1\x74\x28\x58\x40\xff", "vaddps ymm0, ymm1, ymmword ptr [rax-0x20]"); + TEST64("\x67\x62\xf1\x74\x28\x58\x40\xff", "vaddps ymm0, ymm1, ymmword ptr [eax-0x20]"); + TEST32("\x62\xf1\x74\x2a\x58\x40\xff", "vaddps ymm0{k2}, ymm1, ymmword ptr [eax-0x20]"); + TEST32("\x67\x62\xf1\x74\x2a\x58\x40\xff", "vaddps ymm0{k2}, ymm1, ymmword ptr [bx+1*si-0x20]"); + TEST64("\x62\xf1\x74\x2a\x58\x40\xff", "vaddps ymm0{k2}, ymm1, ymmword ptr [rax-0x20]"); + TEST64("\x67\x62\xf1\x74\x2a\x58\x40\xff", "vaddps ymm0{k2}, ymm1, ymmword ptr [eax-0x20]"); + TEST32("\x62\xf1\x74\xaa\x58\x40\xff", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [eax-0x20]"); + TEST32("\x67\x62\xf1\x74\xaa\x58\x40\xff", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [bx+1*si-0x20]"); + TEST64("\x62\xf1\x74\xaa\x58\x40\xff", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [rax-0x20]"); + TEST64("\x67\x62\xf1\x74\xaa\x58\x40\xff", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [eax-0x20]"); + TEST32("\x62\xf1\x74\xa8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xa8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xa8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xa8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x38\x58\x40\xff", "vaddps ymm0, ymm1, dword ptr [eax-0x4]{1to8}"); + TEST32("\x67\x62\xf1\x74\x38\x58\x40\xff", "vaddps ymm0, ymm1, dword ptr [bx+1*si-0x4]{1to8}"); + TEST64("\x62\xf1\x74\x38\x58\x40\xff", "vaddps ymm0, ymm1, dword ptr [rax-0x4]{1to8}"); + TEST64("\x67\x62\xf1\x74\x38\x58\x40\xff", "vaddps ymm0, ymm1, dword ptr [eax-0x4]{1to8}"); + TEST32("\x62\xf1\x74\x3a\x58\x40\xff", "vaddps ymm0{k2}, ymm1, dword ptr [eax-0x4]{1to8}"); + TEST32("\x67\x62\xf1\x74\x3a\x58\x40\xff", "vaddps ymm0{k2}, ymm1, dword ptr [bx+1*si-0x4]{1to8}"); + TEST64("\x62\xf1\x74\x3a\x58\x40\xff", "vaddps ymm0{k2}, ymm1, dword ptr [rax-0x4]{1to8}"); + TEST64("\x67\x62\xf1\x74\x3a\x58\x40\xff", "vaddps ymm0{k2}, ymm1, dword ptr [eax-0x4]{1to8}"); + TEST32("\x62\xf1\x74\xba\x58\x40\xff", "vaddps ymm0{k2}{z}, ymm1, dword ptr [eax-0x4]{1to8}"); + TEST32("\x67\x62\xf1\x74\xba\x58\x40\xff", "vaddps ymm0{k2}{z}, ymm1, dword ptr [bx+1*si-0x4]{1to8}"); + TEST64("\x62\xf1\x74\xba\x58\x40\xff", "vaddps ymm0{k2}{z}, ymm1, dword ptr [rax-0x4]{1to8}"); + TEST64("\x67\x62\xf1\x74\xba\x58\x40\xff", "vaddps ymm0{k2}{z}, ymm1, dword ptr [eax-0x4]{1to8}"); + TEST32("\x62\xf1\x74\xb8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xb8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xb8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xb8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x48\x58\x40\xff", "vaddps zmm0, zmm1, zmmword ptr [eax-0x40]"); + TEST32("\x67\x62\xf1\x74\x48\x58\x40\xff", "vaddps zmm0, zmm1, zmmword ptr [bx+1*si-0x40]"); + TEST64("\x62\xf1\x74\x48\x58\x40\xff", "vaddps zmm0, zmm1, zmmword ptr [rax-0x40]"); + TEST64("\x67\x62\xf1\x74\x48\x58\x40\xff", "vaddps zmm0, zmm1, zmmword ptr [eax-0x40]"); + TEST32("\x62\xf1\x74\x4a\x58\x40\xff", "vaddps zmm0{k2}, zmm1, zmmword ptr [eax-0x40]"); + TEST32("\x67\x62\xf1\x74\x4a\x58\x40\xff", "vaddps zmm0{k2}, zmm1, zmmword ptr [bx+1*si-0x40]"); + TEST64("\x62\xf1\x74\x4a\x58\x40\xff", "vaddps zmm0{k2}, zmm1, zmmword ptr [rax-0x40]"); + TEST64("\x67\x62\xf1\x74\x4a\x58\x40\xff", "vaddps zmm0{k2}, zmm1, zmmword ptr [eax-0x40]"); + TEST32("\x62\xf1\x74\xca\x58\x40\xff", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [eax-0x40]"); + TEST32("\x67\x62\xf1\x74\xca\x58\x40\xff", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [bx+1*si-0x40]"); + TEST64("\x62\xf1\x74\xca\x58\x40\xff", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [rax-0x40]"); + TEST64("\x67\x62\xf1\x74\xca\x58\x40\xff", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [eax-0x40]"); + TEST32("\x62\xf1\x74\xc8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xc8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xc8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xc8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x58\x58\x40\xff", "vaddps zmm0, zmm1, dword ptr [eax-0x4]{1to16}"); + TEST32("\x67\x62\xf1\x74\x58\x58\x40\xff", "vaddps zmm0, zmm1, dword ptr [bx+1*si-0x4]{1to16}"); + TEST64("\x62\xf1\x74\x58\x58\x40\xff", "vaddps zmm0, zmm1, dword ptr [rax-0x4]{1to16}"); + TEST64("\x67\x62\xf1\x74\x58\x58\x40\xff", "vaddps zmm0, zmm1, dword ptr [eax-0x4]{1to16}"); + TEST32("\x62\xf1\x74\x5a\x58\x40\xff", "vaddps zmm0{k2}, zmm1, dword ptr [eax-0x4]{1to16}"); + TEST32("\x67\x62\xf1\x74\x5a\x58\x40\xff", "vaddps zmm0{k2}, zmm1, dword ptr [bx+1*si-0x4]{1to16}"); + TEST64("\x62\xf1\x74\x5a\x58\x40\xff", "vaddps zmm0{k2}, zmm1, dword ptr [rax-0x4]{1to16}"); + TEST64("\x67\x62\xf1\x74\x5a\x58\x40\xff", "vaddps zmm0{k2}, zmm1, dword ptr [eax-0x4]{1to16}"); + TEST32("\x62\xf1\x74\xda\x58\x40\xff", "vaddps zmm0{k2}{z}, zmm1, dword ptr [eax-0x4]{1to16}"); + TEST32("\x67\x62\xf1\x74\xda\x58\x40\xff", "vaddps zmm0{k2}{z}, zmm1, dword ptr [bx+1*si-0x4]{1to16}"); + TEST64("\x62\xf1\x74\xda\x58\x40\xff", "vaddps zmm0{k2}{z}, zmm1, dword ptr [rax-0x4]{1to16}"); + TEST64("\x67\x62\xf1\x74\xda\x58\x40\xff", "vaddps zmm0{k2}{z}, zmm1, dword ptr [eax-0x4]{1to16}"); + TEST32("\x62\xf1\x74\xd8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xd8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xd8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xd8\x58\x40\xff", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x68\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x68\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x68\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x68\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x6a\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x6a\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x6a\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x6a\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xea\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xea\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xea\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xea\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xe8\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xe8\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xe8\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xe8\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x78\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x78\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x78\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x78\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x7a\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x7a\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x7a\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x7a\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xfa\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xfa\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xfa\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xfa\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xf8\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xf8\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xf8\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xf8\x58\x40\xff", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x08\x58\x80\x01\x00\x00\x00", "vaddps xmm0, xmm1, xmmword ptr [eax+0x1]"); + TEST32("\x67\x62\xf1\x74\x08\x58\x80\x01\x00", "vaddps xmm0, xmm1, xmmword ptr [bx+1*si+0x1]"); + TEST64("\x62\xf1\x74\x08\x58\x80\x01\x00\x00\x00", "vaddps xmm0, xmm1, xmmword ptr [rax+0x1]"); + TEST64("\x67\x62\xf1\x74\x08\x58\x80\x01\x00\x00\x00", "vaddps xmm0, xmm1, xmmword ptr [eax+0x1]"); + TEST32("\x62\xf1\x74\x0a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}, xmm1, xmmword ptr [eax+0x1]"); + TEST32("\x67\x62\xf1\x74\x0a\x58\x80\x01\x00", "vaddps xmm0{k2}, xmm1, xmmword ptr [bx+1*si+0x1]"); + TEST64("\x62\xf1\x74\x0a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}, xmm1, xmmword ptr [rax+0x1]"); + TEST64("\x67\x62\xf1\x74\x0a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}, xmm1, xmmword ptr [eax+0x1]"); + TEST32("\x62\xf1\x74\x8a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [eax+0x1]"); + TEST32("\x67\x62\xf1\x74\x8a\x58\x80\x01\x00", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [bx+1*si+0x1]"); + TEST64("\x62\xf1\x74\x8a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [rax+0x1]"); + TEST64("\x67\x62\xf1\x74\x8a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}{z}, xmm1, xmmword ptr [eax+0x1]"); + TEST32("\x62\xf1\x74\x88\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\x88\x58\x80\x01\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\x88\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\x88\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x18\x58\x80\x01\x00\x00\x00", "vaddps xmm0, xmm1, dword ptr [eax+0x1]{1to4}"); + TEST32("\x67\x62\xf1\x74\x18\x58\x80\x01\x00", "vaddps xmm0, xmm1, dword ptr [bx+1*si+0x1]{1to4}"); + TEST64("\x62\xf1\x74\x18\x58\x80\x01\x00\x00\x00", "vaddps xmm0, xmm1, dword ptr [rax+0x1]{1to4}"); + TEST64("\x67\x62\xf1\x74\x18\x58\x80\x01\x00\x00\x00", "vaddps xmm0, xmm1, dword ptr [eax+0x1]{1to4}"); + TEST32("\x62\xf1\x74\x1a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}, xmm1, dword ptr [eax+0x1]{1to4}"); + TEST32("\x67\x62\xf1\x74\x1a\x58\x80\x01\x00", "vaddps xmm0{k2}, xmm1, dword ptr [bx+1*si+0x1]{1to4}"); + TEST64("\x62\xf1\x74\x1a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}, xmm1, dword ptr [rax+0x1]{1to4}"); + TEST64("\x67\x62\xf1\x74\x1a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}, xmm1, dword ptr [eax+0x1]{1to4}"); + TEST32("\x62\xf1\x74\x9a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}{z}, xmm1, dword ptr [eax+0x1]{1to4}"); + TEST32("\x67\x62\xf1\x74\x9a\x58\x80\x01\x00", "vaddps xmm0{k2}{z}, xmm1, dword ptr [bx+1*si+0x1]{1to4}"); + TEST64("\x62\xf1\x74\x9a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}{z}, xmm1, dword ptr [rax+0x1]{1to4}"); + TEST64("\x67\x62\xf1\x74\x9a\x58\x80\x01\x00\x00\x00", "vaddps xmm0{k2}{z}, xmm1, dword ptr [eax+0x1]{1to4}"); + TEST32("\x62\xf1\x74\x98\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\x98\x58\x80\x01\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\x98\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\x98\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x28\x58\x80\x01\x00\x00\x00", "vaddps ymm0, ymm1, ymmword ptr [eax+0x1]"); + TEST32("\x67\x62\xf1\x74\x28\x58\x80\x01\x00", "vaddps ymm0, ymm1, ymmword ptr [bx+1*si+0x1]"); + TEST64("\x62\xf1\x74\x28\x58\x80\x01\x00\x00\x00", "vaddps ymm0, ymm1, ymmword ptr [rax+0x1]"); + TEST64("\x67\x62\xf1\x74\x28\x58\x80\x01\x00\x00\x00", "vaddps ymm0, ymm1, ymmword ptr [eax+0x1]"); + TEST32("\x62\xf1\x74\x2a\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}, ymm1, ymmword ptr [eax+0x1]"); + TEST32("\x67\x62\xf1\x74\x2a\x58\x80\x01\x00", "vaddps ymm0{k2}, ymm1, ymmword ptr [bx+1*si+0x1]"); + TEST64("\x62\xf1\x74\x2a\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}, ymm1, ymmword ptr [rax+0x1]"); + TEST64("\x67\x62\xf1\x74\x2a\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}, ymm1, ymmword ptr [eax+0x1]"); + TEST32("\x62\xf1\x74\xaa\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [eax+0x1]"); + TEST32("\x67\x62\xf1\x74\xaa\x58\x80\x01\x00", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [bx+1*si+0x1]"); + TEST64("\x62\xf1\x74\xaa\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [rax+0x1]"); + TEST64("\x67\x62\xf1\x74\xaa\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}{z}, ymm1, ymmword ptr [eax+0x1]"); + TEST32("\x62\xf1\x74\xa8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xa8\x58\x80\x01\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xa8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xa8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x38\x58\x80\x01\x00\x00\x00", "vaddps ymm0, ymm1, dword ptr [eax+0x1]{1to8}"); + TEST32("\x67\x62\xf1\x74\x38\x58\x80\x01\x00", "vaddps ymm0, ymm1, dword ptr [bx+1*si+0x1]{1to8}"); + TEST64("\x62\xf1\x74\x38\x58\x80\x01\x00\x00\x00", "vaddps ymm0, ymm1, dword ptr [rax+0x1]{1to8}"); + TEST64("\x67\x62\xf1\x74\x38\x58\x80\x01\x00\x00\x00", "vaddps ymm0, ymm1, dword ptr [eax+0x1]{1to8}"); + TEST32("\x62\xf1\x74\x3a\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}, ymm1, dword ptr [eax+0x1]{1to8}"); + TEST32("\x67\x62\xf1\x74\x3a\x58\x80\x01\x00", "vaddps ymm0{k2}, ymm1, dword ptr [bx+1*si+0x1]{1to8}"); + TEST64("\x62\xf1\x74\x3a\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}, ymm1, dword ptr [rax+0x1]{1to8}"); + TEST64("\x67\x62\xf1\x74\x3a\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}, ymm1, dword ptr [eax+0x1]{1to8}"); + TEST32("\x62\xf1\x74\xba\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}{z}, ymm1, dword ptr [eax+0x1]{1to8}"); + TEST32("\x67\x62\xf1\x74\xba\x58\x80\x01\x00", "vaddps ymm0{k2}{z}, ymm1, dword ptr [bx+1*si+0x1]{1to8}"); + TEST64("\x62\xf1\x74\xba\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}{z}, ymm1, dword ptr [rax+0x1]{1to8}"); + TEST64("\x67\x62\xf1\x74\xba\x58\x80\x01\x00\x00\x00", "vaddps ymm0{k2}{z}, ymm1, dword ptr [eax+0x1]{1to8}"); + TEST32("\x62\xf1\x74\xb8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xb8\x58\x80\x01\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xb8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xb8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x48\x58\x80\x01\x00\x00\x00", "vaddps zmm0, zmm1, zmmword ptr [eax+0x1]"); + TEST32("\x67\x62\xf1\x74\x48\x58\x80\x01\x00", "vaddps zmm0, zmm1, zmmword ptr [bx+1*si+0x1]"); + TEST64("\x62\xf1\x74\x48\x58\x80\x01\x00\x00\x00", "vaddps zmm0, zmm1, zmmword ptr [rax+0x1]"); + TEST64("\x67\x62\xf1\x74\x48\x58\x80\x01\x00\x00\x00", "vaddps zmm0, zmm1, zmmword ptr [eax+0x1]"); + TEST32("\x62\xf1\x74\x4a\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}, zmm1, zmmword ptr [eax+0x1]"); + TEST32("\x67\x62\xf1\x74\x4a\x58\x80\x01\x00", "vaddps zmm0{k2}, zmm1, zmmword ptr [bx+1*si+0x1]"); + TEST64("\x62\xf1\x74\x4a\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}, zmm1, zmmword ptr [rax+0x1]"); + TEST64("\x67\x62\xf1\x74\x4a\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}, zmm1, zmmword ptr [eax+0x1]"); + TEST32("\x62\xf1\x74\xca\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [eax+0x1]"); + TEST32("\x67\x62\xf1\x74\xca\x58\x80\x01\x00", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [bx+1*si+0x1]"); + TEST64("\x62\xf1\x74\xca\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [rax+0x1]"); + TEST64("\x67\x62\xf1\x74\xca\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}{z}, zmm1, zmmword ptr [eax+0x1]"); + TEST32("\x62\xf1\x74\xc8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xc8\x58\x80\x01\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xc8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xc8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x58\x58\x80\x01\x00\x00\x00", "vaddps zmm0, zmm1, dword ptr [eax+0x1]{1to16}"); + TEST32("\x67\x62\xf1\x74\x58\x58\x80\x01\x00", "vaddps zmm0, zmm1, dword ptr [bx+1*si+0x1]{1to16}"); + TEST64("\x62\xf1\x74\x58\x58\x80\x01\x00\x00\x00", "vaddps zmm0, zmm1, dword ptr [rax+0x1]{1to16}"); + TEST64("\x67\x62\xf1\x74\x58\x58\x80\x01\x00\x00\x00", "vaddps zmm0, zmm1, dword ptr [eax+0x1]{1to16}"); + TEST32("\x62\xf1\x74\x5a\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}, zmm1, dword ptr [eax+0x1]{1to16}"); + TEST32("\x67\x62\xf1\x74\x5a\x58\x80\x01\x00", "vaddps zmm0{k2}, zmm1, dword ptr [bx+1*si+0x1]{1to16}"); + TEST64("\x62\xf1\x74\x5a\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}, zmm1, dword ptr [rax+0x1]{1to16}"); + TEST64("\x67\x62\xf1\x74\x5a\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}, zmm1, dword ptr [eax+0x1]{1to16}"); + TEST32("\x62\xf1\x74\xda\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}{z}, zmm1, dword ptr [eax+0x1]{1to16}"); + TEST32("\x67\x62\xf1\x74\xda\x58\x80\x01\x00", "vaddps zmm0{k2}{z}, zmm1, dword ptr [bx+1*si+0x1]{1to16}"); + TEST64("\x62\xf1\x74\xda\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}{z}, zmm1, dword ptr [rax+0x1]{1to16}"); + TEST64("\x67\x62\xf1\x74\xda\x58\x80\x01\x00\x00\x00", "vaddps zmm0{k2}{z}, zmm1, dword ptr [eax+0x1]{1to16}"); + TEST32("\x62\xf1\x74\xd8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf1\x74\xd8\x58\x80\x01\x00", "UD"); // EVEX.z = 1 + TEST64("\x62\xf1\x74\xd8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf1\x74\xd8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.z = 1 + TEST32("\x62\xf1\x74\x68\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x68\x58\x80\x01\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x68\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x68\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x6a\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x6a\x58\x80\x01\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x6a\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x6a\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xea\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xea\x58\x80\x01\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xea\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xea\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xe8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xe8\x58\x80\x01\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xe8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xe8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x78\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x78\x58\x80\x01\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x78\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x78\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\x7a\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\x7a\x58\x80\x01\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\x7a\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\x7a\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xfa\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xfa\x58\x80\x01\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xfa\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xfa\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x62\xf1\x74\xf8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST32("\x67\x62\xf1\x74\xf8\x58\x80\x01\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x62\xf1\x74\xf8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + TEST64("\x67\x62\xf1\x74\xf8\x58\x80\x01\x00\x00\x00", "UD"); // EVEX.L'L = 11 + + // Test register extensions encoded in EVEX prefixs + TEST3264("\x62\xf1\x74\x08\x58\xc2", "vaddps xmm0, xmm1, xmm2", "vaddps xmm0, xmm1, xmm2"); + TEST3264("\x62\xd1\x74\x08\x58\xc2", "vaddps xmm0, xmm1, xmm2", "vaddps xmm0, xmm1, xmm10"); + TEST64("\x62\xb1\x74\x08\x58\xc2", "vaddps xmm0, xmm1, xmm18"); + TEST64("\x62\x91\x74\x08\x58\xc2", "vaddps xmm0, xmm1, xmm26"); + TEST3264("\x62\xf1\x34\x08\x58\xc2", "vaddps xmm0, xmm1, xmm2", "vaddps xmm0, xmm9, xmm2"); + TEST3264("\x62\xd1\x34\x08\x58\xc2", "vaddps xmm0, xmm1, xmm2", "vaddps xmm0, xmm9, xmm10"); + TEST64("\x62\xb1\x34\x08\x58\xc2", "vaddps xmm0, xmm9, xmm18"); + TEST64("\x62\x91\x34\x08\x58\xc2", "vaddps xmm0, xmm9, xmm26"); + TEST3264("\x62\xf1\x74\x00\x58\xc2", "UD", "vaddps xmm0, xmm17, xmm2"); // EVEX.V' = 0 + TEST3264("\x62\xd1\x74\x00\x58\xc2", "UD", "vaddps xmm0, xmm17, xmm10"); // EVEX.V' = 0 + TEST64("\x62\xb1\x74\x00\x58\xc2", "vaddps xmm0, xmm17, xmm18"); + TEST64("\x62\x91\x74\x00\x58\xc2", "vaddps xmm0, xmm17, xmm26"); + TEST3264("\x62\xf1\x34\x00\x58\xc2", "UD", "vaddps xmm0, xmm25, xmm2"); // EVEX.V' = 0 + TEST3264("\x62\xd1\x34\x00\x58\xc2", "UD", "vaddps xmm0, xmm25, xmm10"); // EVEX.V' = 0 + TEST64("\x62\xb1\x34\x00\x58\xc2", "vaddps xmm0, xmm25, xmm18"); + TEST64("\x62\x91\x34\x00\x58\xc2", "vaddps xmm0, xmm25, xmm26"); + TEST64("\x62\x71\x74\x08\x58\xc2", "vaddps xmm8, xmm1, xmm2"); + TEST64("\x62\x51\x74\x08\x58\xc2", "vaddps xmm8, xmm1, xmm10"); + TEST64("\x62\x31\x74\x08\x58\xc2", "vaddps xmm8, xmm1, xmm18"); + TEST64("\x62\x11\x74\x08\x58\xc2", "vaddps xmm8, xmm1, xmm26"); + TEST64("\x62\x71\x34\x08\x58\xc2", "vaddps xmm8, xmm9, xmm2"); + TEST64("\x62\x51\x34\x08\x58\xc2", "vaddps xmm8, xmm9, xmm10"); + TEST64("\x62\x31\x34\x08\x58\xc2", "vaddps xmm8, xmm9, xmm18"); + TEST64("\x62\x11\x34\x08\x58\xc2", "vaddps xmm8, xmm9, xmm26"); + TEST64("\x62\x71\x74\x00\x58\xc2", "vaddps xmm8, xmm17, xmm2"); + TEST64("\x62\x51\x74\x00\x58\xc2", "vaddps xmm8, xmm17, xmm10"); + TEST64("\x62\x31\x74\x00\x58\xc2", "vaddps xmm8, xmm17, xmm18"); + TEST64("\x62\x11\x74\x00\x58\xc2", "vaddps xmm8, xmm17, xmm26"); + TEST64("\x62\x71\x34\x00\x58\xc2", "vaddps xmm8, xmm25, xmm2"); + TEST64("\x62\x51\x34\x00\x58\xc2", "vaddps xmm8, xmm25, xmm10"); + TEST64("\x62\x31\x34\x00\x58\xc2", "vaddps xmm8, xmm25, xmm18"); + TEST64("\x62\x11\x34\x00\x58\xc2", "vaddps xmm8, xmm25, xmm26"); + TEST3264("\x62\xe1\x74\x08\x58\xc2", "vaddps xmm0, xmm1, xmm2", "vaddps xmm16, xmm1, xmm2"); + TEST3264("\x62\xc1\x74\x08\x58\xc2", "vaddps xmm0, xmm1, xmm2", "vaddps xmm16, xmm1, xmm10"); + TEST64("\x62\xa1\x74\x08\x58\xc2", "vaddps xmm16, xmm1, xmm18"); + TEST64("\x62\x81\x74\x08\x58\xc2", "vaddps xmm16, xmm1, xmm26"); + TEST3264("\x62\xe1\x34\x08\x58\xc2", "vaddps xmm0, xmm1, xmm2", "vaddps xmm16, xmm9, xmm2"); + TEST3264("\x62\xc1\x34\x08\x58\xc2", "vaddps xmm0, xmm1, xmm2", "vaddps xmm16, xmm9, xmm10"); + TEST64("\x62\xa1\x34\x08\x58\xc2", "vaddps xmm16, xmm9, xmm18"); + TEST64("\x62\x81\x34\x08\x58\xc2", "vaddps xmm16, xmm9, xmm26"); + TEST3264("\x62\xe1\x74\x00\x58\xc2", "UD", "vaddps xmm16, xmm17, xmm2"); // EVEX.V' = 0 + TEST3264("\x62\xc1\x74\x00\x58\xc2", "UD", "vaddps xmm16, xmm17, xmm10"); // EVEX.V' = 0 + TEST64("\x62\xa1\x74\x00\x58\xc2", "vaddps xmm16, xmm17, xmm18"); + TEST64("\x62\x81\x74\x00\x58\xc2", "vaddps xmm16, xmm17, xmm26"); + TEST3264("\x62\xe1\x34\x00\x58\xc2", "UD", "vaddps xmm16, xmm25, xmm2"); // EVEX.V' = 0 + TEST3264("\x62\xc1\x34\x00\x58\xc2", "UD", "vaddps xmm16, xmm25, xmm10"); // EVEX.V' = 0 + TEST64("\x62\xa1\x34\x00\x58\xc2", "vaddps xmm16, xmm25, xmm18"); + TEST64("\x62\x81\x34\x00\x58\xc2", "vaddps xmm16, xmm25, xmm26"); + TEST64("\x62\x61\x74\x08\x58\xc2", "vaddps xmm24, xmm1, xmm2"); + TEST64("\x62\x41\x74\x08\x58\xc2", "vaddps xmm24, xmm1, xmm10"); + TEST64("\x62\x21\x74\x08\x58\xc2", "vaddps xmm24, xmm1, xmm18"); + TEST64("\x62\x01\x74\x08\x58\xc2", "vaddps xmm24, xmm1, xmm26"); + TEST64("\x62\x61\x34\x08\x58\xc2", "vaddps xmm24, xmm9, xmm2"); + TEST64("\x62\x41\x34\x08\x58\xc2", "vaddps xmm24, xmm9, xmm10"); + TEST64("\x62\x21\x34\x08\x58\xc2", "vaddps xmm24, xmm9, xmm18"); + TEST64("\x62\x01\x34\x08\x58\xc2", "vaddps xmm24, xmm9, xmm26"); + TEST64("\x62\x61\x74\x00\x58\xc2", "vaddps xmm24, xmm17, xmm2"); + TEST64("\x62\x41\x74\x00\x58\xc2", "vaddps xmm24, xmm17, xmm10"); + TEST64("\x62\x21\x74\x00\x58\xc2", "vaddps xmm24, xmm17, xmm18"); + TEST64("\x62\x01\x74\x00\x58\xc2", "vaddps xmm24, xmm17, xmm26"); + TEST64("\x62\x61\x34\x00\x58\xc2", "vaddps xmm24, xmm25, xmm2"); + TEST64("\x62\x41\x34\x00\x58\xc2", "vaddps xmm24, xmm25, xmm10"); + TEST64("\x62\x21\x34\x00\x58\xc2", "vaddps xmm24, xmm25, xmm18"); + TEST64("\x62\x01\x34\x00\x58\xc2", "vaddps xmm24, xmm25, xmm26"); + + // VMOVDDUP has special tuple size for L0. + TEST("\x62\xf1\xff\x08\x12\x48\x01", "vmovddup xmm1, qword ptr [@ax+0x8]"); + TEST("\x62\xf1\xff\x08\x12\xc8", "vmovddup xmm1, xmm0"); + TEST("\x62\xf1\xff\x28\x12\x48\x01", "vmovddup ymm1, ymmword ptr [@ax+0x20]"); + TEST("\x62\xf1\xff\x28\x12\xc8", "vmovddup ymm1, ymm0"); + TEST("\x62\xf1\xff\x48\x12\x48\x01", "vmovddup zmm1, zmmword ptr [@ax+0x40]"); + TEST("\x62\xf1\xff\x48\x12\xc8", "vmovddup zmm1, zmm0"); + + // Check EVEX.L'L constraints + TEST("\x62\xf2\x7d\x08\x18\x48\x01", "vbroadcastss xmm1, dword ptr [@ax+0x4]"); + TEST("\x62\xf2\x7d\x08\x18\xc8", "vbroadcastss xmm1, xmm0"); + TEST("\x62\xf2\x7d\x28\x18\x48\x01", "vbroadcastss ymm1, dword ptr [@ax+0x4]"); + TEST("\x62\xf2\x7d\x28\x18\xc8", "vbroadcastss ymm1, xmm0"); + TEST("\x62\xf2\x7d\x48\x18\x48\x01", "vbroadcastss zmm1, dword ptr [@ax+0x4]"); + TEST("\x62\xf2\x7d\x48\x18\xc8", "vbroadcastss zmm1, xmm0"); + TEST("\x62\xf2\x7d\x68\x18\x48\x01", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\x7d\x68\x18\xc8", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\x7d\x08\x19\x48\x01", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\x7d\x08\x19\xc8", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\x7d\x28\x19\x48\x01", "vbroadcastf32x2 ymm1, qword ptr [@ax+0x8]"); + TEST("\x62\xf2\x7d\x28\x19\xc8", "vbroadcastf32x2 ymm1, xmm0"); + TEST("\x62\xf2\x7d\x48\x19\x48\x01", "vbroadcastf32x2 zmm1, qword ptr [@ax+0x8]"); + TEST("\x62\xf2\x7d\x48\x19\xc8", "vbroadcastf32x2 zmm1, xmm0"); + TEST("\x62\xf2\x7d\x68\x19\x48\x01", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\x7d\x68\x19\xc8", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\xfd\x08\x19\x48\x01", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\xfd\x08\x19\xc8", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\xfd\x28\x19\x48\x01", "vbroadcastsd ymm1, qword ptr [@ax+0x8]"); + TEST("\x62\xf2\xfd\x28\x19\xc8", "vbroadcastsd ymm1, xmm0"); + TEST("\x62\xf2\xfd\x48\x19\x48\x01", "vbroadcastsd zmm1, qword ptr [@ax+0x8]"); + TEST("\x62\xf2\xfd\x48\x19\xc8", "vbroadcastsd zmm1, xmm0"); + TEST("\x62\xf2\xfd\x68\x19\x48\x01", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\xfd\x68\x19\xc8", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\x7d\x08\x1a\x48\x01", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\x7d\x08\x1a\xc8", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\x7d\x28\x1a\x48\x01", "vbroadcastf32x4 ymm1, xmmword ptr [@ax+0x10]"); + TEST("\x62\xf2\x7d\x28\x1a\xc8", "UD"); // must have a memory operand + TEST("\x62\xf2\x7d\x48\x1a\x48\x01", "vbroadcastf32x4 zmm1, xmmword ptr [@ax+0x10]"); + TEST("\x62\xf2\x7d\x48\x1a\xc8", "UD"); // must have a memory operand + TEST("\x62\xf2\x7d\x68\x1a\x48\x01", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\x7d\x68\x1a\xc8", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\xfd\x08\x1a\x48\x01", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\xfd\x08\x1a\xc8", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\xfd\x28\x1a\x48\x01", "vbroadcastf64x2 ymm1, xmmword ptr [@ax+0x10]"); + TEST("\x62\xf2\xfd\x28\x1a\xc8", "UD"); // must have a memory operand + TEST("\x62\xf2\xfd\x48\x1a\x48\x01", "vbroadcastf64x2 zmm1, xmmword ptr [@ax+0x10]"); + TEST("\x62\xf2\xfd\x48\x1a\xc8", "UD"); // must have a memory operand + TEST("\x62\xf2\xfd\x68\x1a\x48\x01", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\xfd\x68\x1a\xc8", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\x7d\x08\x1b\x48\x01", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\x7d\x08\x1b\xc8", "UD"); // EVEX.L'L = 0 + TEST3264("\x62\xf2\x7d\x28\x1b\x48\x01", "UD", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf2\x7d\x28\x1b\xc8", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf2\x7d\x48\x1b\x48\x01", "vbroadcastf32x8 zmm1, ymmword ptr [@ax+0x20]"); + TEST("\x62\xf2\x7d\x48\x1b\xc8", "UD"); // must have a memory operand + TEST("\x62\xf2\x7d\x68\x1b\x48\x01", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\x7d\x68\x1b\xc8", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\xfd\x08\x1b\x48\x01", "UD"); // EVEX.L'L = 0 + TEST("\x62\xf2\xfd\x08\x1b\xc8", "UD"); // EVEX.L'L = 0 + TEST3264("\x62\xf2\xfd\x28\x1b\x48\x01", "UD", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf2\xfd\x28\x1b\xc8", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf2\xfd\x48\x1b\x48\x01", "vbroadcastf64x4 zmm1, ymmword ptr [@ax+0x20]"); + TEST("\x62\xf2\xfd\x48\x1b\xc8", "UD"); // must have a memory operand + TEST("\x62\xf2\xfd\x68\x1b\x48\x01", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\xfd\x68\x1b\xc8", "UD"); // EVEX.L'L = 3 + + // EVEX PEXTR/PINSR/MOV_G2X/MOV_X2G/PBROADCAST ignore EVEX.W in 32-bit mode + // and have different mnemonics on due to this distinction. + TEST("\x62\xf3\x7d\x08\x14\x00\x01", "vpextrb byte ptr [@ax], xmm0, 0x1"); + TEST("\x62\xf3\x7d\x08\x14\x40\x01\x01", "vpextrb byte ptr [@ax+0x1], xmm0, 0x1"); + TEST("\x62\xf3\x7d\x08\x14\xc0\x01", "vpextrb eax, xmm0, 0x1"); + TEST("\x62\xf3\x7d\x18\x14\xc0\x01", "UD"); // EVEX.b != 0 + TEST("\x62\xf3\x7d\x28\x14\xc0\x01", "UD"); // EVEX.L'L != 0 + TEST("\x62\xf3\x7d\x48\x14\xc0\x01", "UD"); // EVEX.L'L != 0 + TEST("\x62\xf3\x7d\x88\x14\xc0\x01", "UD"); // EVEX.z != 0 + TEST("\x62\xf3\x7d\x09\x14\xc0\x01", "UD"); // EVEX.aaa != 0 + TEST("\x62\xf3\x7d\x08\x15\x00\x01", "vpextrw word ptr [@ax], xmm0, 0x1"); + TEST("\x62\xf3\x7d\x08\x15\x40\x01\x01", "vpextrw word ptr [@ax+0x2], xmm0, 0x1"); + TEST("\x62\xf3\x7d\x08\x15\xc0\x01", "vpextrw eax, xmm0, 0x1"); + TEST("\x62\xf1\x7d\x08\xc5\xc0\x01", "vpextrw eax, xmm0, 0x1"); + TEST("\x62\xf1\x7d\x08\xc5\x00\x01", "UD"); // must have register operand + TEST("\x62\xf3\x7d\x08\x16\x00\x01", "vpextrd dword ptr [@ax], xmm0, 0x1"); + TEST("\x62\xf3\x7d\x08\x16\x40\x01\x01", "vpextrd dword ptr [@ax+0x4], xmm0, 0x1"); + TEST("\x62\xf3\x7d\x08\x16\xc0\x01", "vpextrd eax, xmm0, 0x1"); + TEST3264("\x62\xf3\xfd\x08\x16\x00\x01", "vpextrd dword ptr [eax], xmm0, 0x1", "vpextrq qword ptr [rax], xmm0, 0x1"); // EVEX.W ignored + TEST3264("\x62\xf3\xfd\x08\x16\x40\x01\x01", "vpextrd dword ptr [eax+0x4], xmm0, 0x1", "vpextrq qword ptr [rax+0x8], xmm0, 0x1"); // EVEX.W ignored + TEST3264("\x62\xf3\xfd\x08\x16\xc0\x01", "vpextrd eax, xmm0, 0x1", "vpextrq rax, xmm0, 0x1"); // EVEX.W ignored + TEST("\x62\xf3\x75\x08\x20\x00\x01", "vpinsrb xmm0, xmm1, byte ptr [@ax], 0x1"); + TEST("\x62\xf3\x75\x08\x20\x40\x01\x01", "vpinsrb xmm0, xmm1, byte ptr [@ax+0x1], 0x1"); + TEST("\x62\xf3\x75\x08\x20\xc0\x01", "vpinsrb xmm0, xmm1, al, 0x1"); + TEST("\x62\xf1\x75\x08\xc4\x00\x01", "vpinsrw xmm0, xmm1, word ptr [@ax], 0x1"); + TEST("\x62\xf1\x75\x08\xc4\x40\x01\x01", "vpinsrw xmm0, xmm1, word ptr [@ax+0x2], 0x1"); + TEST("\x62\xf1\x75\x08\xc4\xc0\x01", "vpinsrw xmm0, xmm1, ax, 0x1"); + TEST("\x62\xf3\x75\x08\x22\x00\x01", "vpinsrd xmm0, xmm1, dword ptr [@ax], 0x1"); + TEST("\x62\xf3\x75\x08\x22\x40\x01\x01", "vpinsrd xmm0, xmm1, dword ptr [@ax+0x4], 0x1"); + TEST("\x62\xf3\x75\x08\x22\xc0\x01", "vpinsrd xmm0, xmm1, eax, 0x1"); + TEST3264("\x62\xf3\xf5\x08\x22\x00\x01", "vpinsrd xmm0, xmm1, dword ptr [eax], 0x1", "vpinsrq xmm0, xmm1, qword ptr [rax], 0x1"); // EVEX.W ignored + TEST3264("\x62\xf3\xf5\x08\x22\x40\x01\x01", "vpinsrd xmm0, xmm1, dword ptr [eax+0x4], 0x1", "vpinsrq xmm0, xmm1, qword ptr [rax+0x8], 0x1"); // EVEX.W ignored + TEST3264("\x62\xf3\xf5\x08\x22\xc0\x01", "vpinsrd xmm0, xmm1, eax, 0x1", "vpinsrq xmm0, xmm1, rax, 0x1"); // EVEX.W ignored + TEST("\x62\xf1\x7d\x08\x6e\x40\x01", "vmovd xmm0, dword ptr [@ax+0x4]"); + TEST("\x62\xf1\x7d\x28\x6e\x40\x01", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf1\x7d\x48\x6e\x40\x01", "UD"); // EVEX.L'L = 2 + TEST("\x62\xf1\x7d\x68\x6e\x40\x01", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf1\x7d\x08\x6e\xc1", "vmovd xmm0, ecx"); + TEST("\x62\xf1\x7d\x28\x6e\xc1", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf1\x7d\x48\x6e\xc1", "UD"); // EVEX.L'L = 2 + TEST("\x62\xf1\x7d\x68\x6e\xc1", "UD"); // EVEX.L'L = 3 + TEST3264("\x62\xf1\xfd\x08\x6e\x40\x01", "vmovd xmm0, dword ptr [eax+0x4]", "vmovq xmm0, qword ptr [rax+0x8]"); // EVEX.W ignored + TEST("\x62\xf1\xfd\x28\x6e\x40\x01", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf1\xfd\x48\x6e\x40\x01", "UD"); // EVEX.L'L = 2 + TEST("\x62\xf1\xfd\x68\x6e\x40\x01", "UD"); // EVEX.L'L = 3 + TEST3264("\x62\xf1\xfd\x08\x6e\xc1", "vmovd xmm0, ecx", "vmovq xmm0, rcx"); // EVEX.W ignored + TEST("\x62\xf1\xfd\x28\x6e\xc1", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf1\xfd\x48\x6e\xc1", "UD"); // EVEX.L'L = 2 + TEST("\x62\xf1\xfd\x68\x6e\xc1", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf1\x7d\x08\x7e\x40\x01", "vmovd dword ptr [@ax+0x4], xmm0"); + TEST("\x62\xf1\x7d\x28\x7e\x40\x01", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf1\x7d\x48\x7e\x40\x01", "UD"); // EVEX.L'L = 2 + TEST("\x62\xf1\x7d\x68\x7e\x40\x01", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf1\x7d\x08\x7e\xc1", "vmovd ecx, xmm0"); + TEST("\x62\xf1\x7d\x28\x7e\xc1", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf1\x7d\x48\x7e\xc1", "UD"); // EVEX.L'L = 2 + TEST("\x62\xf1\x7d\x68\x7e\xc1", "UD"); // EVEX.L'L = 3 + TEST3264("\x62\xf1\xfd\x08\x7e\x40\x01", "vmovd dword ptr [eax+0x4], xmm0", "vmovq qword ptr [rax+0x8], xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xfd\x28\x7e\x40\x01", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf1\xfd\x48\x7e\x40\x01", "UD"); // EVEX.L'L = 2 + TEST("\x62\xf1\xfd\x68\x7e\x40\x01", "UD"); // EVEX.L'L = 3 + TEST3264("\x62\xf1\xfd\x08\x7e\xc1", "vmovd ecx, xmm0", "vmovq rcx, xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xfd\x28\x7e\xc1", "UD"); // EVEX.L'L = 1 + TEST("\x62\xf1\xfd\x48\x7e\xc1", "UD"); // EVEX.L'L = 2 + TEST("\x62\xf1\xfd\x68\x7e\xc1", "UD"); // EVEX.L'L = 3 + TEST("\x62\xf2\x7d\x08\x7a\x00", "UD"); // Must have register operand + TEST("\x62\xf2\x7d\x08\x7a\xc0", "vpbroadcastb xmm0, al"); + TEST("\x62\xf2\x7d\x28\x7a\xc0", "vpbroadcastb ymm0, al"); + TEST("\x62\xf2\x7d\x48\x7a\xc0", "vpbroadcastb zmm0, al"); + TEST("\x62\xf2\xfd\x08\x7a\xc0", "UD"); // EVEX.W = 1 + TEST("\x62\xf2\x7d\x18\x7a\xc0", "UD"); // EVEX.b = 1 + TEST("\x62\xf2\x7d\x09\x7a\xc0", "vpbroadcastb xmm0{k1}, al"); + TEST("\x62\xf2\x7d\x89\x7a\xc0", "vpbroadcastb xmm0{k1}{z}, al"); + TEST("\x62\xf2\x7d\x08\x7b\x00", "UD"); // Must have register operand + TEST("\x62\xf2\x7d\x08\x7b\xc0", "vpbroadcastw xmm0, ax"); + TEST("\x62\xf2\x7d\x28\x7b\xc0", "vpbroadcastw ymm0, ax"); + TEST("\x62\xf2\x7d\x48\x7b\xc0", "vpbroadcastw zmm0, ax"); + TEST("\x62\xf2\xfd\x08\x7b\xc0", "UD"); // EVEX.W = 1 + TEST("\x62\xf2\x7d\x18\x7b\xc0", "UD"); // EVEX.b = 1 + TEST("\x62\xf2\x7d\x09\x7b\xc0", "vpbroadcastw xmm0{k1}, ax"); + TEST("\x62\xf2\x7d\x89\x7b\xc0", "vpbroadcastw xmm0{k1}{z}, ax"); + TEST("\x62\xf2\x7d\x08\x7c\x00", "UD"); // Must have register operand + TEST("\x62\xf2\x7d\x08\x7c\xc0", "vpbroadcastd xmm0, eax"); + TEST("\x62\xf2\x7d\x28\x7c\xc0", "vpbroadcastd ymm0, eax"); + TEST("\x62\xf2\x7d\x48\x7c\xc0", "vpbroadcastd zmm0, eax"); + TEST("\x62\xf2\x7d\x18\x7c\xc0", "UD"); // EVEX.b = 1 + TEST("\x62\xf2\x7d\x09\x7c\xc0", "vpbroadcastd xmm0{k1}, eax"); + TEST("\x62\xf2\x7d\x89\x7c\xc0", "vpbroadcastd xmm0{k1}{z}, eax"); + TEST("\x62\xf2\xfd\x08\x7c\x00", "UD"); // Must have register operand + TEST3264("\x62\xf2\xfd\x08\x7c\xc0", "vpbroadcastd xmm0, eax", "vpbroadcastq xmm0, rax"); // EVEX.W ignored + TEST3264("\x62\xf2\xfd\x28\x7c\xc0", "vpbroadcastd ymm0, eax", "vpbroadcastq ymm0, rax"); // EVEX.W ignored + TEST3264("\x62\xf2\xfd\x48\x7c\xc0", "vpbroadcastd zmm0, eax", "vpbroadcastq zmm0, rax"); // EVEX.W ignored + TEST("\x62\xf2\xfd\x18\x7c\xc0", "UD"); // EVEX.b = 1 + TEST3264("\x62\xf2\xfd\x09\x7c\xc0", "vpbroadcastd xmm0{k1}, eax", "vpbroadcastq xmm0{k1}, rax"); // EVEX.W ignored + TEST3264("\x62\xf2\xfd\x89\x7c\xc0", "vpbroadcastd xmm0{k1}{z}, eax", "vpbroadcastq xmm0{k1}{z}, rax"); // EVEX.W ignored + + // EVEX.z with memory or mask destination is UD + TEST32("\x62\xf2\x7d\x08\x63\x40\x01", "vpcompressb byte ptr [eax+0x1], xmm0"); + TEST32("\x67\x62\xf2\x7d\x08\x63\x40\x01", "vpcompressb byte ptr [bx+1*si+0x1], xmm0"); + TEST64("\x62\xf2\x7d\x08\x63\x40\x01", "vpcompressb byte ptr [rax+0x1], xmm0"); + TEST64("\x67\x62\xf2\x7d\x08\x63\x40\x01", "vpcompressb byte ptr [eax+0x1], xmm0"); + TEST32("\x62\xf2\x7d\x88\x63\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf2\x7d\x88\x63\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x62\xf2\x7d\x88\x63\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf2\x7d\x88\x63\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x62\xf2\x7d\x09\x63\x40\x01", "vpcompressb byte ptr [eax+0x1]{k1}, xmm0"); + TEST32("\x67\x62\xf2\x7d\x09\x63\x40\x01", "vpcompressb byte ptr [bx+1*si+0x1]{k1}, xmm0"); + TEST64("\x62\xf2\x7d\x09\x63\x40\x01", "vpcompressb byte ptr [rax+0x1]{k1}, xmm0"); + TEST64("\x67\x62\xf2\x7d\x09\x63\x40\x01", "vpcompressb byte ptr [eax+0x1]{k1}, xmm0"); + TEST32("\x62\xf2\x7d\x89\x63\x40\x01", "UD"); // EVEX.z = 1 + TEST32("\x67\x62\xf2\x7d\x89\x63\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x62\xf2\x7d\x89\x63\x40\x01", "UD"); // EVEX.z = 1 + TEST64("\x67\x62\xf2\x7d\x89\x63\x40\x01", "UD"); // EVEX.z = 1 + TEST("\x62\xf2\x7d\x08\x63\xc1", "vpcompressb xmm1, xmm0"); + TEST("\x62\xf2\x7d\x09\x63\xc1", "vpcompressb xmm1{k1}, xmm0"); + TEST("\x62\xf2\x7d\x88\x63\xc1", "UD"); // EVEX.z = 1 + TEST("\x62\xf2\x7d\x89\x63\xc1", "vpcompressb xmm1{k1}{z}, xmm0"); + TEST("\x62\xf1\x75\x08\x74\xc2", "vpcmpeqb k0, xmm1, xmm2"); + TEST("\x62\xf1\x75\x09\x74\xc2", "vpcmpeqb k0{k1}, xmm1, xmm2"); + TEST("\x62\xf1\x75\x88\x74\xc2", "UD"); // EVEX.z = 1 + TEST("\x62\xf1\x75\x89\x74\xc2", "UD"); // EVEX.z = 1 + + // CVT(T?S[SD]2U?SI|U?SI2S[SD]) ignore EVEX.W in 32-bit mode. + TEST("\x62\xf1\x7e\x08\x2c\x40\x01", "vcvttss2si eax, dword ptr [@ax+0x4]"); + TEST("\x62\xf1\x7e\x18\x2c\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x7e\x08\x2c\xc0", "vcvttss2si eax, xmm0"); + TEST("\x62\xf1\x7e\x18\x2c\xc0", "vcvttss2si eax, xmm0, {sae}"); + TEST("\x62\xf1\xfe\x08\x2c\x40\x01", "vcvttss2si @ax, dword ptr [@ax+0x4]"); // EVEX.W ignored + TEST("\x62\xf1\xfe\x08\x2c\xc0", "vcvttss2si @ax, xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xfe\x18\x2c\xc0", "vcvttss2si @ax, xmm0, {sae}"); // EVEX.W ignored + TEST("\x62\xf1\x7f\x08\x2c\x40\x01", "vcvttsd2si eax, qword ptr [@ax+0x8]"); + TEST("\x62\xf1\x7f\x18\x2c\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x7f\x08\x2c\xc0", "vcvttsd2si eax, xmm0"); + TEST("\x62\xf1\x7f\x18\x2c\xc0", "vcvttsd2si eax, xmm0, {sae}"); + TEST("\x62\xf1\xff\x08\x2c\x40\x01", "vcvttsd2si @ax, qword ptr [@ax+0x8]"); // EVEX.W ignored + TEST("\x62\xf1\xff\x08\x2c\xc0", "vcvttsd2si @ax, xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xff\x18\x2c\xc0", "vcvttsd2si @ax, xmm0, {sae}"); // EVEX.W ignored + TEST("\x62\xf1\x7e\x08\x2d\x40\x01", "vcvtss2si eax, dword ptr [@ax+0x4]"); + TEST("\x62\xf1\x7e\x18\x2d\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x7e\x08\x2d\xc0", "vcvtss2si eax, xmm0"); + TEST("\x62\xf1\x7e\x18\x2d\xc0", "vcvtss2si eax, xmm0, {rn-sae}"); + TEST("\x62\xf1\xfe\x08\x2d\x40\x01", "vcvtss2si @ax, dword ptr [@ax+0x4]"); // EVEX.W ignored + TEST("\x62\xf1\xfe\x08\x2d\xc0", "vcvtss2si @ax, xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xfe\x18\x2d\xc0", "vcvtss2si @ax, xmm0, {rn-sae}"); // EVEX.W ignored + TEST("\x62\xf1\x7f\x08\x2d\x40\x01", "vcvtsd2si eax, qword ptr [@ax+0x8]"); + TEST("\x62\xf1\x7f\x18\x2d\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x7f\x08\x2d\xc0", "vcvtsd2si eax, xmm0"); + TEST("\x62\xf1\x7f\x18\x2d\xc0", "vcvtsd2si eax, xmm0, {rn-sae}"); + TEST("\x62\xf1\xff\x08\x2d\x40\x01", "vcvtsd2si @ax, qword ptr [@ax+0x8]"); // EVEX.W ignored + TEST("\x62\xf1\xff\x08\x2d\xc0", "vcvtsd2si @ax, xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xff\x18\x2d\xc0", "vcvtsd2si @ax, xmm0, {rn-sae}"); // EVEX.W ignored + TEST("\x62\xf1\x7e\x08\x78\x40\x01", "vcvttss2usi eax, dword ptr [@ax+0x4]"); + TEST("\x62\xf1\x7e\x18\x78\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x7e\x08\x78\xc0", "vcvttss2usi eax, xmm0"); + TEST("\x62\xf1\x7e\x18\x78\xc0", "vcvttss2usi eax, xmm0, {sae}"); + TEST("\x62\xf1\xfe\x08\x78\x40\x01", "vcvttss2usi @ax, dword ptr [@ax+0x4]"); // EVEX.W ignored + TEST("\x62\xf1\xfe\x08\x78\xc0", "vcvttss2usi @ax, xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xfe\x18\x78\xc0", "vcvttss2usi @ax, xmm0, {sae}"); // EVEX.W ignored + TEST("\x62\xf1\x7f\x08\x78\x40\x01", "vcvttsd2usi eax, qword ptr [@ax+0x8]"); + TEST("\x62\xf1\x7f\x18\x78\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x7f\x08\x78\xc0", "vcvttsd2usi eax, xmm0"); + TEST("\x62\xf1\x7f\x18\x78\xc0", "vcvttsd2usi eax, xmm0, {sae}"); + TEST("\x62\xf1\xff\x08\x78\x40\x01", "vcvttsd2usi @ax, qword ptr [@ax+0x8]"); // EVEX.W ignored + TEST("\x62\xf1\xff\x08\x78\xc0", "vcvttsd2usi @ax, xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xff\x18\x78\xc0", "vcvttsd2usi @ax, xmm0, {sae}"); // EVEX.W ignored + TEST("\x62\xf1\x7e\x08\x79\x40\x01", "vcvtss2usi eax, dword ptr [@ax+0x4]"); + TEST("\x62\xf1\x7e\x18\x79\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x7e\x08\x79\xc0", "vcvtss2usi eax, xmm0"); + TEST("\x62\xf1\x7e\x18\x79\xc0", "vcvtss2usi eax, xmm0, {rn-sae}"); + TEST("\x62\xf1\xfe\x08\x79\x40\x01", "vcvtss2usi @ax, dword ptr [@ax+0x4]"); // EVEX.W ignored + TEST("\x62\xf1\xfe\x08\x79\xc0", "vcvtss2usi @ax, xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xfe\x18\x79\xc0", "vcvtss2usi @ax, xmm0, {rn-sae}"); // EVEX.W ignored + TEST("\x62\xf1\x7f\x08\x79\x40\x01", "vcvtsd2usi eax, qword ptr [@ax+0x8]"); + TEST("\x62\xf1\x7f\x18\x79\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x7f\x08\x79\xc0", "vcvtsd2usi eax, xmm0"); + TEST("\x62\xf1\x7f\x18\x79\xc0", "vcvtsd2usi eax, xmm0, {rn-sae}"); + TEST("\x62\xf1\xff\x08\x79\x40\x01", "vcvtsd2usi @ax, qword ptr [@ax+0x8]"); // EVEX.W ignored + TEST("\x62\xf1\xff\x08\x79\xc0", "vcvtsd2usi @ax, xmm0"); // EVEX.W ignored + TEST("\x62\xf1\xff\x18\x79\xc0", "vcvtsd2usi @ax, xmm0, {rn-sae}"); // EVEX.W ignored + TEST("\x62\xf1\x6e\x08\x2a\x40\x01", "vcvtsi2ss xmm0, xmm2, dword ptr [@ax+0x4]"); + TEST("\x62\xf1\x6e\x18\x2a\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x6e\x08\x2a\xc0", "vcvtsi2ss xmm0, xmm2, eax"); + TEST("\x62\xf1\x6e\x18\x2a\xc0", "vcvtsi2ss xmm0, xmm2, eax, {rn-sae}"); + TEST3264("\x62\xf1\xee\x08\x2a\x40\x01", "vcvtsi2ss xmm0, xmm2, dword ptr [eax+0x4]", "vcvtsi2ss xmm0, xmm2, qword ptr [rax+0x8]"); // EVEX.W ignored + TEST("\x62\xf1\xee\x08\x2a\xc0", "vcvtsi2ss xmm0, xmm2, @ax"); // EVEX.W ignored + TEST("\x62\xf1\xee\x18\x2a\xc0", "vcvtsi2ss xmm0, xmm2, @ax, {rn-sae}"); // EVEX.W ignored + TEST("\x62\xf1\x6f\x08\x2a\x40\x01", "vcvtsi2sd xmm0, xmm2, dword ptr [@ax+0x4]"); + TEST("\x62\xf1\x6f\x18\x2a\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x6f\x08\x2a\xc0", "vcvtsi2sd xmm0, xmm2, eax"); + TEST("\x62\xf1\x6f\x18\x2a\xc0", "vcvtsi2sd xmm0, xmm2, eax, {rn-sae}"); + TEST3264("\x62\xf1\xef\x08\x2a\x40\x01", "vcvtsi2sd xmm0, xmm2, dword ptr [eax+0x4]", "vcvtsi2sd xmm0, xmm2, qword ptr [rax+0x8]"); // EVEX.W ignored + TEST("\x62\xf1\xef\x08\x2a\xc0", "vcvtsi2sd xmm0, xmm2, @ax"); // EVEX.W ignored + TEST("\x62\xf1\xef\x18\x2a\xc0", "vcvtsi2sd xmm0, xmm2, @ax, {rn-sae}"); // EVEX.W ignored + TEST("\x62\xf1\x6e\x08\x7b\x40\x01", "vcvtusi2ss xmm0, xmm2, dword ptr [@ax+0x4]"); + TEST("\x62\xf1\x6e\x18\x7b\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x6e\x08\x7b\xc0", "vcvtusi2ss xmm0, xmm2, eax"); + TEST("\x62\xf1\x6e\x18\x7b\xc0", "vcvtusi2ss xmm0, xmm2, eax, {rn-sae}"); + TEST3264("\x62\xf1\xee\x08\x7b\x40\x01", "vcvtusi2ss xmm0, xmm2, dword ptr [eax+0x4]", "vcvtusi2ss xmm0, xmm2, qword ptr [rax+0x8]"); // EVEX.W ignored + TEST("\x62\xf1\xee\x08\x7b\xc0", "vcvtusi2ss xmm0, xmm2, @ax"); // EVEX.W ignored + TEST("\x62\xf1\xee\x18\x7b\xc0", "vcvtusi2ss xmm0, xmm2, @ax, {rn-sae}"); // EVEX.W ignored + TEST("\x62\xf1\x6f\x08\x7b\x40\x01", "vcvtusi2sd xmm0, xmm2, dword ptr [@ax+0x4]"); + TEST("\x62\xf1\x6f\x18\x7b\x40\x01", "UD"); // EVEX.b with memory operand + TEST("\x62\xf1\x6f\x08\x7b\xc0", "vcvtusi2sd xmm0, xmm2, eax"); + TEST("\x62\xf1\x6f\x18\x7b\xc0", "vcvtusi2sd xmm0, xmm2, eax, {rn-sae}"); + TEST3264("\x62\xf1\xef\x08\x7b\x40\x01", "vcvtusi2sd xmm0, xmm2, dword ptr [eax+0x4]", "vcvtusi2sd xmm0, xmm2, qword ptr [rax+0x8]"); // EVEX.W ignored + TEST("\x62\xf1\xef\x08\x7b\xc0", "vcvtusi2sd xmm0, xmm2, @ax"); // EVEX.W ignored + TEST("\x62\xf1\xef\x18\x7b\xc0", "vcvtusi2sd xmm0, xmm2, @ax, {rn-sae}"); // EVEX.W ignored + + // 32-bit mode: no UD constraints for K-reg + // 64-bit mode: EVEX.R/EVEX.vvvv=0xxx causes UD for K-reg; EVEX.B is ignored + TEST("\xc5\xed\x41\x00", "UD"); // Must have register operand + TEST("\xc5\xed\x41\xcb", "kandb k1, k2, k3"); + TEST("\xc4\xe1\x6d\x41\xcb", "kandb k1, k2, k3"); // 3-byte VEX encoding + TEST("\xc4\xc1\x6d\x41\xcb", "kandb k1, k2, k3"); // VEX.B is ignored + TEST64("\xc4\x61\x6d\x41\xcb", "UD"); // VEX.R is UD + TEST3264("\xc4\xe1\x2d\x41\xcb", "kandb k1, k2, k3", "UD"); // 32-bit: VEX.vvvv MSB is ignored, 64-bit: VEX.vvvv = 0xxx + TEST64("\xc5\xad\x41\xcb", "UD"); // VEX.vvvv = 0xxx + + TEST("\x62\xf2\x7e\x08\x28\x00", "UD"); // Must have register operand + TEST("\x62\xf2\x7e\x08\x28\xc1", "vpmovm2b xmm0, k1"); + TEST3264("\x62\xe2\x7e\x08\x28\xc1", "vpmovm2b xmm0, k1", "vpmovm2b xmm16, k1"); // EVEX.R' ignored + TEST("\x62\xd2\x7e\x08\x28\xc1", "vpmovm2b xmm0, k1"); // EVEX.B ignored + TEST64("\x62\xb2\x7e\x08\x28\xc1", "vpmovm2b xmm0, k1"); // EVEX.X ignored + TEST64("\x62\x72\x7e\x08\x28\xc1", "vpmovm2b xmm8, k1"); + TEST("\x62\xf2\xfe\x08\x28\x00", "UD"); // Must have register operand + TEST("\x62\xf2\xfe\x08\x28\xc1", "vpmovm2w xmm0, k1"); + TEST3264("\x62\xe2\xfe\x08\x28\xc1", "vpmovm2w xmm0, k1", "vpmovm2w xmm16, k1"); // EVEX.R' ignored + TEST("\x62\xd2\xfe\x08\x28\xc1", "vpmovm2w xmm0, k1"); // EVEX.B ignored + TEST64("\x62\xb2\xfe\x08\x28\xc1", "vpmovm2w xmm0, k1"); // EVEX.X ignored + TEST64("\x62\x72\xfe\x08\x28\xc1", "vpmovm2w xmm8, k1"); + TEST("\x62\xf2\x7e\x08\x38\x00", "UD"); // Must have register operand + TEST("\x62\xf2\x7e\x08\x38\xc1", "vpmovm2d xmm0, k1"); + TEST3264("\x62\xe2\x7e\x08\x38\xc1", "vpmovm2d xmm0, k1", "vpmovm2d xmm16, k1"); // EVEX.R' ignored + TEST("\x62\xd2\x7e\x08\x38\xc1", "vpmovm2d xmm0, k1"); // EVEX.B ignored + TEST64("\x62\xb2\x7e\x08\x38\xc1", "vpmovm2d xmm0, k1"); // EVEX.X ignored + TEST64("\x62\x72\x7e\x08\x38\xc1", "vpmovm2d xmm8, k1"); + TEST("\x62\xf2\xfe\x08\x38\x00", "UD"); // Must have register operand + TEST("\x62\xf2\xfe\x08\x38\xc1", "vpmovm2q xmm0, k1"); + TEST3264("\x62\xe2\xfe\x08\x38\xc1", "vpmovm2q xmm0, k1", "vpmovm2q xmm16, k1"); // EVEX.R' ignored + TEST("\x62\xd2\xfe\x08\x38\xc1", "vpmovm2q xmm0, k1"); // EVEX.B ignored + TEST64("\x62\xb2\xfe\x08\x38\xc1", "vpmovm2q xmm0, k1"); // EVEX.X ignored + TEST64("\x62\x72\xfe\x08\x38\xc1", "vpmovm2q xmm8, k1"); + + TEST("\x62\xf2\x7e\x08\x29\x00", "UD"); // Must have register operand + TEST("\x62\xf2\x7e\x08\x29\xc1", "vpmovb2m k0, xmm1"); + TEST3264("\x62\xe2\x7e\x08\x29\xc1", "vpmovb2m k0, xmm1", "UD"); // 32-bit: EVEX.R' ignored, 64-bit: EVEX.R' for mask is UD + TEST3264("\x62\xd2\x7e\x08\x29\xc1", "vpmovb2m k0, xmm1", "vpmovb2m k0, xmm9"); // EVEX.B ignored + TEST64("\x62\xb2\x7e\x08\x29\xc1", "vpmovb2m k0, xmm17"); + TEST64("\x62\x72\x7e\x08\x29\xc1", "UD"); // EVEX.R for mask is UD + TEST("\x62\xf2\xfe\x08\x29\x00", "UD"); // Must have register operand + TEST("\x62\xf2\xfe\x08\x29\xc1", "vpmovw2m k0, xmm1"); + TEST3264("\x62\xe2\xfe\x08\x29\xc1", "vpmovw2m k0, xmm1", "UD"); // 32-bit: EVEX.R' ignored, 64-bit: EVEX.R' for mask is UD + TEST3264("\x62\xd2\xfe\x08\x29\xc1", "vpmovw2m k0, xmm1", "vpmovw2m k0, xmm9"); // EVEX.B ignored + TEST64("\x62\xb2\xfe\x08\x29\xc1", "vpmovw2m k0, xmm17"); + TEST64("\x62\x72\xfe\x08\x29\xc1", "UD"); // EVEX.R for mask is UD + TEST("\x62\xf2\x7e\x08\x39\x00", "UD"); // Must have register operand + TEST("\x62\xf2\x7e\x08\x39\xc1", "vpmovd2m k0, xmm1"); + TEST3264("\x62\xe2\x7e\x08\x39\xc1", "vpmovd2m k0, xmm1", "UD"); // 32-bit: EVEX.R' ignored, 64-bit: EVEX.R' for mask is UD + TEST3264("\x62\xd2\x7e\x08\x39\xc1", "vpmovd2m k0, xmm1", "vpmovd2m k0, xmm9"); // EVEX.B ignored + TEST64("\x62\xb2\x7e\x08\x39\xc1", "vpmovd2m k0, xmm17"); + TEST64("\x62\x72\x7e\x08\x39\xc1", "UD"); // EVEX.R for mask is UD + TEST("\x62\xf2\xfe\x08\x39\x00", "UD"); // Must have register operand + TEST("\x62\xf2\xfe\x08\x39\xc1", "vpmovq2m k0, xmm1"); + TEST3264("\x62\xe2\xfe\x08\x39\xc1", "vpmovq2m k0, xmm1", "UD"); // 32-bit: EVEX.R' ignored, 64-bit: EVEX.R' for mask is UD + TEST3264("\x62\xd2\xfe\x08\x39\xc1", "vpmovq2m k0, xmm1", "vpmovq2m k0, xmm9"); // EVEX.B ignored + TEST64("\x62\xb2\xfe\x08\x39\xc1", "vpmovq2m k0, xmm17"); + TEST64("\x62\x72\xfe\x08\x39\xc1", "UD"); // EVEX.R for mask is UD + + // VSIB encoding, test all combinations of EVEX.RXBR'V' once + TEST("\x62\xf2\x7d\x0a\xa2\xcc", "UD"); // Must have memory operand + TEST("\x62\xf2\x7d\x0a\xa2\x01", "UD"); // Must have SIB byte + TEST("\x62\xf2\x7d\x08\xa2\x0c\xe7", "UD"); // EVEX.aaa = 000 + TEST3264("\x67\x62\xf2\x7d\x0a\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [edi+8*xmm4]{k2}, xmm1"); // VISB and 16-bit addrsize is UD + TEST("\x62\xf2\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [@di+8*xmm4]{k2}, xmm1"); + TEST3264("\x62\xd2\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterdps dword ptr [r15+8*xmm4]{k2}, xmm1"); + TEST64("\x62\xb2\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm12]{k2}, xmm1"); + TEST64("\x62\x92\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm12]{k2}, xmm1"); + TEST3264("\x62\xf2\x7d\x02\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [rdi+8*xmm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\x7d\x02\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [r15+8*xmm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm28]{k2}, xmm1"); + TEST64("\x62\x92\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm28]{k2}, xmm1"); + TEST64("\x62\x72\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm4]{k2}, xmm9"); + TEST64("\x62\x52\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm4]{k2}, xmm9"); + TEST64("\x62\x32\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm12]{k2}, xmm9"); + TEST64("\x62\x12\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm12]{k2}, xmm9"); + TEST64("\x62\x72\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm20]{k2}, xmm9"); + TEST64("\x62\x52\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm20]{k2}, xmm9"); + TEST64("\x62\x32\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm28]{k2}, xmm9"); + TEST64("\x62\x12\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm28]{k2}, xmm9"); + TEST3264("\x62\xe2\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterdps dword ptr [rdi+8*xmm4]{k2}, xmm17"); + TEST3264("\x62\xc2\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterdps dword ptr [r15+8*xmm4]{k2}, xmm17"); + TEST64("\x62\xa2\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm12]{k2}, xmm17"); + TEST64("\x62\x82\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm12]{k2}, xmm17"); + TEST3264("\x62\xe2\x7d\x02\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [rdi+8*xmm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\x7d\x02\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [r15+8*xmm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm28]{k2}, xmm17"); + TEST64("\x62\x82\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm28]{k2}, xmm17"); + TEST64("\x62\x62\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm4]{k2}, xmm25"); + TEST64("\x62\x42\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm4]{k2}, xmm25"); + TEST64("\x62\x22\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm12]{k2}, xmm25"); + TEST64("\x62\x02\x7d\x0a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm12]{k2}, xmm25"); + TEST64("\x62\x62\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm20]{k2}, xmm25"); + TEST64("\x62\x42\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm20]{k2}, xmm25"); + TEST64("\x62\x22\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*xmm28]{k2}, xmm25"); + TEST64("\x62\x02\x7d\x02\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*xmm28]{k2}, xmm25"); + TEST("\x62\xf2\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [@di+8*ymm4]{k2}, ymm1"); + TEST3264("\x62\xd2\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [edi+8*ymm4]{k2}, ymm1", "vscatterdps dword ptr [r15+8*ymm4]{k2}, ymm1"); + TEST64("\x62\xb2\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm12]{k2}, ymm1"); + TEST64("\x62\x92\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm12]{k2}, ymm1"); + TEST3264("\x62\xf2\x7d\x22\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [rdi+8*ymm20]{k2}, ymm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\x7d\x22\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [r15+8*ymm20]{k2}, ymm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm28]{k2}, ymm1"); + TEST64("\x62\x92\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm28]{k2}, ymm1"); + TEST64("\x62\x72\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm4]{k2}, ymm9"); + TEST64("\x62\x52\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm4]{k2}, ymm9"); + TEST64("\x62\x32\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm12]{k2}, ymm9"); + TEST64("\x62\x12\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm12]{k2}, ymm9"); + TEST64("\x62\x72\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm20]{k2}, ymm9"); + TEST64("\x62\x52\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm20]{k2}, ymm9"); + TEST64("\x62\x32\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm28]{k2}, ymm9"); + TEST64("\x62\x12\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm28]{k2}, ymm9"); + TEST3264("\x62\xe2\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [edi+8*ymm4]{k2}, ymm1", "vscatterdps dword ptr [rdi+8*ymm4]{k2}, ymm17"); + TEST3264("\x62\xc2\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [edi+8*ymm4]{k2}, ymm1", "vscatterdps dword ptr [r15+8*ymm4]{k2}, ymm17"); + TEST64("\x62\xa2\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm12]{k2}, ymm17"); + TEST64("\x62\x82\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm12]{k2}, ymm17"); + TEST3264("\x62\xe2\x7d\x22\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [rdi+8*ymm20]{k2}, ymm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\x7d\x22\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [r15+8*ymm20]{k2}, ymm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm28]{k2}, ymm17"); + TEST64("\x62\x82\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm28]{k2}, ymm17"); + TEST64("\x62\x62\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm4]{k2}, ymm25"); + TEST64("\x62\x42\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm4]{k2}, ymm25"); + TEST64("\x62\x22\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm12]{k2}, ymm25"); + TEST64("\x62\x02\x7d\x2a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm12]{k2}, ymm25"); + TEST64("\x62\x62\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm20]{k2}, ymm25"); + TEST64("\x62\x42\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm20]{k2}, ymm25"); + TEST64("\x62\x22\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*ymm28]{k2}, ymm25"); + TEST64("\x62\x02\x7d\x22\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*ymm28]{k2}, ymm25"); + TEST("\x62\xf2\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [@di+8*zmm4]{k2}, zmm1"); + TEST3264("\x62\xd2\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [edi+8*zmm4]{k2}, zmm1", "vscatterdps dword ptr [r15+8*zmm4]{k2}, zmm1"); + TEST64("\x62\xb2\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm12]{k2}, zmm1"); + TEST64("\x62\x92\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm12]{k2}, zmm1"); + TEST3264("\x62\xf2\x7d\x42\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [rdi+8*zmm20]{k2}, zmm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\x7d\x42\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [r15+8*zmm20]{k2}, zmm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm28]{k2}, zmm1"); + TEST64("\x62\x92\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm28]{k2}, zmm1"); + TEST64("\x62\x72\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm4]{k2}, zmm9"); + TEST64("\x62\x52\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm4]{k2}, zmm9"); + TEST64("\x62\x32\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm12]{k2}, zmm9"); + TEST64("\x62\x12\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm12]{k2}, zmm9"); + TEST64("\x62\x72\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm20]{k2}, zmm9"); + TEST64("\x62\x52\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm20]{k2}, zmm9"); + TEST64("\x62\x32\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm28]{k2}, zmm9"); + TEST64("\x62\x12\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm28]{k2}, zmm9"); + TEST3264("\x62\xe2\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [edi+8*zmm4]{k2}, zmm1", "vscatterdps dword ptr [rdi+8*zmm4]{k2}, zmm17"); + TEST3264("\x62\xc2\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [edi+8*zmm4]{k2}, zmm1", "vscatterdps dword ptr [r15+8*zmm4]{k2}, zmm17"); + TEST64("\x62\xa2\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm12]{k2}, zmm17"); + TEST64("\x62\x82\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm12]{k2}, zmm17"); + TEST3264("\x62\xe2\x7d\x42\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [rdi+8*zmm20]{k2}, zmm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\x7d\x42\xa2\x0c\xe7", "UD", "vscatterdps dword ptr [r15+8*zmm20]{k2}, zmm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm28]{k2}, zmm17"); + TEST64("\x62\x82\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm28]{k2}, zmm17"); + TEST64("\x62\x62\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm4]{k2}, zmm25"); + TEST64("\x62\x42\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm4]{k2}, zmm25"); + TEST64("\x62\x22\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm12]{k2}, zmm25"); + TEST64("\x62\x02\x7d\x4a\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm12]{k2}, zmm25"); + TEST64("\x62\x62\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm20]{k2}, zmm25"); + TEST64("\x62\x42\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm20]{k2}, zmm25"); + TEST64("\x62\x22\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [rdi+8*zmm28]{k2}, zmm25"); + TEST64("\x62\x02\x7d\x42\xa2\x0c\xe7", "vscatterdps dword ptr [r15+8*zmm28]{k2}, zmm25"); + TEST("\x62\xf2\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [@di+8*xmm4]{k2}, xmm1"); + TEST3264("\x62\xd2\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterqps dword ptr [r15+8*xmm4]{k2}, xmm1"); + TEST64("\x62\xb2\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm12]{k2}, xmm1"); + TEST64("\x62\x92\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm12]{k2}, xmm1"); + TEST3264("\x62\xf2\x7d\x02\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [rdi+8*xmm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\x7d\x02\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [r15+8*xmm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm28]{k2}, xmm1"); + TEST64("\x62\x92\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm28]{k2}, xmm1"); + TEST64("\x62\x72\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm4]{k2}, xmm9"); + TEST64("\x62\x52\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm4]{k2}, xmm9"); + TEST64("\x62\x32\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm12]{k2}, xmm9"); + TEST64("\x62\x12\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm12]{k2}, xmm9"); + TEST64("\x62\x72\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm20]{k2}, xmm9"); + TEST64("\x62\x52\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm20]{k2}, xmm9"); + TEST64("\x62\x32\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm28]{k2}, xmm9"); + TEST64("\x62\x12\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm28]{k2}, xmm9"); + TEST3264("\x62\xe2\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterqps dword ptr [rdi+8*xmm4]{k2}, xmm17"); + TEST3264("\x62\xc2\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterqps dword ptr [r15+8*xmm4]{k2}, xmm17"); + TEST64("\x62\xa2\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm12]{k2}, xmm17"); + TEST64("\x62\x82\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm12]{k2}, xmm17"); + TEST3264("\x62\xe2\x7d\x02\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [rdi+8*xmm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\x7d\x02\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [r15+8*xmm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm28]{k2}, xmm17"); + TEST64("\x62\x82\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm28]{k2}, xmm17"); + TEST64("\x62\x62\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm4]{k2}, xmm25"); + TEST64("\x62\x42\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm4]{k2}, xmm25"); + TEST64("\x62\x22\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm12]{k2}, xmm25"); + TEST64("\x62\x02\x7d\x0a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm12]{k2}, xmm25"); + TEST64("\x62\x62\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm20]{k2}, xmm25"); + TEST64("\x62\x42\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm20]{k2}, xmm25"); + TEST64("\x62\x22\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*xmm28]{k2}, xmm25"); + TEST64("\x62\x02\x7d\x02\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*xmm28]{k2}, xmm25"); + TEST("\x62\xf2\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [@di+8*ymm4]{k2}, xmm1"); + TEST3264("\x62\xd2\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [edi+8*ymm4]{k2}, xmm1", "vscatterqps dword ptr [r15+8*ymm4]{k2}, xmm1"); + TEST64("\x62\xb2\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm12]{k2}, xmm1"); + TEST64("\x62\x92\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm12]{k2}, xmm1"); + TEST3264("\x62\xf2\x7d\x22\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [rdi+8*ymm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\x7d\x22\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [r15+8*ymm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm28]{k2}, xmm1"); + TEST64("\x62\x92\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm28]{k2}, xmm1"); + TEST64("\x62\x72\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm4]{k2}, xmm9"); + TEST64("\x62\x52\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm4]{k2}, xmm9"); + TEST64("\x62\x32\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm12]{k2}, xmm9"); + TEST64("\x62\x12\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm12]{k2}, xmm9"); + TEST64("\x62\x72\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm20]{k2}, xmm9"); + TEST64("\x62\x52\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm20]{k2}, xmm9"); + TEST64("\x62\x32\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm28]{k2}, xmm9"); + TEST64("\x62\x12\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm28]{k2}, xmm9"); + TEST3264("\x62\xe2\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [edi+8*ymm4]{k2}, xmm1", "vscatterqps dword ptr [rdi+8*ymm4]{k2}, xmm17"); + TEST3264("\x62\xc2\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [edi+8*ymm4]{k2}, xmm1", "vscatterqps dword ptr [r15+8*ymm4]{k2}, xmm17"); + TEST64("\x62\xa2\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm12]{k2}, xmm17"); + TEST64("\x62\x82\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm12]{k2}, xmm17"); + TEST3264("\x62\xe2\x7d\x22\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [rdi+8*ymm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\x7d\x22\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [r15+8*ymm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm28]{k2}, xmm17"); + TEST64("\x62\x82\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm28]{k2}, xmm17"); + TEST64("\x62\x62\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm4]{k2}, xmm25"); + TEST64("\x62\x42\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm4]{k2}, xmm25"); + TEST64("\x62\x22\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm12]{k2}, xmm25"); + TEST64("\x62\x02\x7d\x2a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm12]{k2}, xmm25"); + TEST64("\x62\x62\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm20]{k2}, xmm25"); + TEST64("\x62\x42\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm20]{k2}, xmm25"); + TEST64("\x62\x22\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*ymm28]{k2}, xmm25"); + TEST64("\x62\x02\x7d\x22\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*ymm28]{k2}, xmm25"); + TEST("\x62\xf2\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [@di+8*zmm4]{k2}, ymm1"); + TEST3264("\x62\xd2\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [edi+8*zmm4]{k2}, ymm1", "vscatterqps dword ptr [r15+8*zmm4]{k2}, ymm1"); + TEST64("\x62\xb2\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm12]{k2}, ymm1"); + TEST64("\x62\x92\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm12]{k2}, ymm1"); + TEST3264("\x62\xf2\x7d\x42\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [rdi+8*zmm20]{k2}, ymm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\x7d\x42\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [r15+8*zmm20]{k2}, ymm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm28]{k2}, ymm1"); + TEST64("\x62\x92\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm28]{k2}, ymm1"); + TEST64("\x62\x72\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm4]{k2}, ymm9"); + TEST64("\x62\x52\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm4]{k2}, ymm9"); + TEST64("\x62\x32\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm12]{k2}, ymm9"); + TEST64("\x62\x12\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm12]{k2}, ymm9"); + TEST64("\x62\x72\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm20]{k2}, ymm9"); + TEST64("\x62\x52\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm20]{k2}, ymm9"); + TEST64("\x62\x32\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm28]{k2}, ymm9"); + TEST64("\x62\x12\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm28]{k2}, ymm9"); + TEST3264("\x62\xe2\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [edi+8*zmm4]{k2}, ymm1", "vscatterqps dword ptr [rdi+8*zmm4]{k2}, ymm17"); + TEST3264("\x62\xc2\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [edi+8*zmm4]{k2}, ymm1", "vscatterqps dword ptr [r15+8*zmm4]{k2}, ymm17"); + TEST64("\x62\xa2\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm12]{k2}, ymm17"); + TEST64("\x62\x82\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm12]{k2}, ymm17"); + TEST3264("\x62\xe2\x7d\x42\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [rdi+8*zmm20]{k2}, ymm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\x7d\x42\xa3\x0c\xe7", "UD", "vscatterqps dword ptr [r15+8*zmm20]{k2}, ymm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm28]{k2}, ymm17"); + TEST64("\x62\x82\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm28]{k2}, ymm17"); + TEST64("\x62\x62\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm4]{k2}, ymm25"); + TEST64("\x62\x42\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm4]{k2}, ymm25"); + TEST64("\x62\x22\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm12]{k2}, ymm25"); + TEST64("\x62\x02\x7d\x4a\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm12]{k2}, ymm25"); + TEST64("\x62\x62\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm20]{k2}, ymm25"); + TEST64("\x62\x42\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm20]{k2}, ymm25"); + TEST64("\x62\x22\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [rdi+8*zmm28]{k2}, ymm25"); + TEST64("\x62\x02\x7d\x42\xa3\x0c\xe7", "vscatterqps dword ptr [r15+8*zmm28]{k2}, ymm25"); + TEST("\x62\xf2\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [@di+8*xmm4]{k2}, xmm1"); + TEST3264("\x62\xd2\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterdpd qword ptr [r15+8*xmm4]{k2}, xmm1"); + TEST64("\x62\xb2\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm12]{k2}, xmm1"); + TEST64("\x62\x92\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm12]{k2}, xmm1"); + TEST3264("\x62\xf2\xfd\x02\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [rdi+8*xmm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\xfd\x02\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [r15+8*xmm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm28]{k2}, xmm1"); + TEST64("\x62\x92\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm28]{k2}, xmm1"); + TEST64("\x62\x72\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm4]{k2}, xmm9"); + TEST64("\x62\x52\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm4]{k2}, xmm9"); + TEST64("\x62\x32\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm12]{k2}, xmm9"); + TEST64("\x62\x12\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm12]{k2}, xmm9"); + TEST64("\x62\x72\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm20]{k2}, xmm9"); + TEST64("\x62\x52\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm20]{k2}, xmm9"); + TEST64("\x62\x32\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm28]{k2}, xmm9"); + TEST64("\x62\x12\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm28]{k2}, xmm9"); + TEST3264("\x62\xe2\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterdpd qword ptr [rdi+8*xmm4]{k2}, xmm17"); + TEST3264("\x62\xc2\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterdpd qword ptr [r15+8*xmm4]{k2}, xmm17"); + TEST64("\x62\xa2\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm12]{k2}, xmm17"); + TEST64("\x62\x82\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm12]{k2}, xmm17"); + TEST3264("\x62\xe2\xfd\x02\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [rdi+8*xmm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\xfd\x02\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [r15+8*xmm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm28]{k2}, xmm17"); + TEST64("\x62\x82\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm28]{k2}, xmm17"); + TEST64("\x62\x62\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm4]{k2}, xmm25"); + TEST64("\x62\x42\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm4]{k2}, xmm25"); + TEST64("\x62\x22\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm12]{k2}, xmm25"); + TEST64("\x62\x02\xfd\x0a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm12]{k2}, xmm25"); + TEST64("\x62\x62\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm20]{k2}, xmm25"); + TEST64("\x62\x42\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm20]{k2}, xmm25"); + TEST64("\x62\x22\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm28]{k2}, xmm25"); + TEST64("\x62\x02\xfd\x02\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm28]{k2}, xmm25"); + TEST("\x62\xf2\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [@di+8*xmm4]{k2}, ymm1"); + TEST3264("\x62\xd2\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [edi+8*xmm4]{k2}, ymm1", "vscatterdpd qword ptr [r15+8*xmm4]{k2}, ymm1"); + TEST64("\x62\xb2\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm12]{k2}, ymm1"); + TEST64("\x62\x92\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm12]{k2}, ymm1"); + TEST3264("\x62\xf2\xfd\x22\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [rdi+8*xmm20]{k2}, ymm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\xfd\x22\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [r15+8*xmm20]{k2}, ymm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm28]{k2}, ymm1"); + TEST64("\x62\x92\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm28]{k2}, ymm1"); + TEST64("\x62\x72\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm4]{k2}, ymm9"); + TEST64("\x62\x52\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm4]{k2}, ymm9"); + TEST64("\x62\x32\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm12]{k2}, ymm9"); + TEST64("\x62\x12\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm12]{k2}, ymm9"); + TEST64("\x62\x72\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm20]{k2}, ymm9"); + TEST64("\x62\x52\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm20]{k2}, ymm9"); + TEST64("\x62\x32\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm28]{k2}, ymm9"); + TEST64("\x62\x12\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm28]{k2}, ymm9"); + TEST3264("\x62\xe2\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [edi+8*xmm4]{k2}, ymm1", "vscatterdpd qword ptr [rdi+8*xmm4]{k2}, ymm17"); + TEST3264("\x62\xc2\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [edi+8*xmm4]{k2}, ymm1", "vscatterdpd qword ptr [r15+8*xmm4]{k2}, ymm17"); + TEST64("\x62\xa2\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm12]{k2}, ymm17"); + TEST64("\x62\x82\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm12]{k2}, ymm17"); + TEST3264("\x62\xe2\xfd\x22\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [rdi+8*xmm20]{k2}, ymm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\xfd\x22\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [r15+8*xmm20]{k2}, ymm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm28]{k2}, ymm17"); + TEST64("\x62\x82\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm28]{k2}, ymm17"); + TEST64("\x62\x62\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm4]{k2}, ymm25"); + TEST64("\x62\x42\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm4]{k2}, ymm25"); + TEST64("\x62\x22\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm12]{k2}, ymm25"); + TEST64("\x62\x02\xfd\x2a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm12]{k2}, ymm25"); + TEST64("\x62\x62\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm20]{k2}, ymm25"); + TEST64("\x62\x42\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm20]{k2}, ymm25"); + TEST64("\x62\x22\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*xmm28]{k2}, ymm25"); + TEST64("\x62\x02\xfd\x22\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*xmm28]{k2}, ymm25"); + TEST("\x62\xf2\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [@di+8*ymm4]{k2}, zmm1"); + TEST3264("\x62\xd2\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [edi+8*ymm4]{k2}, zmm1", "vscatterdpd qword ptr [r15+8*ymm4]{k2}, zmm1"); + TEST64("\x62\xb2\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm12]{k2}, zmm1"); + TEST64("\x62\x92\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm12]{k2}, zmm1"); + TEST3264("\x62\xf2\xfd\x42\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [rdi+8*ymm20]{k2}, zmm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\xfd\x42\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [r15+8*ymm20]{k2}, zmm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm28]{k2}, zmm1"); + TEST64("\x62\x92\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm28]{k2}, zmm1"); + TEST64("\x62\x72\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm4]{k2}, zmm9"); + TEST64("\x62\x52\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm4]{k2}, zmm9"); + TEST64("\x62\x32\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm12]{k2}, zmm9"); + TEST64("\x62\x12\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm12]{k2}, zmm9"); + TEST64("\x62\x72\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm20]{k2}, zmm9"); + TEST64("\x62\x52\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm20]{k2}, zmm9"); + TEST64("\x62\x32\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm28]{k2}, zmm9"); + TEST64("\x62\x12\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm28]{k2}, zmm9"); + TEST3264("\x62\xe2\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [edi+8*ymm4]{k2}, zmm1", "vscatterdpd qword ptr [rdi+8*ymm4]{k2}, zmm17"); + TEST3264("\x62\xc2\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [edi+8*ymm4]{k2}, zmm1", "vscatterdpd qword ptr [r15+8*ymm4]{k2}, zmm17"); + TEST64("\x62\xa2\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm12]{k2}, zmm17"); + TEST64("\x62\x82\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm12]{k2}, zmm17"); + TEST3264("\x62\xe2\xfd\x42\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [rdi+8*ymm20]{k2}, zmm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\xfd\x42\xa2\x0c\xe7", "UD", "vscatterdpd qword ptr [r15+8*ymm20]{k2}, zmm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm28]{k2}, zmm17"); + TEST64("\x62\x82\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm28]{k2}, zmm17"); + TEST64("\x62\x62\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm4]{k2}, zmm25"); + TEST64("\x62\x42\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm4]{k2}, zmm25"); + TEST64("\x62\x22\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm12]{k2}, zmm25"); + TEST64("\x62\x02\xfd\x4a\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm12]{k2}, zmm25"); + TEST64("\x62\x62\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm20]{k2}, zmm25"); + TEST64("\x62\x42\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm20]{k2}, zmm25"); + TEST64("\x62\x22\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [rdi+8*ymm28]{k2}, zmm25"); + TEST64("\x62\x02\xfd\x42\xa2\x0c\xe7", "vscatterdpd qword ptr [r15+8*ymm28]{k2}, zmm25"); + TEST("\x62\xf2\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [@di+8*xmm4]{k2}, xmm1"); + TEST3264("\x62\xd2\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterqpd qword ptr [r15+8*xmm4]{k2}, xmm1"); + TEST64("\x62\xb2\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm12]{k2}, xmm1"); + TEST64("\x62\x92\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm12]{k2}, xmm1"); + TEST3264("\x62\xf2\xfd\x02\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [rdi+8*xmm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\xfd\x02\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [r15+8*xmm20]{k2}, xmm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm28]{k2}, xmm1"); + TEST64("\x62\x92\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm28]{k2}, xmm1"); + TEST64("\x62\x72\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm4]{k2}, xmm9"); + TEST64("\x62\x52\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm4]{k2}, xmm9"); + TEST64("\x62\x32\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm12]{k2}, xmm9"); + TEST64("\x62\x12\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm12]{k2}, xmm9"); + TEST64("\x62\x72\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm20]{k2}, xmm9"); + TEST64("\x62\x52\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm20]{k2}, xmm9"); + TEST64("\x62\x32\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm28]{k2}, xmm9"); + TEST64("\x62\x12\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm28]{k2}, xmm9"); + TEST3264("\x62\xe2\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterqpd qword ptr [rdi+8*xmm4]{k2}, xmm17"); + TEST3264("\x62\xc2\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [edi+8*xmm4]{k2}, xmm1", "vscatterqpd qword ptr [r15+8*xmm4]{k2}, xmm17"); + TEST64("\x62\xa2\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm12]{k2}, xmm17"); + TEST64("\x62\x82\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm12]{k2}, xmm17"); + TEST3264("\x62\xe2\xfd\x02\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [rdi+8*xmm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\xfd\x02\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [r15+8*xmm20]{k2}, xmm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm28]{k2}, xmm17"); + TEST64("\x62\x82\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm28]{k2}, xmm17"); + TEST64("\x62\x62\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm4]{k2}, xmm25"); + TEST64("\x62\x42\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm4]{k2}, xmm25"); + TEST64("\x62\x22\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm12]{k2}, xmm25"); + TEST64("\x62\x02\xfd\x0a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm12]{k2}, xmm25"); + TEST64("\x62\x62\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm20]{k2}, xmm25"); + TEST64("\x62\x42\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm20]{k2}, xmm25"); + TEST64("\x62\x22\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*xmm28]{k2}, xmm25"); + TEST64("\x62\x02\xfd\x02\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*xmm28]{k2}, xmm25"); + TEST("\x62\xf2\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [@di+8*ymm4]{k2}, ymm1"); + TEST3264("\x62\xd2\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [edi+8*ymm4]{k2}, ymm1", "vscatterqpd qword ptr [r15+8*ymm4]{k2}, ymm1"); + TEST64("\x62\xb2\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm12]{k2}, ymm1"); + TEST64("\x62\x92\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm12]{k2}, ymm1"); + TEST3264("\x62\xf2\xfd\x22\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [rdi+8*ymm20]{k2}, ymm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\xfd\x22\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [r15+8*ymm20]{k2}, ymm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm28]{k2}, ymm1"); + TEST64("\x62\x92\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm28]{k2}, ymm1"); + TEST64("\x62\x72\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm4]{k2}, ymm9"); + TEST64("\x62\x52\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm4]{k2}, ymm9"); + TEST64("\x62\x32\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm12]{k2}, ymm9"); + TEST64("\x62\x12\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm12]{k2}, ymm9"); + TEST64("\x62\x72\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm20]{k2}, ymm9"); + TEST64("\x62\x52\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm20]{k2}, ymm9"); + TEST64("\x62\x32\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm28]{k2}, ymm9"); + TEST64("\x62\x12\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm28]{k2}, ymm9"); + TEST3264("\x62\xe2\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [edi+8*ymm4]{k2}, ymm1", "vscatterqpd qword ptr [rdi+8*ymm4]{k2}, ymm17"); + TEST3264("\x62\xc2\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [edi+8*ymm4]{k2}, ymm1", "vscatterqpd qword ptr [r15+8*ymm4]{k2}, ymm17"); + TEST64("\x62\xa2\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm12]{k2}, ymm17"); + TEST64("\x62\x82\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm12]{k2}, ymm17"); + TEST3264("\x62\xe2\xfd\x22\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [rdi+8*ymm20]{k2}, ymm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\xfd\x22\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [r15+8*ymm20]{k2}, ymm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm28]{k2}, ymm17"); + TEST64("\x62\x82\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm28]{k2}, ymm17"); + TEST64("\x62\x62\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm4]{k2}, ymm25"); + TEST64("\x62\x42\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm4]{k2}, ymm25"); + TEST64("\x62\x22\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm12]{k2}, ymm25"); + TEST64("\x62\x02\xfd\x2a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm12]{k2}, ymm25"); + TEST64("\x62\x62\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm20]{k2}, ymm25"); + TEST64("\x62\x42\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm20]{k2}, ymm25"); + TEST64("\x62\x22\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*ymm28]{k2}, ymm25"); + TEST64("\x62\x02\xfd\x22\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*ymm28]{k2}, ymm25"); + TEST("\x62\xf2\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [@di+8*zmm4]{k2}, zmm1"); + TEST3264("\x62\xd2\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [edi+8*zmm4]{k2}, zmm1", "vscatterqpd qword ptr [r15+8*zmm4]{k2}, zmm1"); + TEST64("\x62\xb2\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm12]{k2}, zmm1"); + TEST64("\x62\x92\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm12]{k2}, zmm1"); + TEST3264("\x62\xf2\xfd\x42\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [rdi+8*zmm20]{k2}, zmm1"); // EVEX.V' == 0 + TEST3264("\x62\xd2\xfd\x42\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [r15+8*zmm20]{k2}, zmm1"); // EVEX.V' == 0 + TEST64("\x62\xb2\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm28]{k2}, zmm1"); + TEST64("\x62\x92\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm28]{k2}, zmm1"); + TEST64("\x62\x72\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm4]{k2}, zmm9"); + TEST64("\x62\x52\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm4]{k2}, zmm9"); + TEST64("\x62\x32\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm12]{k2}, zmm9"); + TEST64("\x62\x12\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm12]{k2}, zmm9"); + TEST64("\x62\x72\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm20]{k2}, zmm9"); + TEST64("\x62\x52\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm20]{k2}, zmm9"); + TEST64("\x62\x32\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm28]{k2}, zmm9"); + TEST64("\x62\x12\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm28]{k2}, zmm9"); + TEST3264("\x62\xe2\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [edi+8*zmm4]{k2}, zmm1", "vscatterqpd qword ptr [rdi+8*zmm4]{k2}, zmm17"); + TEST3264("\x62\xc2\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [edi+8*zmm4]{k2}, zmm1", "vscatterqpd qword ptr [r15+8*zmm4]{k2}, zmm17"); + TEST64("\x62\xa2\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm12]{k2}, zmm17"); + TEST64("\x62\x82\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm12]{k2}, zmm17"); + TEST3264("\x62\xe2\xfd\x42\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [rdi+8*zmm20]{k2}, zmm17"); // EVEX.V' == 0 + TEST3264("\x62\xc2\xfd\x42\xa3\x0c\xe7", "UD", "vscatterqpd qword ptr [r15+8*zmm20]{k2}, zmm17"); // EVEX.V' == 0 + TEST64("\x62\xa2\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm28]{k2}, zmm17"); + TEST64("\x62\x82\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm28]{k2}, zmm17"); + TEST64("\x62\x62\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm4]{k2}, zmm25"); + TEST64("\x62\x42\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm4]{k2}, zmm25"); + TEST64("\x62\x22\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm12]{k2}, zmm25"); + TEST64("\x62\x02\xfd\x4a\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm12]{k2}, zmm25"); + TEST64("\x62\x62\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm20]{k2}, zmm25"); + TEST64("\x62\x42\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm20]{k2}, zmm25"); + TEST64("\x62\x22\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [rdi+8*zmm28]{k2}, zmm25"); + TEST64("\x62\x02\xfd\x42\xa3\x0c\xe7", "vscatterqpd qword ptr [r15+8*zmm28]{k2}, zmm25"); + + // All EVEX-VSIB instructions. VSCATTER* cases additionally test scaled offset. + TEST("\x62\xf2\x7d\x09\xa2\x44\xe7\x01", "vscatterdps dword ptr [@di+8*xmm4+0x4]{k1}, xmm0"); + TEST("\x62\xf2\x7d\x29\xa2\x44\xe7\x01", "vscatterdps dword ptr [@di+8*ymm4+0x4]{k1}, ymm0"); + TEST("\x62\xf2\x7d\x49\xa2\x44\xe7\x01", "vscatterdps dword ptr [@di+8*zmm4+0x4]{k1}, zmm0"); + TEST("\x62\xf2\x7d\x09\xa3\x44\xe7\x01", "vscatterqps dword ptr [@di+8*xmm4+0x4]{k1}, xmm0"); + TEST("\x62\xf2\x7d\x29\xa3\x44\xe7\x01", "vscatterqps dword ptr [@di+8*ymm4+0x4]{k1}, xmm0"); + TEST("\x62\xf2\x7d\x49\xa3\x44\xe7\x01", "vscatterqps dword ptr [@di+8*zmm4+0x4]{k1}, ymm0"); + TEST("\x62\xf2\xfd\x09\xa2\x44\xe7\x01", "vscatterdpd qword ptr [@di+8*xmm4+0x8]{k1}, xmm0"); + TEST("\x62\xf2\xfd\x29\xa2\x44\xe7\x01", "vscatterdpd qword ptr [@di+8*xmm4+0x8]{k1}, ymm0"); + TEST("\x62\xf2\xfd\x49\xa2\x44\xe7\x01", "vscatterdpd qword ptr [@di+8*ymm4+0x8]{k1}, zmm0"); + TEST("\x62\xf2\xfd\x09\xa3\x44\xe7\x01", "vscatterqpd qword ptr [@di+8*xmm4+0x8]{k1}, xmm0"); + TEST("\x62\xf2\xfd\x29\xa3\x44\xe7\x01", "vscatterqpd qword ptr [@di+8*ymm4+0x8]{k1}, ymm0"); + TEST("\x62\xf2\xfd\x49\xa3\x44\xe7\x01", "vscatterqpd qword ptr [@di+8*zmm4+0x8]{k1}, zmm0"); + TEST("\x62\xf2\x7d\x09\xa0\x44\xe7\x01", "vpscatterdd dword ptr [@di+8*xmm4+0x4]{k1}, xmm0"); + TEST("\x62\xf2\x7d\x29\xa0\x44\xe7\x01", "vpscatterdd dword ptr [@di+8*ymm4+0x4]{k1}, ymm0"); + TEST("\x62\xf2\x7d\x49\xa0\x44\xe7\x01", "vpscatterdd dword ptr [@di+8*zmm4+0x4]{k1}, zmm0"); + TEST("\x62\xf2\x7d\x09\xa1\x44\xe7\x01", "vpscatterqd dword ptr [@di+8*xmm4+0x4]{k1}, xmm0"); + TEST("\x62\xf2\x7d\x29\xa1\x44\xe7\x01", "vpscatterqd dword ptr [@di+8*ymm4+0x4]{k1}, xmm0"); + TEST("\x62\xf2\x7d\x49\xa1\x44\xe7\x01", "vpscatterqd dword ptr [@di+8*zmm4+0x4]{k1}, ymm0"); + TEST("\x62\xf2\xfd\x09\xa0\x44\xe7\x01", "vpscatterdq qword ptr [@di+8*xmm4+0x8]{k1}, xmm0"); + TEST("\x62\xf2\xfd\x29\xa0\x44\xe7\x01", "vpscatterdq qword ptr [@di+8*xmm4+0x8]{k1}, ymm0"); + TEST("\x62\xf2\xfd\x49\xa0\x44\xe7\x01", "vpscatterdq qword ptr [@di+8*ymm4+0x8]{k1}, zmm0"); + TEST("\x62\xf2\xfd\x09\xa1\x44\xe7\x01", "vpscatterqq qword ptr [@di+8*xmm4+0x8]{k1}, xmm0"); + TEST("\x62\xf2\xfd\x29\xa1\x44\xe7\x01", "vpscatterqq qword ptr [@di+8*ymm4+0x8]{k1}, ymm0"); + TEST("\x62\xf2\xfd\x49\xa1\x44\xe7\x01", "vpscatterqq qword ptr [@di+8*zmm4+0x8]{k1}, zmm0"); + TEST("\x62\xf2\x7d\x09\x90\x44\xe7\x01", "vpgatherdd xmm0{k1}, dword ptr [@di+8*xmm4+0x4]"); + TEST("\x62\xf2\x7d\x29\x90\x44\xe7\x01", "vpgatherdd ymm0{k1}, dword ptr [@di+8*ymm4+0x4]"); + TEST("\x62\xf2\x7d\x49\x90\x44\xe7\x01", "vpgatherdd zmm0{k1}, dword ptr [@di+8*zmm4+0x4]"); + TEST("\x62\xf2\x7d\x09\x91\x44\xe7\x01", "vpgatherqd xmm0{k1}, dword ptr [@di+8*xmm4+0x4]"); + TEST("\x62\xf2\x7d\x29\x91\x44\xe7\x01", "vpgatherqd xmm0{k1}, dword ptr [@di+8*ymm4+0x4]"); + TEST("\x62\xf2\x7d\x49\x91\x44\xe7\x01", "vpgatherqd ymm0{k1}, dword ptr [@di+8*zmm4+0x4]"); + TEST("\x62\xf2\xfd\x09\x90\x44\xe7\x01", "vpgatherdq xmm0{k1}, qword ptr [@di+8*xmm4+0x8]"); + TEST("\x62\xf2\xfd\x29\x90\x44\xe7\x01", "vpgatherdq ymm0{k1}, qword ptr [@di+8*xmm4+0x8]"); + TEST("\x62\xf2\xfd\x49\x90\x44\xe7\x01", "vpgatherdq zmm0{k1}, qword ptr [@di+8*ymm4+0x8]"); + TEST("\x62\xf2\xfd\x09\x91\x44\xe7\x01", "vpgatherqq xmm0{k1}, qword ptr [@di+8*xmm4+0x8]"); + TEST("\x62\xf2\xfd\x29\x91\x44\xe7\x01", "vpgatherqq ymm0{k1}, qword ptr [@di+8*ymm4+0x8]"); + TEST("\x62\xf2\xfd\x49\x91\x44\xe7\x01", "vpgatherqq zmm0{k1}, qword ptr [@di+8*zmm4+0x8]"); + TEST("\x62\xf2\x7d\x09\x92\x44\xe7\x01", "vgatherdps xmm0{k1}, dword ptr [@di+8*xmm4+0x4]"); + TEST("\x62\xf2\x7d\x29\x92\x44\xe7\x01", "vgatherdps ymm0{k1}, dword ptr [@di+8*ymm4+0x4]"); + TEST("\x62\xf2\x7d\x49\x92\x44\xe7\x01", "vgatherdps zmm0{k1}, dword ptr [@di+8*zmm4+0x4]"); + TEST("\x62\xf2\x7d\x09\x93\x44\xe7\x01", "vgatherqps xmm0{k1}, dword ptr [@di+8*xmm4+0x4]"); + TEST("\x62\xf2\x7d\x29\x93\x44\xe7\x01", "vgatherqps xmm0{k1}, dword ptr [@di+8*ymm4+0x4]"); + TEST("\x62\xf2\x7d\x49\x93\x44\xe7\x01", "vgatherqps ymm0{k1}, dword ptr [@di+8*zmm4+0x4]"); + TEST("\x62\xf2\xfd\x09\x92\x44\xe7\x01", "vgatherdpd xmm0{k1}, qword ptr [@di+8*xmm4+0x8]"); + TEST("\x62\xf2\xfd\x29\x92\x44\xe7\x01", "vgatherdpd ymm0{k1}, qword ptr [@di+8*xmm4+0x8]"); + TEST("\x62\xf2\xfd\x49\x92\x44\xe7\x01", "vgatherdpd zmm0{k1}, qword ptr [@di+8*ymm4+0x8]"); + TEST("\x62\xf2\xfd\x09\x93\x44\xe7\x01", "vgatherqpd xmm0{k1}, qword ptr [@di+8*xmm4+0x8]"); + TEST("\x62\xf2\xfd\x29\x93\x44\xe7\x01", "vgatherqpd ymm0{k1}, qword ptr [@di+8*ymm4+0x8]"); + TEST("\x62\xf2\xfd\x49\x93\x44\xe7\x01", "vgatherqpd zmm0{k1}, qword ptr [@di+8*zmm4+0x8]"); + + // AVX512-FP16 + TEST("\x62\xf5\x74\x08\x5c\xc2", "vsubph xmm0, xmm1, xmm2"); + TEST("\x62\xf5\x74\x28\x5c\xc2", "vsubph ymm0, ymm1, ymm2"); + TEST("\x62\xf5\x74\x48\x5c\xc2", "vsubph zmm0, zmm1, zmm2"); + TEST("\x62\xf5\x74\x08\x5c\x42\x01", "vsubph xmm0, xmm1, xmmword ptr [@dx+0x10]"); + TEST("\x62\xf5\x74\x28\x5c\x42\x01", "vsubph ymm0, ymm1, ymmword ptr [@dx+0x20]"); + TEST("\x62\xf5\x74\x48\x5c\x42\x01", "vsubph zmm0, zmm1, zmmword ptr [@dx+0x40]"); + TEST("\x62\xf5\x74\x18\x5c\x42\x01", "vsubph xmm0, xmm1, word ptr [@dx+0x2]{1to8}"); + TEST("\x62\xf5\x74\x38\x5c\x42\x01", "vsubph ymm0, ymm1, word ptr [@dx+0x2]{1to16}"); + TEST("\x62\xf5\x74\x58\x5c\x42\x01", "vsubph zmm0, zmm1, word ptr [@dx+0x2]{1to32}"); + TEST64("\x62\x93\x36\x34\xc2\xeb\x89", "vcmpsh k5{k4}, xmm25, xmm27, 0x89, {sae}"); + TEST("\x62\xf5\x66\x4c\x11\xd5", "vmovsh xmm5{k4}, xmm3, xmm2"); + TEST64("\x62\x25\x66\x4c\x11\xd5", "vmovsh xmm21{k4}, xmm3, xmm26"); + + // GFNI + TEST("\x66\x0f\x38\xcf\xc1", "gf2p8mulb xmm0, xmm1"); + TEST("\x66\x0f\x3a\xce\xc1\x01", "gf2p8affineqb xmm0, xmm1, 0x1"); + TEST("\x66\x0f\x3a\xcf\xc1\x01", "gf2p8affineinvqb xmm0, xmm1, 0x1"); + TEST("\xc4\xe2\x69\xcf\xc1", "vgf2p8mulb xmm0, xmm2, xmm1"); + TEST("\xc4\xe2\x6d\xcf\xc1", "vgf2p8mulb ymm0, ymm2, ymm1"); + TEST("\xc4\xe3\xe9\xce\xc1\x01", "vgf2p8affineqb xmm0, xmm2, xmm1, 0x1"); + TEST("\xc4\xe3\xed\xce\xc1\x01", "vgf2p8affineqb ymm0, ymm2, ymm1, 0x1"); + TEST("\xc4\xe3\xe9\xcf\xc1\x01", "vgf2p8affineinvqb xmm0, xmm2, xmm1, 0x1"); + TEST("\xc4\xe3\xed\xcf\xc1\x01", "vgf2p8affineinvqb ymm0, ymm2, ymm1, 0x1"); + TEST("\x62\xf3\xdd\x18\xcf\x49\x01\x07", "vgf2p8affineinvqb xmm1, xmm4, qword ptr [@cx+0x8]{1to2}, 0x7"); + TEST64("\x62\xf3\xdd\x10\xcf\x49\x01\x07", "vgf2p8affineinvqb xmm1, xmm20, qword ptr [rcx+0x8]{1to2}, 0x7"); + + // AMD RDPRU + TEST64("\x0f\x01\xfd", "rdpru"); + TEST64("\x66\x0f\x01\xfd", "rdpru"); // 66 prefix ignored + + // AMD SNP + TEST64("\xf3\x0f\x01\xfd", "rmpquery"); + TEST64("\xf2\x0f\x01\xfd", "rmpread"); + TEST64("\xf3\x0f\x01\xfe", "rmpadjust"); + TEST64("\xf2\x0f\x01\xfe", "rmpupdate"); + TEST64("\xf3\x0f\x01\xff", "psmash"); + TEST64("\xf2\x0f\x01\xff", "pvalidate"); + + // PBNDKB + TEST3264("\x0f\x01\xc7", "UD", "pbndkb"); + + // SM4 + TEST("\xc4\xe2\x6a\xda\x01", "vsm4key4 xmm0, xmm2, xmmword ptr [@cx]"); + TEST("\xc4\xe2\x6e\xda\x01", "vsm4key4 ymm0, ymm2, ymmword ptr [@cx]"); + TEST("\xc4\xe2\x6a\xda\xc1", "vsm4key4 xmm0, xmm2, xmm1"); + TEST("\xc4\xe2\x6e\xda\xc1", "vsm4key4 ymm0, ymm2, ymm1"); + TEST("\x62\xf2\x6e\x08\xda\x01", "vsm4key4 xmm0, xmm2, xmmword ptr [@cx]"); + TEST("\x62\xf2\x6e\x28\xda\x01", "vsm4key4 ymm0, ymm2, ymmword ptr [@cx]"); + TEST("\x62\xf2\x6e\x48\xda\x01", "vsm4key4 zmm0, zmm2, zmmword ptr [@cx]"); + TEST("\x62\xf2\x6e\x08\xda\xc1", "vsm4key4 xmm0, xmm2, xmm1"); + TEST("\x62\xf2\x6e\x28\xda\xc1", "vsm4key4 ymm0, ymm2, ymm1"); + TEST("\x62\xf2\x6e\x48\xda\xc1", "vsm4key4 zmm0, zmm2, zmm1"); + TEST("\xc4\xe2\x6b\xda\x01", "vsm4rnds4 xmm0, xmm2, xmmword ptr [@cx]"); + TEST("\xc4\xe2\x6f\xda\x01", "vsm4rnds4 ymm0, ymm2, ymmword ptr [@cx]"); + TEST("\xc4\xe2\x6b\xda\xc1", "vsm4rnds4 xmm0, xmm2, xmm1"); + TEST("\xc4\xe2\x6f\xda\xc1", "vsm4rnds4 ymm0, ymm2, ymm1"); + TEST("\x62\xf2\x6f\x08\xda\x01", "vsm4rnds4 xmm0, xmm2, xmmword ptr [@cx]"); + TEST("\x62\xf2\x6f\x28\xda\x01", "vsm4rnds4 ymm0, ymm2, ymmword ptr [@cx]"); + TEST("\x62\xf2\x6f\x48\xda\x01", "vsm4rnds4 zmm0, zmm2, zmmword ptr [@cx]"); + TEST("\x62\xf2\x6f\x08\xda\xc1", "vsm4rnds4 xmm0, xmm2, xmm1"); + TEST("\x62\xf2\x6f\x28\xda\xc1", "vsm4rnds4 ymm0, ymm2, ymm1"); + TEST("\x62\xf2\x6f\x48\xda\xc1", "vsm4rnds4 zmm0, zmm2, zmm1"); + + + puts(failed ? "Some tests FAILED" : "All tests PASSED"); + return failed ? EXIT_FAILURE : EXIT_SUCCESS; +} diff --git a/third_party/fadec/decode.c b/third_party/fadec/decode.c new file mode 100644 index 0000000..fc493be --- /dev/null +++ b/third_party/fadec/decode.c @@ -0,0 +1,791 @@ + +#include +#include +#include + +#include + + +#ifdef __GNUC__ +#define LIKELY(x) __builtin_expect((x), 1) +#define UNLIKELY(x) __builtin_expect((x), 0) +#define ASSUME(x) do { if (!(x)) __builtin_unreachable(); } while (0) +#else +#define LIKELY(x) (x) +#define UNLIKELY(x) (x) +#define ASSUME(x) ((void) 0) +#endif + +// Defines FD_TABLE_OFFSET_32 and FD_TABLE_OFFSET_64, if available +#define FD_DECODE_TABLE_DEFINES +#include +#undef FD_DECODE_TABLE_DEFINES + +enum DecodeMode { + DECODE_64 = 0, + DECODE_32 = 1, +}; + +typedef enum DecodeMode DecodeMode; + +#define ENTRY_NONE 0 +#define ENTRY_INSTR 1 +#define ENTRY_TABLE256 2 +#define ENTRY_TABLE16 3 +#define ENTRY_TABLE8E 4 +#define ENTRY_TABLE_PREFIX 5 +#define ENTRY_TABLE_VEX 6 +#define ENTRY_TABLE_ROOT 8 +#define ENTRY_MASK 7 + +static uint16_t +table_lookup(unsigned cur_idx, unsigned entry_idx) { + static _Alignas(16) const uint16_t _decode_table[] = { +#define FD_DECODE_TABLE_DATA +#include +#undef FD_DECODE_TABLE_DATA + }; + return _decode_table[cur_idx + entry_idx]; +} + +static unsigned +table_walk(unsigned table_entry, unsigned entry_idx) { + return table_lookup(table_entry & ~0x3, entry_idx); +} + +#define LOAD_LE_1(buf) ((uint64_t) *(const uint8_t*) (buf)) +#define LOAD_LE_2(buf) (LOAD_LE_1(buf) | LOAD_LE_1((const uint8_t*) (buf) + 1)<<8) +#define LOAD_LE_3(buf) (LOAD_LE_2(buf) | LOAD_LE_1((const uint8_t*) (buf) + 2)<<16) +#define LOAD_LE_4(buf) (LOAD_LE_2(buf) | LOAD_LE_2((const uint8_t*) (buf) + 2)<<16) +#define LOAD_LE_8(buf) (LOAD_LE_4(buf) | LOAD_LE_4((const uint8_t*) (buf) + 4)<<32) + +enum +{ + PREFIX_REXB = 0x01, + PREFIX_REXX = 0x02, + PREFIX_REXR = 0x04, + PREFIX_REXW = 0x08, + PREFIX_REX = 0x40, + PREFIX_REXRR = 0x10, + PREFIX_VEX = 0x20, +}; + +struct InstrDesc +{ + uint16_t type; + uint16_t operand_indices; + uint16_t operand_sizes; + uint16_t reg_types; +}; + +#define DESC_HAS_MODRM(desc) (((desc)->operand_indices & (3 << 0)) != 0) +#define DESC_MODRM_IDX(desc) ((((desc)->operand_indices >> 0) & 3) ^ 3) +#define DESC_HAS_MODREG(desc) (((desc)->operand_indices & (3 << 2)) != 0) +#define DESC_MODREG_IDX(desc) ((((desc)->operand_indices >> 2) & 3) ^ 3) +#define DESC_HAS_VEXREG(desc) (((desc)->operand_indices & (3 << 4)) != 0) +#define DESC_VEXREG_IDX(desc) ((((desc)->operand_indices >> 4) & 3) ^ 3) +#define DESC_IMM_CONTROL(desc) (((desc)->operand_indices >> 12) & 0x7) +#define DESC_IMM_IDX(desc) ((((desc)->operand_indices >> 6) & 3) ^ 3) +#define DESC_EVEX_BCST(desc) (((desc)->operand_indices >> 8) & 1) +#define DESC_EVEX_MASK(desc) (((desc)->operand_indices >> 9) & 1) +#define DESC_ZEROREG_VAL(desc) (((desc)->operand_indices >> 10) & 1) +#define DESC_LOCK(desc) (((desc)->operand_indices >> 11) & 1) +#define DESC_VSIB(desc) (((desc)->operand_indices >> 15) & 1) +#define DESC_OPSIZE(desc) (((desc)->reg_types >> 11) & 7) +#define DESC_MODRM_SIZE(desc) (((desc)->operand_sizes >> 0) & 3) +#define DESC_MODREG_SIZE(desc) (((desc)->operand_sizes >> 2) & 3) +#define DESC_VEXREG_SIZE(desc) (((desc)->operand_sizes >> 4) & 3) +#define DESC_IMM_SIZE(desc) (((desc)->operand_sizes >> 6) & 3) +#define DESC_LEGACY(desc) (((desc)->operand_sizes >> 8) & 1) +#define DESC_SIZE_FIX1(desc) (((desc)->operand_sizes >> 10) & 7) +#define DESC_SIZE_FIX2(desc) (((desc)->operand_sizes >> 13) & 3) +#define DESC_INSTR_WIDTH(desc) (((desc)->operand_sizes >> 15) & 1) +#define DESC_MODRM(desc) (((desc)->reg_types >> 14) & 1) +#define DESC_IGN66(desc) (((desc)->reg_types >> 15) & 1) +#define DESC_EVEX_SAE(desc) (((desc)->reg_types >> 8) & 1) +#define DESC_EVEX_ER(desc) (((desc)->reg_types >> 9) & 1) +#define DESC_EVEX_BCST16(desc) (((desc)->reg_types >> 10) & 1) +#define DESC_REGTY_MODRM(desc) (((desc)->reg_types >> 0) & 7) +#define DESC_REGTY_MODREG(desc) (((desc)->reg_types >> 3) & 7) +#define DESC_REGTY_VEXREG(desc) (((desc)->reg_types >> 6) & 3) + +int +fd_decode(const uint8_t* buffer, size_t len_sz, int mode_int, uintptr_t address, + FdInstr* instr) +{ + int len = len_sz > 15 ? 15 : len_sz; + + // Ensure that we can actually handle the decode request + DecodeMode mode; + unsigned table_root_idx; + switch (mode_int) + { +#if defined(FD_TABLE_OFFSET_32) + case 32: table_root_idx = FD_TABLE_OFFSET_32; mode = DECODE_32; break; +#endif +#if defined(FD_TABLE_OFFSET_64) + case 64: table_root_idx = FD_TABLE_OFFSET_64; mode = DECODE_64; break; +#endif + default: return FD_ERR_INTERNAL; + } + + int off = 0; + uint8_t vex_operand = 0; + + uint8_t addr_size = mode == DECODE_64 ? 3 : 2; + unsigned prefix_rex = 0; + uint8_t prefix_rep = 0; + unsigned vexl = 0; + unsigned prefix_evex = 0; + instr->segment = FD_REG_NONE; + + // Values must match prefixes in parseinstrs.py. + enum { + PF_SEG1 = 0xfff8 - 0xfff8, + PF_SEG2 = 0xfff9 - 0xfff8, + PF_66 = 0xfffa - 0xfff8, + PF_67 = 0xfffb - 0xfff8, + PF_LOCK = 0xfffc - 0xfff8, + PF_REP = 0xfffd - 0xfff8, + PF_REX = 0xfffe - 0xfff8, + }; + + uint8_t prefixes[8] = {0}; + unsigned table_entry = 0; + while (true) { + if (UNLIKELY(off >= len)) + return FD_ERR_PARTIAL; + uint8_t prefix = buffer[off]; + table_entry = table_lookup(table_root_idx, prefix); + if (LIKELY(table_entry - 0xfff8 >= 8)) + break; + prefixes[PF_REX] = 0; + prefixes[table_entry - 0xfff8] = prefix; + off++; + } + if (off) { + if (UNLIKELY(prefixes[PF_SEG2])) { + if (prefixes[PF_SEG2] & 0x02) + instr->segment = prefixes[PF_SEG2] >> 3 & 3; + else + instr->segment = prefixes[PF_SEG2] & 7; + } + if (UNLIKELY(prefixes[PF_67])) + addr_size--; + prefix_rex = prefixes[PF_REX]; + prefix_rep = prefixes[PF_REP]; + } + + // table_entry kinds: INSTR(0), T16(1), ESCAPE_A(2), ESCAPE_B(3) + if (LIKELY(!(table_entry & 2))) { + off++; + + // Then, walk through ModR/M-encoded opcode extensions. + if (table_entry & 1) { + if (UNLIKELY(off >= len)) + return FD_ERR_PARTIAL; + unsigned isreg = buffer[off] >= 0xc0; + table_entry = table_walk(table_entry, ((buffer[off] >> 2) & 0xe) | isreg); + // table_entry kinds: INSTR(0), T8E(1) + if (table_entry & 1) + table_entry = table_walk(table_entry, buffer[off] & 7); + } + + // table_entry kinds: INSTR(0) + goto direct; + } + + if (UNLIKELY(off >= len)) + return FD_ERR_PARTIAL; + + unsigned opcode_escape = 0; + uint8_t mandatory_prefix = 0; // without escape/VEX/EVEX, this is ignored. + if (buffer[off] == 0x0f) + { + if (UNLIKELY(off + 1 >= len)) + return FD_ERR_PARTIAL; + if (buffer[off + 1] == 0x38) + opcode_escape = 2; + else if (buffer[off + 1] == 0x3a) + opcode_escape = 3; + else + opcode_escape = 1; + off += opcode_escape >= 2 ? 2 : 1; + + // If there is no REP/REPNZ prefix offer 66h as mandatory prefix. If + // there is a REP prefix, then the 66h prefix is ignored here. + mandatory_prefix = prefix_rep ? prefix_rep ^ 0xf1 : !!prefixes[PF_66]; + } + else if (UNLIKELY((unsigned) buffer[off] - 0xc4 < 2 || buffer[off] == 0x62)) + { + unsigned vex_prefix = buffer[off]; + // VEX (C4/C5) or EVEX (62) + if (UNLIKELY(off + 1 >= len)) + return FD_ERR_PARTIAL; + if (UNLIKELY(mode == DECODE_32 && buffer[off + 1] < 0xc0)) { + off++; + table_entry = table_walk(table_entry, 0); + // table_entry kinds: INSTR(0) + goto direct; + } + + // VEX/EVEX + 66/F3/F2/REX will #UD. + // Note: REX is also here only respected if it immediately precedes the + // opcode, in this case the VEX/EVEX "prefix". + if (prefixes[PF_66] || prefixes[PF_REP] || prefix_rex) + return FD_ERR_UD; + + uint8_t byte = buffer[off + 1]; + if (vex_prefix == 0xc5) // 2-byte VEX + { + opcode_escape = 1; + prefix_rex = byte & 0x80 ? 0 : PREFIX_REXR; + } + else // 3-byte VEX or EVEX + { + // SDM Vol 2A 2-15 (Dec. 2016): Ignored in 32-bit mode + if (mode == DECODE_64) + prefix_rex = byte >> 5 ^ 0x7; + if (vex_prefix == 0x62) // EVEX + { + if (byte & 0x08) // Bit 3 of opcode_escape must be clear. + return FD_ERR_UD; + _Static_assert(PREFIX_REXRR == 0x10, "wrong REXRR value"); + if (mode == DECODE_64) + prefix_rex |= (byte & PREFIX_REXRR) ^ PREFIX_REXRR; + } + else // 3-byte VEX + { + if (byte & 0x18) // Bits 4:3 of opcode_escape must be clear. + return FD_ERR_UD; + } + + opcode_escape = (byte & 0x07); + if (UNLIKELY(opcode_escape == 0)) { + int prefix_len = vex_prefix == 0x62 ? 4 : 3; + // Pretend to decode the prefix plus one opcode byte. + return off + prefix_len > len ? FD_ERR_PARTIAL : FD_ERR_UD; + } + + // Load third byte of VEX prefix + if (UNLIKELY(off + 2 >= len)) + return FD_ERR_PARTIAL; + byte = buffer[off + 2]; + prefix_rex |= byte & 0x80 ? PREFIX_REXW : 0; + } + + mandatory_prefix = byte & 3; + vex_operand = ((byte & 0x78) >> 3) ^ 0xf; + prefix_rex |= PREFIX_VEX; + + if (vex_prefix == 0x62) // EVEX + { + if (!(byte & 0x04)) // Bit 10 must be 1. + return FD_ERR_UD; + if (UNLIKELY(off + 3 >= len)) + return FD_ERR_PARTIAL; + byte = buffer[off + 3]; + // prefix_evex is z:L'L/RC:b:V':aaa + vexl = (byte >> 5) & 3; + prefix_evex = byte | 0x100; // Ensure that prefix_evex is non-zero. + if (mode == DECODE_64) // V' causes UD in 32-bit mode + vex_operand |= byte & 0x08 ? 0 : 0x10; // V' + else if (!(byte & 0x08)) + return FD_ERR_UD; + off += 4; + } + else // VEX + { + vexl = byte & 0x04 ? 1 : 0; + off += 0xc7 - vex_prefix; // 3 for c4, 2 for c5 + } + } + + table_entry = table_walk(table_entry, opcode_escape); + // table_entry kinds: INSTR(0) [only for invalid], T256(2) + if (UNLIKELY(!table_entry)) + return FD_ERR_UD; + if (UNLIKELY(off >= len)) + return FD_ERR_PARTIAL; + table_entry = table_walk(table_entry, buffer[off++]); + // table_entry kinds: INSTR(0), T16(1), TVEX(2), TPREFIX(3) + + // Handle mandatory prefixes (which behave like an opcode ext.). + if ((table_entry & 3) == 3) + table_entry = table_walk(table_entry, mandatory_prefix); + // table_entry kinds: INSTR(0), T16(1), TVEX(2) + + // Then, walk through ModR/M-encoded opcode extensions. + if (table_entry & 1) { + if (UNLIKELY(off >= len)) + return FD_ERR_PARTIAL; + unsigned isreg = buffer[off] >= 0xc0; + table_entry = table_walk(table_entry, ((buffer[off] >> 2) & 0xe) | isreg); + // table_entry kinds: INSTR(0), T8E(1), TVEX(2) + if (table_entry & 1) + table_entry = table_walk(table_entry, buffer[off] & 7); + } + // table_entry kinds: INSTR(0), TVEX(2) + + // For VEX prefix, we have to distinguish between VEX.W and VEX.L which may + // be part of the opcode. + if (UNLIKELY(table_entry & 2)) + { + uint8_t index = 0; + index |= prefix_rex & PREFIX_REXW ? (1 << 0) : 0; + // When EVEX.L'L is the rounding mode, the instruction must not have + // L'L constraints. + index |= vexl << 1; + table_entry = table_walk(table_entry, index); + } + // table_entry kinds: INSTR(0) + +direct: + // table_entry kinds: INSTR(0) + if (UNLIKELY(!table_entry)) + return FD_ERR_UD; + + static _Alignas(16) const struct InstrDesc descs[] = { +#define FD_DECODE_TABLE_DESCS +#include +#undef FD_DECODE_TABLE_DESCS + }; + const struct InstrDesc* desc = &descs[table_entry >> 2]; + + instr->type = desc->type; + instr->addrsz = addr_size; + instr->flags = ((prefix_rep + 1) & 6) + (mode == DECODE_64 ? FD_FLAG_64 : 0); + instr->address = address; + + for (unsigned i = 0; i < sizeof(instr->operands) / sizeof(FdOp); i++) + instr->operands[i] = (FdOp) {0}; + + if (DESC_MODRM(desc) && UNLIKELY(off++ >= len)) + return FD_ERR_PARTIAL; + unsigned op_byte = buffer[off - 1] | (!DESC_MODRM(desc) ? 0xc0 : 0); + + if (UNLIKELY(prefix_evex)) { + // VSIB inst (gather/scatter) without mask register or w/EVEX.z is UD + if (DESC_VSIB(desc) && (!(prefix_evex & 0x07) || (prefix_evex & 0x80))) + return FD_ERR_UD; + // Inst doesn't support masking, so EVEX.z or EVEX.aaa is UD + if (!DESC_EVEX_MASK(desc) && (prefix_evex & 0x87)) + return FD_ERR_UD; + // EVEX.z without EVEX.aaa is UD. The Intel SDM is rather unprecise + // about this, but real hardware doesn't accept this. + if ((prefix_evex & 0x87) == 0x80) + return FD_ERR_UD; + + // Cases for SAE/RC (reg operands only): + // - ER supported -> all ok + // - SAE supported -> assume L'L is RC, but ignored (undocumented) + // - Neither supported -> b == 0 + if ((prefix_evex & 0x10) && (op_byte & 0xc0) == 0xc0) { // EVEX.b+reg + if (!DESC_EVEX_SAE(desc)) + return FD_ERR_UD; + vexl = 2; + if (DESC_EVEX_ER(desc)) + instr->evex = prefix_evex; + else + instr->evex = (prefix_evex & 0x87) | 0x60; // set RC, clear B + } else { + if (UNLIKELY(vexl == 3)) // EVEX.L'L == 11b is UD + return FD_ERR_UD; + instr->evex = prefix_evex & 0x87; // clear RC, clear B + } + + if (DESC_VSIB(desc)) + vex_operand &= 0xf; // EVEX.V' is used as index extension instead. + } else { + instr->evex = 0; + } + + unsigned op_size; + unsigned op_size_alt = 0; + if (!(DESC_OPSIZE(desc) & 4)) { + if (mode == DECODE_64) + op_size = ((prefix_rex & PREFIX_REXW) || DESC_OPSIZE(desc) == 3) ? 4 : + UNLIKELY(prefixes[PF_66] && !DESC_IGN66(desc)) ? 2 : + DESC_OPSIZE(desc) ? 4 : + 3; + else + op_size = UNLIKELY(prefixes[PF_66] && !DESC_IGN66(desc)) ? 2 : 3; + } else { + op_size = 5 + vexl; + op_size_alt = op_size - (DESC_OPSIZE(desc) & 3); + } + + uint8_t operand_sizes[4] = { + DESC_SIZE_FIX1(desc), DESC_SIZE_FIX2(desc) + 1, op_size, op_size_alt + }; + + if (UNLIKELY(instr->type == FDI_MOV_CR || instr->type == FDI_MOV_DR)) { + unsigned modreg = (op_byte >> 3) & 0x7; + unsigned modrm = op_byte & 0x7; + + FdOp* op_modreg = &instr->operands[DESC_MODREG_IDX(desc)]; + op_modreg->type = FD_OT_REG; + op_modreg->size = op_size; + op_modreg->reg = modreg | (prefix_rex & PREFIX_REXR ? 8 : 0); + op_modreg->misc = instr->type == FDI_MOV_CR ? FD_RT_CR : FD_RT_DR; + if (instr->type == FDI_MOV_CR && (~0x011d >> op_modreg->reg) & 1) + return FD_ERR_UD; + else if (instr->type == FDI_MOV_DR && prefix_rex & PREFIX_REXR) + return FD_ERR_UD; + + FdOp* op_modrm = &instr->operands[DESC_MODRM_IDX(desc)]; + op_modrm->type = FD_OT_REG; + op_modrm->size = op_size; + op_modrm->reg = modrm | (prefix_rex & PREFIX_REXB ? 8 : 0); + op_modrm->misc = FD_RT_GPL; + goto skip_modrm; + } + + if (DESC_HAS_MODREG(desc)) + { + FdOp* op_modreg = &instr->operands[DESC_MODREG_IDX(desc)]; + unsigned reg_idx = (op_byte & 0x38) >> 3; + unsigned reg_ty = DESC_REGTY_MODREG(desc); + op_modreg->misc = reg_ty; + if (LIKELY(reg_ty < 2)) + reg_idx += prefix_rex & PREFIX_REXR ? 8 : 0; + else if (reg_ty == 7 && (prefix_rex & PREFIX_REXR || prefix_evex & 0x80)) + return FD_ERR_UD; // REXR in 64-bit mode or EVEX.z with mask as dest + if (UNLIKELY(reg_ty == FD_RT_VEC)) // REXRR ignored above in 32-bit mode + reg_idx += prefix_rex & PREFIX_REXRR ? 16 : 0; + else if (UNLIKELY(prefix_rex & PREFIX_REXRR)) + return FD_ERR_UD; + op_modreg->type = FD_OT_REG; + op_modreg->size = operand_sizes[DESC_MODREG_SIZE(desc)]; + op_modreg->reg = reg_idx; + } + + if (DESC_HAS_MODRM(desc)) + { + FdOp* op_modrm = &instr->operands[DESC_MODRM_IDX(desc)]; + op_modrm->size = operand_sizes[DESC_MODRM_SIZE(desc)]; + + unsigned rm = op_byte & 0x07; + if (op_byte >= 0xc0) + { + uint8_t reg_idx = rm; + unsigned reg_ty = DESC_REGTY_MODRM(desc); + op_modrm->misc = reg_ty; + if (LIKELY(reg_ty < 2)) + reg_idx += prefix_rex & PREFIX_REXB ? 8 : 0; + if (prefix_evex && reg_ty == 0) // vector registers only + reg_idx += prefix_rex & PREFIX_REXX ? 16 : 0; + op_modrm->type = FD_OT_REG; + op_modrm->reg = reg_idx; + } + else + { + unsigned dispscale = 0; + + if (UNLIKELY(prefix_evex)) { + // EVEX.z for memory destination operand is UD. + if (UNLIKELY(prefix_evex & 0x80) && DESC_MODRM_IDX(desc) == 0) + return FD_ERR_UD; + + // EVEX.b for memory-operand without broadcast support is UD. + if (UNLIKELY(prefix_evex & 0x10)) { + if (UNLIKELY(!DESC_EVEX_BCST(desc))) + return FD_ERR_UD; + if (UNLIKELY(DESC_EVEX_BCST16(desc))) + dispscale = 1; + else + dispscale = prefix_rex & PREFIX_REXW ? 3 : 2; + instr->segment |= dispscale << 6; // Store broadcast size + op_modrm->type = FD_OT_MEMBCST; + } else { + dispscale = op_modrm->size - 1; + op_modrm->type = FD_OT_MEM; + } + } else { + op_modrm->type = FD_OT_MEM; + } + + // 16-bit address size implies different ModRM encoding + if (UNLIKELY(addr_size == 1)) { + ASSUME(mode == DECODE_32); + if (UNLIKELY(DESC_VSIB(desc))) // 16-bit addr size + VSIB is UD + return FD_ERR_UD; + if (rm < 6) + op_modrm->misc = rm & 1 ? FD_REG_DI : FD_REG_SI; + else + op_modrm->misc = FD_REG_NONE; + + if (rm < 4) + op_modrm->reg = rm & 2 ? FD_REG_BP : FD_REG_BX; + else if (rm < 6 || (op_byte & 0xc7) == 0x06) + op_modrm->reg = FD_REG_NONE; + else + op_modrm->reg = rm == 6 ? FD_REG_BP : FD_REG_BX; + + const uint8_t* dispbase = &buffer[off]; + if (op_byte & 0x40) { + if (UNLIKELY((off += 1) > len)) + return FD_ERR_PARTIAL; + instr->disp = (int8_t) LOAD_LE_1(dispbase) * (1 << dispscale); + } else if (op_byte & 0x80 || (op_byte & 0xc7) == 0x06) { + if (UNLIKELY((off += 2) > len)) + return FD_ERR_PARTIAL; + instr->disp = (int16_t) LOAD_LE_2(dispbase); + } else { + instr->disp = 0; + } + goto end_modrm; + } + + // SIB byte + uint8_t base = rm; + if (rm == 4) { + if (UNLIKELY(off >= len)) + return FD_ERR_PARTIAL; + uint8_t sib = buffer[off++]; + unsigned scale = sib & 0xc0; + unsigned idx = (sib & 0x38) >> 3; + idx += prefix_rex & PREFIX_REXX ? 8 : 0; + base = sib & 0x07; + if (idx == 4) + idx = FD_REG_NONE; + op_modrm->misc = scale | idx; + } else { + op_modrm->misc = FD_REG_NONE; + } + + if (UNLIKELY(DESC_VSIB(desc))) { + // VSIB must have a memory operand with SIB byte. + if (rm != 4) + return FD_ERR_UD; + _Static_assert(FD_REG_NONE == 0x3f, "unexpected FD_REG_NONE"); + // idx 4 is valid for VSIB + if ((op_modrm->misc & 0x3f) == FD_REG_NONE) + op_modrm->misc &= 0xc4; + if (prefix_evex) // EVEX.V':EVEX.X:SIB.idx + op_modrm->misc |= prefix_evex & 0x8 ? 0 : 0x10; + } + + // RIP-relative addressing only if SIB-byte is absent + if (op_byte < 0x40 && rm == 5 && mode == DECODE_64) + op_modrm->reg = FD_REG_IP; + else if (op_byte < 0x40 && base == 5) + op_modrm->reg = FD_REG_NONE; + else + op_modrm->reg = base + (prefix_rex & PREFIX_REXB ? 8 : 0); + + const uint8_t* dispbase = &buffer[off]; + if (op_byte & 0x40) { + if (UNLIKELY((off += 1) > len)) + return FD_ERR_PARTIAL; + instr->disp = (int8_t) LOAD_LE_1(dispbase) * (1 << dispscale); + } else if (op_byte & 0x80 || (op_byte < 0x40 && base == 5)) { + if (UNLIKELY((off += 4) > len)) + return FD_ERR_PARTIAL; + instr->disp = (int32_t) LOAD_LE_4(dispbase); + } else { + instr->disp = 0; + } + end_modrm:; + } + } + + if (UNLIKELY(DESC_HAS_VEXREG(desc))) + { + FdOp* operand = &instr->operands[DESC_VEXREG_IDX(desc)]; + if (DESC_ZEROREG_VAL(desc)) { + operand->type = FD_OT_REG; + operand->size = 1; + operand->reg = FD_REG_CL; + operand->misc = FD_RT_GPL; + } else { + operand->type = FD_OT_REG; + // Without VEX prefix, this encodes an implicit register + operand->size = operand_sizes[DESC_VEXREG_SIZE(desc)]; + if (mode == DECODE_32) + vex_operand &= 0x7; + // Note: 32-bit will never UD here. EVEX.V' is caught above already. + // Note: UD if > 16 for non-VEC. No EVEX-encoded instruction uses + // EVEX.vvvv to refer to non-vector registers. Verified in parseinstrs. + operand->reg = vex_operand; + + unsigned reg_ty = DESC_REGTY_VEXREG(desc); // VEC GPL MSK FPU/TMM + if (prefix_rex & PREFIX_VEX) { // TMM with VEX, FPU otherwise + // In 64-bit mode: UD if FD_RT_MASK and vex_operand&8 != 0 + if (reg_ty == 2 && vex_operand >= 8) + return FD_ERR_UD; + if (UNLIKELY(reg_ty == 3)) // TMM + operand->reg &= 0x7; // TODO: verify + operand->misc = (06710 >> (3 * reg_ty)) & 0x7; + } else { + operand->misc = (04710 >> (3 * reg_ty)) & 0x7; + } + } + } + else if (vex_operand != 0) + { + // TODO: bit 3 ignored in 32-bit mode? unverified + return FD_ERR_UD; + } + + uint32_t imm_control = UNLIKELY(DESC_IMM_CONTROL(desc)); + if (LIKELY(!imm_control)) { + } else if (UNLIKELY(imm_control == 1)) + { + // 1 = immediate constant 1, used for shifts + FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)]; + operand->type = FD_OT_IMM; + operand->size = 1; + instr->imm = 1; + } + else if (UNLIKELY(imm_control == 2)) + { + // 2 = memory, address-sized, used for mov with moffs operand + FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)]; + operand->type = FD_OT_MEM; + operand->size = operand_sizes[DESC_IMM_SIZE(desc)]; + operand->reg = FD_REG_NONE; + operand->misc = FD_REG_NONE; + + int moffsz = 1 << addr_size; + if (UNLIKELY(off + moffsz > len)) + return FD_ERR_PARTIAL; + if (moffsz == 2) + instr->disp = LOAD_LE_2(&buffer[off]); + if (moffsz == 4) + instr->disp = LOAD_LE_4(&buffer[off]); + if (LIKELY(moffsz == 8)) + instr->disp = LOAD_LE_8(&buffer[off]); + off += moffsz; + } + else if (UNLIKELY(imm_control == 3)) + { + // 3 = register in imm8[7:4], used for RVMR encoding with VBLENDVP[SD] + FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)]; + operand->type = FD_OT_REG; + operand->size = op_size; + operand->misc = FD_RT_VEC; + + if (UNLIKELY(off + 1 > len)) + return FD_ERR_PARTIAL; + uint8_t reg = (uint8_t) LOAD_LE_1(&buffer[off]); + off += 1; + + if (mode == DECODE_32) + reg &= 0x7f; + operand->reg = reg >> 4; + instr->imm = reg & 0x0f; + } + else if (imm_control != 0) + { + // 4/5 = immediate, operand-sized/8 bit + // 6/7 = offset, operand-sized/8 bit (used for jumps/calls) + int imm_byte = imm_control & 1; + int imm_offset = imm_control & 2; + + FdOp* operand = &instr->operands[DESC_IMM_IDX(desc)]; + operand->type = FD_OT_IMM; + + if (imm_byte) { + if (UNLIKELY(off + 1 > len)) + return FD_ERR_PARTIAL; + instr->imm = (int8_t) LOAD_LE_1(&buffer[off++]); + operand->size = DESC_IMM_SIZE(desc) & 1 ? 1 : op_size; + } else { + operand->size = operand_sizes[DESC_IMM_SIZE(desc)]; + + uint8_t imm_size; + if (UNLIKELY(instr->type == FDI_RET || instr->type == FDI_RETF || + instr->type == FDI_SSE_EXTRQ || + instr->type == FDI_SSE_INSERTQ)) + imm_size = 2; + else if (UNLIKELY(instr->type == FDI_JMPF || instr->type == FDI_CALLF)) + imm_size = (1 << op_size >> 1) + 2; + else if (UNLIKELY(instr->type == FDI_ENTER)) + imm_size = 3; + else if (instr->type == FDI_MOVABS) + imm_size = (1 << op_size >> 1); + else + imm_size = op_size == 2 ? 2 : 4; + + if (UNLIKELY(off + imm_size > len)) + return FD_ERR_PARTIAL; + + if (imm_size == 2) + instr->imm = (int16_t) LOAD_LE_2(&buffer[off]); + else if (imm_size == 3) + instr->imm = LOAD_LE_3(&buffer[off]); + else if (imm_size == 4) + instr->imm = (int32_t) LOAD_LE_4(&buffer[off]); + else if (imm_size == 6) + instr->imm = LOAD_LE_4(&buffer[off]) | LOAD_LE_2(&buffer[off+4]) << 32; + else if (imm_size == 8) + instr->imm = (int64_t) LOAD_LE_8(&buffer[off]); + off += imm_size; + } + + if (imm_offset) + { + if (instr->address != 0) + instr->imm += instr->address + off; + else + operand->type = FD_OT_OFF; + } + } + +skip_modrm: + if (UNLIKELY(prefixes[PF_LOCK])) { + if (!DESC_LOCK(desc) || instr->operands[0].type != FD_OT_MEM) + return FD_ERR_UD; + instr->flags |= FD_FLAG_LOCK; + } + + if (UNLIKELY(DESC_LEGACY(desc))) { + // Without REX prefix, convert one-byte GP regs to high-byte regs + // This actually only applies to SZ8/MOVSX/MOVZX; but no VEX-encoded + // instructions have a byte-sized GP register in the first two operands. + if (!(prefix_rex & PREFIX_REX)) { + for (int i = 0; i < 2; i++) { + FdOp* operand = &instr->operands[i]; + if (operand->type == FD_OT_NONE) + break; + if (operand->type == FD_OT_REG && operand->misc == FD_RT_GPL && + operand->size == 1 && operand->reg >= 4) + operand->misc = FD_RT_GPH; + } + } + + if (instr->type == FDI_XCHG_NOP) { + // Only 4890, 90, and 6690 are true NOPs. + if (instr->operands[0].reg == 0) { + instr->operands[0].type = FD_OT_NONE; + instr->operands[1].type = FD_OT_NONE; + instr->type = FD_HAS_REP(instr) ? FDI_PAUSE : FDI_NOP; + } else if ((instr->operands[0].reg & 7) == 0 && FD_HAS_REP(instr)) { + // On Intel, REX.B is ignored for F3.90. + instr->operands[0].type = FD_OT_NONE; + instr->operands[1].type = FD_OT_NONE; + instr->type = FDI_PAUSE; + } else { + instr->type = FDI_XCHG; + } + } + + if (UNLIKELY(instr->type == FDI_3DNOW)) { + unsigned opc3dn = instr->imm; + if (opc3dn & 0x40) + return FD_ERR_UD; + uint64_t msk = opc3dn & 0x80 ? 0x88d144d144d14400 : 0x30003000; + if (!(msk >> (opc3dn & 0x3f) & 1)) + return FD_ERR_UD; + } + + instr->operandsz = UNLIKELY(DESC_INSTR_WIDTH(desc)) ? op_size - 1 : 0; + } else { + instr->operandsz = 0; + } + + instr->size = off; + + return off; +} diff --git a/third_party/fadec/encode-test.c b/third_party/fadec/encode-test.c new file mode 100644 index 0000000..bc4a8d6 --- /dev/null +++ b/third_party/fadec/encode-test.c @@ -0,0 +1,62 @@ + +#include +#include +#include +#include + +#include + + +static +void +print_hex(const uint8_t* buf, size_t len) +{ + for (size_t i = 0; i < len; i++) + printf("%02x", buf[i]); +} + +static +int +test(uint8_t* buf, const char* name, uint64_t mnem, uint64_t op0, uint64_t op1, uint64_t op2, uint64_t op3, const void* exp, size_t exp_len) +{ + memset(buf, 0, 16); + + uint8_t* inst = buf; + int res = fe_enc64(&inst, mnem, op0, op1, op2, op3); + if ((res != 0) != (exp_len == 0)) goto fail; + if (inst - buf != (ptrdiff_t) exp_len) goto fail; + if (memcmp(buf, exp, exp_len)) goto fail; + + return 0; + +fail: + printf("Failed case %s:\n", name); + printf(" Exp (%2zu): ", exp_len); + print_hex(exp, exp_len); + printf("\n Got (%2zd): ", inst - buf); + print_hex(buf, inst - buf); + printf("\n"); + return -1; +} + +#define TEST2(str, exp, exp_len, mnem, flags, op0, op1, op2, op3, ...) test(buf, str, FE_ ## mnem|flags, op0, op1, op2, op3, exp, exp_len) +#define TEST1(str, exp, ...) TEST2(str, exp, sizeof(exp)-1, __VA_ARGS__, 0, 0, 0, 0, 0) +#define TEST(exp, ...) failed |= TEST1(#__VA_ARGS__, exp, __VA_ARGS__) + +int +main(int argc, char** argv) +{ + (void) argc; (void) argv; + + int failed = 0; + uint8_t buf[16]; + + // VSIB encoding doesn't differ for this API +#define FE_MEMV FE_MEM +#define FE_PTR(off) ((intptr_t) buf + (off)) +#define FLAGMASK(flags, mask) (flags | FE_MASK(mask & 7)) +#include "encode-test.inc" + + puts(failed ? "Some tests FAILED" : "All tests PASSED"); + return failed ? EXIT_FAILURE : EXIT_SUCCESS; +} diff --git a/third_party/fadec/encode-test.inc b/third_party/fadec/encode-test.inc new file mode 100644 index 0000000..d1d400c --- /dev/null +++ b/third_party/fadec/encode-test.inc @@ -0,0 +1,2192 @@ + +TEST("\00\xe0", ADD8rr, 0, FE_AX, FE_AH); +TEST("", ADD8rr, 0, FE_SI, FE_AH); +TEST("\xeb\xfe", JMP, 0, FE_PTR(0)); +TEST("\xeb\x7f", JMP, 0, FE_PTR(129)); +TEST("\xe9\x7d\x00\x00\x00", JMP, 0, FE_PTR(130)); +TEST("\xeb\x80", JMP, 0, FE_PTR(-126)); +TEST("\xe9\x7c\xff\xff\xff", JMP, 0, FE_PTR(-127)); +TEST("\xe9\xfb\xff\xff\xff", JMP, FE_JMPL, FE_PTR(0)); +TEST("\xe9\x00\x00\x00\x00", JMP, FE_JMPL, FE_PTR(5)); +TEST("\x75\x00", JNZ, 0, FE_PTR(2)); +TEST("\x0f\x85\x00\x00\x00\x00", JNZ, FE_JMPL, FE_PTR(6)); +TEST("\x70\x7f", JO, 0, FE_PTR(129)); +TEST("\x0f\x80\x7c\x00\x00\x00", JO, 0, FE_PTR(130)); +TEST("\x70\x80", JO, 0, FE_PTR(-126)); +TEST("\x0f\x80\x7b\xff\xff\xff", JO, 0, FE_PTR(-127)); +TEST("\xe3\xfc", JCXZ, 0, FE_PTR(-2)); +TEST("\x67\xe3\xfb", JCXZ, FE_ADDR32, FE_PTR(-2)); +TEST("\xe3\xfc", JCXZ, FE_JMPL, FE_PTR(-2)); +TEST("\xac", LODS8, 0); +TEST("\x67\xac", LODS8, FE_ADDR32); +TEST("\x50", PUSHr, 0, FE_AX); +TEST("\x66\x50", PUSH16r, 0, FE_AX); +TEST("\x54", PUSHr, 0, FE_SP); +TEST("\x41\x57", PUSHr, 0, FE_R15); +TEST("\x41\x50", PUSHr, 0, FE_R8); +TEST("", PUSH_SEGr, 0, FE_ES); +TEST("", PUSH_SEG16r, 0, FE_ES); +TEST("", PUSH_SEGr, 0, FE_CS); +TEST("", PUSH_SEG16r, 0, FE_CS); +TEST("", PUSH_SEGr, 0, FE_SS); +TEST("", PUSH_SEG16r, 0, FE_SS); +TEST("", PUSH_SEGr, 0, FE_DS); +TEST("", PUSH_SEG16r, 0, FE_DS); +TEST("\x0f\xa0", PUSH_SEGr, 0, FE_FS); +TEST("\x66\x0f\xa0", PUSH_SEG16r, 0, FE_FS); +TEST("\x0f\xa8", PUSH_SEGr, 0, FE_GS); +TEST("\x66\x0f\xa8", PUSH_SEG16r, 0, FE_GS); +TEST("\xff\x30", PUSHm, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xff\x31", PUSHm, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0)); +TEST("\x9c", PUSHF, 0); +TEST("\x8c\xc0", MOV_S2Grr, 0, FE_AX, FE_ES); +TEST("\x8c\xc8", MOV_S2Grr, 0, FE_AX, FE_CS); +TEST("\x8c\xd0", MOV_S2Grr, 0, FE_AX, FE_SS); +TEST("\x8c\xd8", MOV_S2Grr, 0, FE_AX, FE_DS); +TEST("\x8c\xe0", MOV_S2Grr, 0, FE_AX, FE_FS); +TEST("\x8c\xe8", MOV_S2Grr, 0, FE_AX, FE_GS); +TEST("\x8e\xc0", MOV_G2Srr, 0, FE_ES, FE_AX); +// TEST("", MOV_G2Srr, 0, FE_CS, FE_AX); +TEST("\x8e\xd0", MOV_G2Srr, 0, FE_SS, FE_AX); +TEST("\x8e\xd8", MOV_G2Srr, 0, FE_DS, FE_AX); +TEST("\x8e\xe0", MOV_G2Srr, 0, FE_FS, FE_AX); +TEST("\x8e\xe8", MOV_G2Srr, 0, FE_GS, FE_AX); +TEST("\xd2\xe4", SHL8rr, 0, FE_AH, FE_CX); +TEST("", SHL8rr, 0, FE_AH, FE_DX); +TEST("\xd0\xe0", SHL8ri, 0, FE_AX, 1); +TEST("\xc0\xe0\x02", SHL8ri, 0, FE_AX, 2); +TEST("\xc1\xe0\x02", SHL32ri, 0, FE_AX, 2); +TEST("\x48\xc1\xe0\x02", SHL64ri, 0, FE_AX, 2); +TEST("\x48\xf7\x28", IMUL64m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc2\x00\x00", RETi, 0, 0); +TEST("\xff\xd0", CALLr, 0, FE_AX); +TEST("\x83\xc0\x7f", ADD32ri, 0, FE_AX, 0x7f); +TEST("\x05\x80\x00\x00\x00", ADD32ri, 0, FE_AX, 0x80); +TEST("\x05\x00\x01\x00\x00", ADD32ri, 0, FE_AX, 0x100); +TEST("\x66\x05\x00\x01", ADD16ri, 0, FE_AX, 0x100); +#ifndef ENC_TEST_TYPESAFE +TEST("", ADD16ri, 0, FE_AX, 0x12345); +TEST("\x66\x05\xff\xee", ADD16ri, 0, FE_AX, 0xffffffffffffeeff); +#endif +TEST("\xb8\x05\x00\x01\x00", MOV32ri, 0, FE_AX, 0x10005); +TEST("\xb8\xff\xff\xff\x7f", MOV32ri, 0, FE_AX, 0x7fffffff); +TEST("\x48\xb8\x05\x00\x01\x00\xff\x00\x00\x00", MOV64ri, 0, FE_AX, 0xff00010005); +TEST("\x48\xc7\xc0\x00\x00\x00\x00", MOV64ri, 0, FE_AX, 0x0); +TEST("\x48\xc7\xc0\x00\x00\x00\x80", MOV64ri, 0, FE_AX, (int32_t) 0x80000000); +TEST("\x48\xb8\x00\x00\x00\x00\x00\x00\x00\x80", MOV64ri, 0, FE_AX, INT64_MIN); +TEST("\x48\xb8\x00\x00\x00\x80\x00\x00\x00\x00", MOV64ri, 0, FE_AX, 0x80000000); +TEST("\xb0\xff", MOV8ri, 0, FE_AX, (int8_t) 0xff); +TEST("\xb4\xff", MOV8ri, 0, FE_AH, -1); +TEST("\xb7\x64", MOV8ri, 0, FE_BH, 0x64); +TEST("\x40\xb6\x64", MOV8ri, 0, FE_SI, 0x64); +TEST("\x41\xb6\x64", MOV8ri, 0, FE_R14, 0x64); +TEST("\x66\x0f\xbe\xc2", MOVSXr16r8, 0, FE_AX, FE_DX); +TEST("\x0f\xbe\xc2", MOVSXr32r8, 0, FE_AX, FE_DX); +TEST("\x48\x0f\xbe\xc2", MOVSXr64r8, 0, FE_AX, FE_DX); +TEST("\x66\x0f\xbe\xc6", MOVSXr16r8, 0, FE_AX, FE_DH); +TEST("\x0f\xbe\xc6", MOVSXr32r8, 0, FE_AX, FE_DH); +TEST("", MOVSXr64r8, 0, FE_AX, FE_DH); +TEST("\x66\x0f\xbf\xc2", MOVSXr16r16, 0, FE_AX, FE_DX); +TEST("\x0f\xbf\xc2", MOVSXr32r16, 0, FE_AX, FE_DX); +TEST("\x48\x0f\xbf\xc2", MOVSXr64r16, 0, FE_AX, FE_DX); +TEST("\x66\x63\xc2", MOVSXr16r32, 0, FE_AX, FE_DX); +TEST("\x63\xc2", MOVSXr32r32, 0, FE_AX, FE_DX); +TEST("\x48\x63\xc2", MOVSXr64r32, 0, FE_AX, FE_DX); +TEST("\xc8\x33\x22\x11", ENTERi, 0, 0x112233); +TEST("", ENTERi, 0, 0x1112233); +TEST("\x0f\x05", SYSCALL, 0); +TEST("\x0f\x90\xc4", SETO8r, 0, FE_AH); +TEST("\x40\x0f\x90\xc4", SETO8r, 0, FE_SP); +TEST("\x41\x0f\x90\xc4", SETO8r, 0, FE_R12); +TEST("\xf3\x0f\xb8\xc2", POPCNT32rr, 0, FE_AX, FE_DX); +TEST("\x66\xf3\x0f\xb8\xc2", POPCNT16rr, 0, FE_AX, FE_DX); +TEST("\xf3\x48\x0f\xb8\xc2", POPCNT64rr, 0, FE_AX, FE_DX); +TEST("\x0f\xbc\xc2", BSF32rr, 0, FE_AX, FE_DX); +TEST("\x66\x0f\xbc\xc2", BSF16rr, 0, FE_AX, FE_DX); +TEST("\x0f\x01\xd0", XGETBV, 0); +TEST("\x41\x90", XCHG32rr, 0, FE_R8, FE_AX); +TEST("\x91", XCHG32rr, 0, FE_CX, FE_AX); +TEST("\x66\x90", XCHG16rr, 0, FE_AX, FE_AX); +TEST("\x87\xc0", XCHG32rr, 0, FE_AX, FE_AX); +TEST("\x48\x90", XCHG64rr, 0, FE_AX, FE_AX); +TEST("\x87\x00", XCHG32mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); +TEST("\x87\x08", XCHG32mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX); +TEST("\x90", NOP, 0); +TEST("\xf3\x90", PAUSE, 0); +TEST("\x0f\x1f\xc0", NOP32r, 0, FE_AX); +TEST("\x26\x01\x00", ADD32mr, FE_SEG(FE_ES), FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); +TEST("\x2e\x01\x00", ADD32mr, FE_SEG(FE_CS), FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); +TEST("\x36\x01\x00", ADD32mr, FE_SEG(FE_SS), FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); +TEST("\x3e\x01\x00", ADD32mr, FE_SEG(FE_DS), FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); +TEST("\x64\x01\x00", ADD32mr, FE_SEG(FE_FS), FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); +TEST("\x65\x01\x00", ADD32mr, FE_SEG(FE_GS), FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); +TEST("\x8e\xc0", MOV_G2Srr, 0, FE_ES, FE_AX); +TEST("\xae", SCAS8, 0); +TEST("\xf2\xae", REPNZ_SCAS8, 0); +TEST("\xf3\xae", REPZ_SCAS8, 0); +TEST("\x66\xab", STOS16, 0); +TEST("\x66\xf3\xab", REP_STOS16, 0); +TEST("\xab", STOS32, 0); +TEST("\xf3\xab", REP_STOS32, 0); +TEST("\x48\xab", STOS64, 0); +TEST("\xf3\x48\xab", REP_STOS64, 0); +TEST("\x6c", INS8, 0); +TEST("\x67\x6c", INS8, FE_ADDR32); +TEST("\x66\x6d", INS16, 0); +TEST("\x67\x66\x6d", INS16, FE_ADDR32); +TEST("\x6d", INS32, 0); +TEST("\x67\x6d", INS32, FE_ADDR32); +TEST("\x0f\x38\xf0\x11", MOVBE32rm, 0, FE_DX, FE_MEM(FE_CX, 0, FE_NOREG, 0)); +TEST("\x66\x0f\x38\xf0\x11", MOVBE16rm, 0, FE_DX, FE_MEM(FE_CX, 0, FE_NOREG, 0)); +TEST("\x48\x0f\x38\xf0\x11", MOVBE64rm, 0, FE_DX, FE_MEM(FE_CX, 0, FE_NOREG, 0)); +TEST("\xf2\x0f\x38\xf0\xc1", CRC32_8rr, 0, FE_AX, FE_CX); +TEST("\xf2\x0f\x38\xf0\xc5", CRC32_8rr, 0, FE_AX, FE_CH); +TEST("\xf2\x0f\x38\xf1\xc1", CRC32_32rr, 0, FE_AX, FE_CX); +TEST("\x66\xf2\x0f\x38\xf1\xc1", CRC32_16rr, 0, FE_AX, FE_CX); +TEST("\x66\xf2\x41\x0f\x38\xf1\xc2", CRC32_16rr, 0, FE_AX, FE_R10); +TEST("\x0f\xc7\xf7", RDRAND32r, 0, FE_DI); +TEST("\x66\x0f\xc7\xf7", RDRAND16r, 0, FE_DI); +TEST("\x48\x0f\xc7\xf7", RDRAND64r, 0, FE_DI); +TEST("\x0f\xc7\xff", RDSEED32r, 0, FE_DI); +TEST("\x66\x0f\xc7\xff", RDSEED16r, 0, FE_DI); +TEST("\x48\x0f\xc7\xff", RDSEED64r, 0, FE_DI); +TEST("\xf3\x0f\xc7\xff", RDPIDr, 0, FE_DI); +TEST("\x66\x0f\x3a\x14\xc1\x02", SSE_PEXTRBrri, 0, FE_CX, FE_XMM0, 2); +TEST("\x66\x0f\x3a\x20\xc1\x02", SSE_PINSRBrri, 0, FE_XMM0, FE_CX, 2); +#ifndef ENC_TEST_TYPESAFE +TEST("", SSE_PEXTRBrri, 0, FE_CH, FE_XMM0, 2); +TEST("", SSE_PINSRBrri, 0, FE_XMM0, FE_CH, 2); +#endif +TEST("\x66\x0f\xf7\xc1", SSE_MASKMOVDQUrr, 0, FE_XMM0, FE_XMM1); +TEST("\x67\x66\x0f\xf7\xc1", SSE_MASKMOVDQUrr, FE_ADDR32, FE_XMM0, FE_XMM1); +TEST("\x66\x0f\x6e\xc1", SSE_MOVD_G2Xrr, 0, FE_XMM0, FE_CX); +TEST("\x66\x41\x0f\x6e\xc1", SSE_MOVD_G2Xrr, 0, FE_XMM0, FE_R9); +TEST("\x66\x44\x0f\x6e\xc1", SSE_MOVD_G2Xrr, 0, FE_XMM8, FE_CX); +TEST("\x66\x45\x0f\x6e\xc1", SSE_MOVD_G2Xrr, 0, FE_XMM8, FE_R9); +TEST("\x66\x48\x0f\x6e\xc1", SSE_MOVQ_G2Xrr, 0, FE_XMM0, FE_CX); +TEST("\x66\x49\x0f\x6e\xc1", SSE_MOVQ_G2Xrr, 0, FE_XMM0, FE_R9); +TEST("\x66\x4c\x0f\x6e\xc1", SSE_MOVQ_G2Xrr, 0, FE_XMM8, FE_CX); +TEST("\x66\x4d\x0f\x6e\xc1", SSE_MOVQ_G2Xrr, 0, FE_XMM8, FE_R9); +TEST("\x66\x0f\x7e\xc1", SSE_MOVD_X2Grr, 0, FE_CX, FE_XMM0); +TEST("\x66\x41\x0f\x7e\xc1", SSE_MOVD_X2Grr, 0, FE_R9, FE_XMM0); +TEST("\x66\x44\x0f\x7e\xc1", SSE_MOVD_X2Grr, 0, FE_CX, FE_XMM8); +TEST("\x66\x45\x0f\x7e\xc1", SSE_MOVD_X2Grr, 0, FE_R9, FE_XMM8); +TEST("\x66\x48\x0f\x7e\xc1", SSE_MOVQ_X2Grr, 0, FE_CX, FE_XMM0); +TEST("\x66\x49\x0f\x7e\xc1", SSE_MOVQ_X2Grr, 0, FE_R9, FE_XMM0); +TEST("\x66\x4c\x0f\x7e\xc1", SSE_MOVQ_X2Grr, 0, FE_CX, FE_XMM8); +TEST("\x66\x4d\x0f\x7e\xc1", SSE_MOVQ_X2Grr, 0, FE_R9, FE_XMM8); +TEST("\x0f\xae\xe8", LFENCE, 0); +TEST("\x0f\xae\xf0", MFENCE, 0); +TEST("\x0f\xae\xf8", SFENCE, 0); +TEST("\x66\x98", C_EX16, 0); +TEST("\x66\x98", CBW, 0); +TEST("\x98", C_EX32, 0); +TEST("\x98", CWDE, 0); +TEST("\x48\x98", C_EX64, 0); +TEST("\x48\x98", CDQE, 0); +TEST("\x66\x99", C_SEP16, 0); +TEST("\x66\x99", CWD, 0); +TEST("\x99", C_SEP32, 0); +TEST("\x99", CDQ, 0); +TEST("\x48\x99", C_SEP64, 0); +TEST("\x48\x99", CQO, 0); +TEST("\x0f\xc7\x0f", CMPXCHGD32m, 0, FE_MEM(FE_DI, 0, FE_NOREG, 0)); +TEST("\x0f\xc7\x0f", CMPXCHG8Bm, 0, FE_MEM(FE_DI, 0, FE_NOREG, 0)); +TEST("\x48\x0f\xc7\x0f", CMPXCHGD64m, 0, FE_MEM(FE_DI, 0, FE_NOREG, 0)); +TEST("\x48\x0f\xc7\x0f", CMPXCHG16Bm, 0, FE_MEM(FE_DI, 0, FE_NOREG, 0)); + +// Condition codes +TEST("\x70\x00", JO, 0, FE_PTR(2)); +TEST("\x70\x00", Jcc, FE_CC_O, FE_PTR(2)); +TEST("\x0f\x80\x00\x00\x00\x00", JO, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x80\x00\x00\x00\x00", Jcc, FE_CC_O|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x80\x7c\x00\x00\x00", JO, 0, FE_PTR(130)); +TEST("\x0f\x80\x7c\x00\x00\x00", Jcc, FE_CC_O, FE_PTR(130)); +TEST("\x0f\x90\xc0", SETO8r, 0, FE_AX); +TEST("\x0f\x90\xc0", SETcc8r, FE_CC_O, FE_AX); +TEST("\x0f\x90\x00", SETO8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x90\x00", SETcc8m, FE_CC_O, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x90\x00", SETO8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x90\x00", SETcc8m, FE_CC_O|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x40\xc0", CMOVO32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x40\xc0", CMOVcc32rr, FE_CC_O, FE_AX, FE_AX); +TEST("\x0f\x40\x00", CMOVO32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x40\x00", CMOVcc32rm, FE_CC_O, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x40\x00", CMOVO32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x40\x00", CMOVcc32rm, FE_CC_O|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe0\x08", CMPOXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe0\x08", CMPccXADD32mrr, FE_CC_O, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe0\x08", CMPOXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe0\x08", CMPccXADD64mrr, FE_CC_O, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x71\x00", JNO, 0, FE_PTR(2)); +TEST("\x71\x00", Jcc, FE_CC_NO, FE_PTR(2)); +TEST("\x0f\x81\x00\x00\x00\x00", JNO, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x81\x00\x00\x00\x00", Jcc, FE_CC_NO|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x81\x7c\x00\x00\x00", JNO, 0, FE_PTR(130)); +TEST("\x0f\x81\x7c\x00\x00\x00", Jcc, FE_CC_NO, FE_PTR(130)); +TEST("\x0f\x91\xc0", SETNO8r, 0, FE_AX); +TEST("\x0f\x91\xc0", SETcc8r, FE_CC_NO, FE_AX); +TEST("\x0f\x91\x00", SETNO8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x91\x00", SETcc8m, FE_CC_NO, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x91\x00", SETNO8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x91\x00", SETcc8m, FE_CC_NO|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x41\xc0", CMOVNO32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x41\xc0", CMOVcc32rr, FE_CC_NO, FE_AX, FE_AX); +TEST("\x0f\x41\x00", CMOVNO32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x41\x00", CMOVcc32rm, FE_CC_NO, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x41\x00", CMOVNO32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x41\x00", CMOVcc32rm, FE_CC_NO|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe1\x08", CMPNOXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe1\x08", CMPccXADD32mrr, FE_CC_NO, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe1\x08", CMPNOXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe1\x08", CMPccXADD64mrr, FE_CC_NO, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x72\x00", JC, 0, FE_PTR(2)); +TEST("\x72\x00", Jcc, FE_CC_C, FE_PTR(2)); +TEST("\x0f\x82\x00\x00\x00\x00", JC, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x82\x00\x00\x00\x00", Jcc, FE_CC_C|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x82\x7c\x00\x00\x00", JC, 0, FE_PTR(130)); +TEST("\x0f\x82\x7c\x00\x00\x00", Jcc, FE_CC_C, FE_PTR(130)); +TEST("\x0f\x92\xc0", SETC8r, 0, FE_AX); +TEST("\x0f\x92\xc0", SETcc8r, FE_CC_C, FE_AX); +TEST("\x0f\x92\x00", SETC8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x92\x00", SETcc8m, FE_CC_C, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x92\x00", SETC8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x92\x00", SETcc8m, FE_CC_C|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x42\xc0", CMOVC32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x42\xc0", CMOVcc32rr, FE_CC_C, FE_AX, FE_AX); +TEST("\x0f\x42\x00", CMOVC32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x42\x00", CMOVcc32rm, FE_CC_C, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x42\x00", CMOVC32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x42\x00", CMOVcc32rm, FE_CC_C|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe2\x08", CMPBXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe2\x08", CMPccXADD32mrr, FE_CC_B, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe2\x08", CMPBXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe2\x08", CMPccXADD64mrr, FE_CC_B, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x73\x00", JNC, 0, FE_PTR(2)); +TEST("\x73\x00", Jcc, FE_CC_NC, FE_PTR(2)); +TEST("\x0f\x83\x00\x00\x00\x00", JNC, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x83\x00\x00\x00\x00", Jcc, FE_CC_NC|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x83\x7c\x00\x00\x00", JNC, 0, FE_PTR(130)); +TEST("\x0f\x83\x7c\x00\x00\x00", Jcc, FE_CC_NC, FE_PTR(130)); +TEST("\x0f\x93\xc0", SETNC8r, 0, FE_AX); +TEST("\x0f\x93\xc0", SETcc8r, FE_CC_NC, FE_AX); +TEST("\x0f\x93\x00", SETNC8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x93\x00", SETcc8m, FE_CC_NC, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x93\x00", SETNC8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x93\x00", SETcc8m, FE_CC_NC|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x43\xc0", CMOVNC32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x43\xc0", CMOVcc32rr, FE_CC_NC, FE_AX, FE_AX); +TEST("\x0f\x43\x00", CMOVNC32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x43\x00", CMOVcc32rm, FE_CC_NC, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x43\x00", CMOVNC32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x43\x00", CMOVcc32rm, FE_CC_NC|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe3\x08", CMPNBXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe3\x08", CMPccXADD32mrr, FE_CC_NB, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe3\x08", CMPNBXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe3\x08", CMPccXADD64mrr, FE_CC_NB, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x74\x00", JZ, 0, FE_PTR(2)); +TEST("\x74\x00", Jcc, FE_CC_Z, FE_PTR(2)); +TEST("\x0f\x84\x00\x00\x00\x00", JZ, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x84\x00\x00\x00\x00", Jcc, FE_CC_Z|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x84\x7c\x00\x00\x00", JZ, 0, FE_PTR(130)); +TEST("\x0f\x84\x7c\x00\x00\x00", Jcc, FE_CC_Z, FE_PTR(130)); +TEST("\x0f\x94\xc0", SETZ8r, 0, FE_AX); +TEST("\x0f\x94\xc0", SETcc8r, FE_CC_Z, FE_AX); +TEST("\x0f\x94\x00", SETZ8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x94\x00", SETcc8m, FE_CC_Z, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x94\x00", SETZ8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x94\x00", SETcc8m, FE_CC_Z|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x44\xc0", CMOVZ32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x44\xc0", CMOVcc32rr, FE_CC_Z, FE_AX, FE_AX); +TEST("\x0f\x44\x00", CMOVZ32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x44\x00", CMOVcc32rm, FE_CC_Z, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x44\x00", CMOVZ32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x44\x00", CMOVcc32rm, FE_CC_Z|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe4\x08", CMPZXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe4\x08", CMPccXADD32mrr, FE_CC_Z, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe4\x08", CMPZXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe4\x08", CMPccXADD64mrr, FE_CC_Z, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x75\x00", JNZ, 0, FE_PTR(2)); +TEST("\x75\x00", Jcc, FE_CC_NZ, FE_PTR(2)); +TEST("\x0f\x85\x00\x00\x00\x00", JNZ, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x85\x00\x00\x00\x00", Jcc, FE_CC_NZ|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x85\x7c\x00\x00\x00", JNZ, 0, FE_PTR(130)); +TEST("\x0f\x85\x7c\x00\x00\x00", Jcc, FE_CC_NZ, FE_PTR(130)); +TEST("\x0f\x95\xc0", SETNZ8r, 0, FE_AX); +TEST("\x0f\x95\xc0", SETcc8r, FE_CC_NZ, FE_AX); +TEST("\x0f\x95\x00", SETNZ8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x95\x00", SETcc8m, FE_CC_NZ, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x95\x00", SETNZ8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x95\x00", SETcc8m, FE_CC_NZ|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x45\xc0", CMOVNZ32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x45\xc0", CMOVcc32rr, FE_CC_NZ, FE_AX, FE_AX); +TEST("\x0f\x45\x00", CMOVNZ32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x45\x00", CMOVcc32rm, FE_CC_NZ, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x45\x00", CMOVNZ32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x45\x00", CMOVcc32rm, FE_CC_NZ|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe5\x08", CMPNZXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe5\x08", CMPccXADD32mrr, FE_CC_NZ, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe5\x08", CMPNZXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe5\x08", CMPccXADD64mrr, FE_CC_NZ, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x76\x00", JBE, 0, FE_PTR(2)); +TEST("\x76\x00", Jcc, FE_CC_BE, FE_PTR(2)); +TEST("\x0f\x86\x00\x00\x00\x00", JBE, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x86\x00\x00\x00\x00", Jcc, FE_CC_BE|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x86\x7c\x00\x00\x00", JBE, 0, FE_PTR(130)); +TEST("\x0f\x86\x7c\x00\x00\x00", Jcc, FE_CC_BE, FE_PTR(130)); +TEST("\x0f\x96\xc0", SETBE8r, 0, FE_AX); +TEST("\x0f\x96\xc0", SETcc8r, FE_CC_BE, FE_AX); +TEST("\x0f\x96\x00", SETBE8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x96\x00", SETcc8m, FE_CC_BE, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x96\x00", SETBE8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x96\x00", SETcc8m, FE_CC_BE|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x46\xc0", CMOVBE32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x46\xc0", CMOVcc32rr, FE_CC_BE, FE_AX, FE_AX); +TEST("\x0f\x46\x00", CMOVBE32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x46\x00", CMOVcc32rm, FE_CC_BE, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x46\x00", CMOVBE32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x46\x00", CMOVcc32rm, FE_CC_BE|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe6\x08", CMPBEXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe6\x08", CMPccXADD32mrr, FE_CC_BE, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe6\x08", CMPBEXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe6\x08", CMPccXADD64mrr, FE_CC_BE, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x77\x00", JA, 0, FE_PTR(2)); +TEST("\x77\x00", Jcc, FE_CC_A, FE_PTR(2)); +TEST("\x0f\x87\x00\x00\x00\x00", JA, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x87\x00\x00\x00\x00", Jcc, FE_CC_A|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x87\x7c\x00\x00\x00", JA, 0, FE_PTR(130)); +TEST("\x0f\x87\x7c\x00\x00\x00", Jcc, FE_CC_A, FE_PTR(130)); +TEST("\x0f\x97\xc0", SETA8r, 0, FE_AX); +TEST("\x0f\x97\xc0", SETcc8r, FE_CC_A, FE_AX); +TEST("\x0f\x97\x00", SETA8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x97\x00", SETcc8m, FE_CC_A, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x97\x00", SETA8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x97\x00", SETcc8m, FE_CC_A|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x47\xc0", CMOVA32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x47\xc0", CMOVcc32rr, FE_CC_A, FE_AX, FE_AX); +TEST("\x0f\x47\x00", CMOVA32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x47\x00", CMOVcc32rm, FE_CC_A, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x47\x00", CMOVA32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x47\x00", CMOVcc32rm, FE_CC_A|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe7\x08", CMPNBEXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe7\x08", CMPccXADD32mrr, FE_CC_NBE, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe7\x08", CMPNBEXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe7\x08", CMPccXADD64mrr, FE_CC_NBE, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x78\x00", JS, 0, FE_PTR(2)); +TEST("\x78\x00", Jcc, FE_CC_S, FE_PTR(2)); +TEST("\x0f\x88\x00\x00\x00\x00", JS, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x88\x00\x00\x00\x00", Jcc, FE_CC_S|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x88\x7c\x00\x00\x00", JS, 0, FE_PTR(130)); +TEST("\x0f\x88\x7c\x00\x00\x00", Jcc, FE_CC_S, FE_PTR(130)); +TEST("\x0f\x98\xc0", SETS8r, 0, FE_AX); +TEST("\x0f\x98\xc0", SETcc8r, FE_CC_S, FE_AX); +TEST("\x0f\x98\x00", SETS8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x98\x00", SETcc8m, FE_CC_S, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x98\x00", SETS8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x98\x00", SETcc8m, FE_CC_S|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x48\xc0", CMOVS32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x48\xc0", CMOVcc32rr, FE_CC_S, FE_AX, FE_AX); +TEST("\x0f\x48\x00", CMOVS32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x48\x00", CMOVcc32rm, FE_CC_S, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x48\x00", CMOVS32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x48\x00", CMOVcc32rm, FE_CC_S|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe8\x08", CMPSXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe8\x08", CMPccXADD32mrr, FE_CC_S, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe8\x08", CMPSXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe8\x08", CMPccXADD64mrr, FE_CC_S, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x79\x00", JNS, 0, FE_PTR(2)); +TEST("\x79\x00", Jcc, FE_CC_NS, FE_PTR(2)); +TEST("\x0f\x89\x00\x00\x00\x00", JNS, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x89\x00\x00\x00\x00", Jcc, FE_CC_NS|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x89\x7c\x00\x00\x00", JNS, 0, FE_PTR(130)); +TEST("\x0f\x89\x7c\x00\x00\x00", Jcc, FE_CC_NS, FE_PTR(130)); +TEST("\x0f\x99\xc0", SETNS8r, 0, FE_AX); +TEST("\x0f\x99\xc0", SETcc8r, FE_CC_NS, FE_AX); +TEST("\x0f\x99\x00", SETNS8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x99\x00", SETcc8m, FE_CC_NS, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x99\x00", SETNS8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x99\x00", SETcc8m, FE_CC_NS|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x49\xc0", CMOVNS32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x49\xc0", CMOVcc32rr, FE_CC_NS, FE_AX, FE_AX); +TEST("\x0f\x49\x00", CMOVNS32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x49\x00", CMOVcc32rm, FE_CC_NS, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x49\x00", CMOVNS32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x49\x00", CMOVcc32rm, FE_CC_NS|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xe9\x08", CMPNSXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xe9\x08", CMPccXADD32mrr, FE_CC_NS, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe9\x08", CMPNSXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xe9\x08", CMPccXADD64mrr, FE_CC_NS, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x7a\x00", JP, 0, FE_PTR(2)); +TEST("\x7a\x00", Jcc, FE_CC_P, FE_PTR(2)); +TEST("\x0f\x8a\x00\x00\x00\x00", JP, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8a\x00\x00\x00\x00", Jcc, FE_CC_P|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8a\x7c\x00\x00\x00", JP, 0, FE_PTR(130)); +TEST("\x0f\x8a\x7c\x00\x00\x00", Jcc, FE_CC_P, FE_PTR(130)); +TEST("\x0f\x9a\xc0", SETP8r, 0, FE_AX); +TEST("\x0f\x9a\xc0", SETcc8r, FE_CC_P, FE_AX); +TEST("\x0f\x9a\x00", SETP8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x9a\x00", SETcc8m, FE_CC_P, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9a\x00", SETP8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9a\x00", SETcc8m, FE_CC_P|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4a\xc0", CMOVP32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x4a\xc0", CMOVcc32rr, FE_CC_P, FE_AX, FE_AX); +TEST("\x0f\x4a\x00", CMOVP32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4a\x00", CMOVcc32rm, FE_CC_P, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4a\x00", CMOVP32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4a\x00", CMOVcc32rm, FE_CC_P|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xea\x08", CMPPXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xea\x08", CMPccXADD32mrr, FE_CC_P, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xea\x08", CMPPXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xea\x08", CMPccXADD64mrr, FE_CC_P, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x7b\x00", JNP, 0, FE_PTR(2)); +TEST("\x7b\x00", Jcc, FE_CC_NP, FE_PTR(2)); +TEST("\x0f\x8b\x00\x00\x00\x00", JNP, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8b\x00\x00\x00\x00", Jcc, FE_CC_NP|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8b\x7c\x00\x00\x00", JNP, 0, FE_PTR(130)); +TEST("\x0f\x8b\x7c\x00\x00\x00", Jcc, FE_CC_NP, FE_PTR(130)); +TEST("\x0f\x9b\xc0", SETNP8r, 0, FE_AX); +TEST("\x0f\x9b\xc0", SETcc8r, FE_CC_NP, FE_AX); +TEST("\x0f\x9b\x00", SETNP8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x9b\x00", SETcc8m, FE_CC_NP, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9b\x00", SETNP8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9b\x00", SETcc8m, FE_CC_NP|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4b\xc0", CMOVNP32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x4b\xc0", CMOVcc32rr, FE_CC_NP, FE_AX, FE_AX); +TEST("\x0f\x4b\x00", CMOVNP32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4b\x00", CMOVcc32rm, FE_CC_NP, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4b\x00", CMOVNP32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4b\x00", CMOVcc32rm, FE_CC_NP|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xeb\x08", CMPNPXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xeb\x08", CMPccXADD32mrr, FE_CC_NP, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xeb\x08", CMPNPXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xeb\x08", CMPccXADD64mrr, FE_CC_NP, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x7c\x00", JL, 0, FE_PTR(2)); +TEST("\x7c\x00", Jcc, FE_CC_L, FE_PTR(2)); +TEST("\x0f\x8c\x00\x00\x00\x00", JL, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8c\x00\x00\x00\x00", Jcc, FE_CC_L|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8c\x7c\x00\x00\x00", JL, 0, FE_PTR(130)); +TEST("\x0f\x8c\x7c\x00\x00\x00", Jcc, FE_CC_L, FE_PTR(130)); +TEST("\x0f\x9c\xc0", SETL8r, 0, FE_AX); +TEST("\x0f\x9c\xc0", SETcc8r, FE_CC_L, FE_AX); +TEST("\x0f\x9c\x00", SETL8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x9c\x00", SETcc8m, FE_CC_L, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9c\x00", SETL8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9c\x00", SETcc8m, FE_CC_L|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4c\xc0", CMOVL32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x4c\xc0", CMOVcc32rr, FE_CC_L, FE_AX, FE_AX); +TEST("\x0f\x4c\x00", CMOVL32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4c\x00", CMOVcc32rm, FE_CC_L, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4c\x00", CMOVL32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4c\x00", CMOVcc32rm, FE_CC_L|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xec\x08", CMPLXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xec\x08", CMPccXADD32mrr, FE_CC_L, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xec\x08", CMPLXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xec\x08", CMPccXADD64mrr, FE_CC_L, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x7d\x00", JGE, 0, FE_PTR(2)); +TEST("\x7d\x00", Jcc, FE_CC_GE, FE_PTR(2)); +TEST("\x0f\x8d\x00\x00\x00\x00", JGE, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8d\x00\x00\x00\x00", Jcc, FE_CC_GE|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8d\x7c\x00\x00\x00", JGE, 0, FE_PTR(130)); +TEST("\x0f\x8d\x7c\x00\x00\x00", Jcc, FE_CC_GE, FE_PTR(130)); +TEST("\x0f\x9d\xc0", SETGE8r, 0, FE_AX); +TEST("\x0f\x9d\xc0", SETcc8r, FE_CC_GE, FE_AX); +TEST("\x0f\x9d\x00", SETGE8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x9d\x00", SETcc8m, FE_CC_GE, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9d\x00", SETGE8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9d\x00", SETcc8m, FE_CC_GE|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4d\xc0", CMOVGE32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x4d\xc0", CMOVcc32rr, FE_CC_GE, FE_AX, FE_AX); +TEST("\x0f\x4d\x00", CMOVGE32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4d\x00", CMOVcc32rm, FE_CC_GE, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4d\x00", CMOVGE32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4d\x00", CMOVcc32rm, FE_CC_GE|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xed\x08", CMPNLXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xed\x08", CMPccXADD32mrr, FE_CC_NL, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xed\x08", CMPNLXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xed\x08", CMPccXADD64mrr, FE_CC_NL, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x7e\x00", JLE, 0, FE_PTR(2)); +TEST("\x7e\x00", Jcc, FE_CC_LE, FE_PTR(2)); +TEST("\x0f\x8e\x00\x00\x00\x00", JLE, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8e\x00\x00\x00\x00", Jcc, FE_CC_LE|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8e\x7c\x00\x00\x00", JLE, 0, FE_PTR(130)); +TEST("\x0f\x8e\x7c\x00\x00\x00", Jcc, FE_CC_LE, FE_PTR(130)); +TEST("\x0f\x9e\xc0", SETLE8r, 0, FE_AX); +TEST("\x0f\x9e\xc0", SETcc8r, FE_CC_LE, FE_AX); +TEST("\x0f\x9e\x00", SETLE8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x9e\x00", SETcc8m, FE_CC_LE, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9e\x00", SETLE8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9e\x00", SETcc8m, FE_CC_LE|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4e\xc0", CMOVLE32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x4e\xc0", CMOVcc32rr, FE_CC_LE, FE_AX, FE_AX); +TEST("\x0f\x4e\x00", CMOVLE32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4e\x00", CMOVcc32rm, FE_CC_LE, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4e\x00", CMOVLE32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4e\x00", CMOVcc32rm, FE_CC_LE|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xee\x08", CMPLEXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xee\x08", CMPccXADD32mrr, FE_CC_LE, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xee\x08", CMPLEXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xee\x08", CMPccXADD64mrr, FE_CC_LE, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +TEST("\x7f\x00", JG, 0, FE_PTR(2)); +TEST("\x7f\x00", Jcc, FE_CC_G, FE_PTR(2)); +TEST("\x0f\x8f\x00\x00\x00\x00", JG, FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8f\x00\x00\x00\x00", Jcc, FE_CC_G|FE_JMPL, FE_PTR(6)); +TEST("\x0f\x8f\x7c\x00\x00\x00", JG, 0, FE_PTR(130)); +TEST("\x0f\x8f\x7c\x00\x00\x00", Jcc, FE_CC_G, FE_PTR(130)); +TEST("\x0f\x9f\xc0", SETG8r, 0, FE_AX); +TEST("\x0f\x9f\xc0", SETcc8r, FE_CC_G, FE_AX); +TEST("\x0f\x9f\x00", SETG8m, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x9f\x00", SETcc8m, FE_CC_G, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9f\x00", SETG8m, FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x9f\x00", SETcc8m, FE_CC_G|FE_ADDR32, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4f\xc0", CMOVG32rr, 0, FE_AX, FE_AX); +TEST("\x0f\x4f\xc0", CMOVcc32rr, FE_CC_G, FE_AX, FE_AX); +TEST("\x0f\x4f\x00", CMOVG32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x0f\x4f\x00", CMOVcc32rm, FE_CC_G, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4f\x00", CMOVG32rm, FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x67\x0f\x4f\x00", CMOVcc32rm, FE_CC_G|FE_ADDR32, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x61\xef\x08", CMPNLEXADD32mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\x61\xef\x08", CMPccXADD32mrr, FE_CC_NLE, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xef\x08", CMPNLEXADD64mrr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); +TEST("\xc4\xe2\xe1\xef\x08", CMPccXADD64mrr, FE_CC_NLE, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX, FE_BX); + +// Test FD/TD encodings +TEST("\xa0\x00\x00\x00\x00\x00\x00\x00\x00", MOV8ra, 0, FE_AX, 0); +TEST("\x67\xa0\x00\x00\x00\x00", MOV8ra, FE_ADDR32, FE_AX, 0); +TEST("\x66\xa1\x00\x00\x00\x00\x00\x00\x00\x00", MOV16ra, 0, FE_AX, 0); +TEST("\x67\x66\xa1\x00\x00\x00\x00", MOV16ra, FE_ADDR32, FE_AX, 0); +TEST("\x66\xa1\x10\x32\x54\x76\x98\xba\xdc\xfe", MOV16ra, 0, FE_AX, 0xfedcba9876543210); +TEST("\x67\x66\xa1\x98\xba\xdc\xfe", MOV16ra, FE_ADDR32, FE_AX, 0xfedcba98); +TEST("\xa1\x10\x32\x54\x76\x98\xba\xdc\xfe", MOV32ra, 0, FE_AX, 0xfedcba9876543210); +TEST("\x67\xa1\x98\xba\xdc\xfe", MOV32ra, FE_ADDR32, FE_AX, 0xfedcba98); +TEST("\x48\xa1\x10\x32\x54\x76\x98\xba\xdc\xfe", MOV64ra, 0, FE_AX, 0xfedcba9876543210); +TEST("\x67\x48\xa1\x98\xba\xdc\xfe", MOV64ra, FE_ADDR32, FE_AX, 0xfedcba98); +TEST("\xa2\x00\x00\x00\x00\x00\x00\x00\x00", MOV8ar, 0, 0, FE_AX); +TEST("\x67\xa2\x00\x00\x00\x00", MOV8ar, FE_ADDR32, 0, FE_AX); +TEST("\x66\xa3\x00\x00\x00\x00\x00\x00\x00\x00", MOV16ar, 0, 0, FE_AX); +TEST("\x67\x66\xa3\x00\x00\x00\x00", MOV16ar, FE_ADDR32, 0, FE_AX); +TEST("\x66\xa3\x10\x32\x54\x76\x98\xba\xdc\xfe", MOV16ar, 0, 0xfedcba9876543210, FE_AX); +TEST("\x67\x66\xa3\x98\xba\xdc\xfe", MOV16ar, FE_ADDR32, 0xfedcba98, FE_AX); +TEST("\xa3\x10\x32\x54\x76\x98\xba\xdc\xfe", MOV32ar, 0, 0xfedcba9876543210, FE_AX); +TEST("\x67\xa3\x98\xba\xdc\xfe", MOV32ar, FE_ADDR32, 0xfedcba98, FE_AX); +TEST("\x48\xa3\x10\x32\x54\x76\x98\xba\xdc\xfe", MOV64ar, 0, 0xfedcba9876543210, FE_AX); +TEST("\x67\x48\xa3\x98\xba\xdc\xfe", MOV64ar, FE_ADDR32, 0xfedcba98, FE_AX); +TEST("", MOV8ra, 0, FE_CX, 0); +TEST("", MOV8ra, FE_ADDR32, FE_CX, 0); +TEST("", MOV16ra, 0, FE_CX, 0); +TEST("", MOV16ra, FE_ADDR32, FE_CX, 0); +TEST("", MOV16ra, 0, FE_CX, 0xfedcba9876543210); +TEST("", MOV16ra, FE_ADDR32, FE_CX, 0xfedcba98); +TEST("", MOV32ra, 0, FE_CX, 0xfedcba9876543210); +TEST("", MOV32ra, FE_ADDR32, FE_CX, 0xfedcba98); +TEST("", MOV64ra, 0, FE_CX, 0xfedcba9876543210); +TEST("", MOV64ra, FE_ADDR32, FE_CX, 0xfedcba98); +TEST("", MOV8ar, 0, 0, FE_CX); +TEST("", MOV8ar, FE_ADDR32, 0, FE_CX); +TEST("", MOV16ar, 0, 0, FE_CX); +TEST("", MOV16ar, FE_ADDR32, 0, FE_CX); +TEST("", MOV16ar, 0, 0xfedcba9876543210, FE_CX); +TEST("", MOV16ar, FE_ADDR32, 0xfedcba98, FE_CX); +TEST("", MOV32ar, 0, 0xfedcba9876543210, FE_CX); +TEST("", MOV32ar, FE_ADDR32, 0xfedcba98, FE_CX); +TEST("", MOV64ar, 0, 0xfedcba9876543210, FE_CX); +TEST("", MOV64ar, FE_ADDR32, 0xfedcba98, FE_CX); + +TEST("\xc7\xf8\x02\x00\x00\x00", XBEGIN, 0, FE_PTR(8)); + +// BMI1 +TEST("\xf3\x0f\xbc\xc2", TZCNT32rr, 0, FE_AX, FE_DX); +TEST("\x66\xf3\x0f\xbc\xc2", TZCNT16rr, 0, FE_AX, FE_DX); +TEST("\xf3\x48\x0f\xbc\xc2", TZCNT64rr, 0, FE_AX, FE_DX); +TEST("\xf3\x0f\xbd\xc2", LZCNT32rr, 0, FE_AX, FE_DX); +TEST("\x66\xf3\x0f\xbd\xc2", LZCNT16rr, 0, FE_AX, FE_DX); +TEST("\xf3\x48\x0f\xbd\xc2", LZCNT64rr, 0, FE_AX, FE_DX); +TEST("\xc4\xc2\x18\xf2\xc7", ANDN32rrr, 0, FE_AX, FE_R12, FE_R15); +TEST("\xc4\xc2\x98\xf2\xc7", ANDN64rrr, 0, FE_AX, FE_R12, FE_R15); +TEST("\xc4\x42\x18\xf2\xc7", ANDN32rrr, 0, FE_R8, FE_R12, FE_R15); +TEST("\xc4\x42\x98\xf2\xc7", ANDN64rrr, 0, FE_R8, FE_R12, FE_R15); +TEST("\xc4\xe2\x78\xf3\xca", BLSR32rr, 0, FE_AX, FE_DX); +TEST("\xc4\xe2\x78\xf3\x08", BLSR32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf8\xf3\xca", BLSR64rr, 0, FE_AX, FE_DX); +TEST("\xc4\xe2\xf8\xf3\x08", BLSR64rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xc2\x38\xf3\xc9", BLSR32rr, 0, FE_R8, FE_R9); +TEST("\xc4\xc2\xb8\xf3\xc9", BLSR64rr, 0, FE_R8, FE_R9); +TEST("\xc4\xe2\x38\xf3\xc9", BLSR32rr, 0, FE_R8, FE_CX); +TEST("\xc4\xe2\xb8\xf3\xc9", BLSR64rr, 0, FE_R8, FE_CX); +TEST("\xc4\xc2\x78\xf3\xc9", BLSR32rr, 0, FE_AX, FE_R9); +TEST("\xc4\xc2\xf8\xf3\xc9", BLSR64rr, 0, FE_AX, FE_R9); +TEST("\xc4\xe2\x78\xf3\xd2", BLSMSK32rr, 0, FE_AX, FE_DX); +TEST("\xc4\xe2\x78\xf3\x10", BLSMSK32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf8\xf3\xd2", BLSMSK64rr, 0, FE_AX, FE_DX); +TEST("\xc4\xe2\xf8\xf3\x10", BLSMSK64rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x78\xf3\xda", BLSI32rr, 0, FE_AX, FE_DX); +TEST("\xc4\xe2\x78\xf3\x18", BLSI32rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf8\xf3\xda", BLSI64rr, 0, FE_AX, FE_DX); +TEST("\xc4\xe2\xf8\xf3\x18", BLSI64rm, 0, FE_AX, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xc2\x18\xf7\xc7", BEXTR32rrr, 0, FE_AX, FE_R15, FE_R12); +TEST("\xc4\xc2\x98\xf7\xc7", BEXTR64rrr, 0, FE_AX, FE_R15, FE_R12); +TEST("\xc4\x42\x18\xf7\xc7", BEXTR32rrr, 0, FE_R8, FE_R15, FE_R12); +TEST("\xc4\x42\x98\xf7\xc7", BEXTR64rrr, 0, FE_R8, FE_R15, FE_R12); + +TEST("\x0f\x30", WRMSR, 0); +TEST("\x0f\x32", RDMSR, 0); +TEST("\x0f\x01\xc6", WRMSRNS, 0); +TEST("\xf2\x0f\x01\xc6", RDMSRLIST, 0); +TEST("\xf3\x0f\x01\xc6", WRMSRLIST, 0); +TEST("\xc4\xe7\x7b\xf6\xc1\x10\x20\x30\x40", RDMSRri, 0, FE_CX, 0x40302010); +TEST("\xc4\xe7\x7a\xf6\xc1\x10\x20\x30\x40", WRMSRNSir, 0, 0x40302010, FE_CX); +TEST("\xf2\x0f\x38\xf8\xc1", URDMSRrr, 0, FE_CX, FE_AX); +TEST("\xf3\x0f\x38\xf8\xc1", UWRMSRrr, 0, FE_CX, FE_AX); +TEST("\xc4\xe7\x7b\xf8\xc1\x10\x20\x30\x40", URDMSRri, 0, FE_CX, 0x40302010); +TEST("\xc4\xe7\x7a\xf8\xc1\x10\x20\x30\x40", UWRMSRir, 0, 0x40302010, FE_CX); + +TEST("\x0f\x38\xfc\x01", AADD32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\x48\x0f\x38\xfc\x01", AADD64mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\x66\x0f\x38\xfc\x01", AAND32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\x66\x48\x0f\x38\xfc\x01", AAND64mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\xf3\x0f\x38\xfc\x01", AXOR32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\xf3\x48\x0f\x38\xfc\x01", AXOR64mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\xf2\x0f\x38\xfc\x01", AOR32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\xf2\x48\x0f\x38\xfc\x01", AOR64mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); + +// Test FPU instructions +TEST("\xd8\x00", FADDm32, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xdc\x00", FADDm64, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xd8\xc0", FADDrr, 0, FE_ST0, FE_ST0); +TEST("\xd8\xc1", FADDrr, 0, FE_ST0, FE_ST1); +TEST("\xdc\xc1", FADDrr, 0, FE_ST1, FE_ST0); +TEST("", FADDrr, 0, FE_ST1, FE_ST1); +TEST("\xde\xc1", FADDPrr, 0, FE_ST1, FE_ST0); +TEST("\xda\x00", FIADDm32, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xde\x00", FIADDm16, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xd9\x00", FLDm32, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xdd\x00", FLDm64, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xdb\x28", FLDm80, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xdf\x00", FILDm16, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xdb\x00", FILDm32, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xdf\x28", FILDm64, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xd9\xc1", FLDr, 0, FE_ST1); +TEST("\xd9\xe8", FLD1, 0); +TEST("\xdf\xe0", FSTSWr, 0, FE_AX); +TEST("", FSTSWr, 0, FE_CX); + +// Test VEX encoding +TEST("\xc5\xfc\x77", VZEROALL, 0); +TEST("\xc5\xf8\x77", VZEROUPPER, 0); +TEST("\xc5\xf2\x58\xc2", VADDSSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc5\xf0\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc5\xf4\x58\xc2", VADDPS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xc1\x74\x58\xc0", VADDPS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM8); +TEST("\xc4\x62\x7d\x19\xc2", VBROADCASTSD256rr, 0, FE_XMM8, FE_XMM2); +TEST("\xc4\x62\x7d\x1a\xc2", VBROADCASTF128_256rr, 0, FE_XMM8, FE_XMM2); +TEST("\xc4\xe2\x71\x9d\xc2", VFNMADD132SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x9d\xc2", VFNMADD132SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x2e\x17", VMASKMOVPS128mrr, 0, FE_MEM(FE_DI, 0, FE_NOREG, 0), FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x2e\x17", VMASKMOVPS256mrr, 0, FE_MEM(FE_DI, 0, FE_NOREG, 0), FE_XMM1, FE_XMM2); +TEST("\xc5\xf1\x71\xd7\x02", VPSRLW128rri, 0, FE_XMM1, FE_XMM7, 0x2); +TEST("\xc5\xf5\x71\xd7\x02", VPSRLW256rri, 0, FE_XMM1, FE_XMM7, 0x2); +TEST("\xc4\xc3\xfd\x00\xc9\x12", VPERMQ256rri, 0, FE_XMM1, FE_XMM9, 0x12); +TEST("\xc4\xe3\xfd\x01\xcf\x12", VPERMPD256rri, 0, FE_XMM1, FE_XMM7, 0x12); +TEST("\xc5\xf9\xc5\xc0\x00", VPEXTRWrri, 0, FE_AX, FE_XMM0, 0x0); +// VMASKMOVDQU is the only VEX instruction which supports addrsize/segment +// overrides without a memory operand. +TEST("\xc5\xf9\xf7\xc1", VMASKMOVDQU128rr, 0, FE_XMM0, FE_XMM1); +TEST("\x64\xc5\xf9\xf7\xc1", VMASKMOVDQU128rr, FE_SEG(FE_FS), FE_XMM0, FE_XMM1); +TEST("\x67\xc5\xf9\xf7\xc1", VMASKMOVDQU128rr, FE_ADDR32, FE_XMM0, FE_XMM1); +TEST("\x64\x67\xc5\xf9\xf7\xc1", VMASKMOVDQU128rr, FE_ADDR32|FE_SEG(FE_FS), FE_XMM0, FE_XMM1); + +// Test VEX.RXBv +TEST("\xc5\xf4\x58\xc2", VADDPS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc5\x74\x58\xc2", VADDPS256rrr, 0, FE_XMM8, FE_XMM1, FE_XMM2); +TEST("\xc5\xb4\x58\xc2", VADDPS256rrr, 0, FE_XMM0, FE_XMM9, FE_XMM2); +TEST("\xc5\x34\x58\xc2", VADDPS256rrr, 0, FE_XMM8, FE_XMM9, FE_XMM2); +TEST("\xc4\xc1\x74\x58\xc2", VADDPS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM10); +TEST("\xc4\x41\x74\x58\xc2", VADDPS256rrr, 0, FE_XMM8, FE_XMM1, FE_XMM10); +TEST("\xc4\xc1\x34\x58\xc2", VADDPS256rrr, 0, FE_XMM0, FE_XMM9, FE_XMM10); +TEST("\xc4\x41\x34\x58\xc2", VADDPS256rrr, 0, FE_XMM8, FE_XMM9, FE_XMM10); + +TEST("\xc5\xf4\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 1, FE_BX, 0)); +TEST("\xc5\x74\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM8, FE_XMM1, FE_MEM(FE_DX, 1, FE_BX, 0)); +TEST("\xc4\xa1\x74\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 1, FE_R11, 0)); +TEST("\xc4\x21\x74\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM8, FE_XMM1, FE_MEM(FE_DX, 1, FE_R11, 0)); +TEST("\xc5\xb4\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM0, FE_XMM9, FE_MEM(FE_DX, 1, FE_BX, 0)); +TEST("\xc5\x34\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM8, FE_XMM9, FE_MEM(FE_DX, 1, FE_BX, 0)); +TEST("\xc4\xa1\x34\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM0, FE_XMM9, FE_MEM(FE_DX, 1, FE_R11, 0)); +TEST("\xc4\x21\x34\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM8, FE_XMM9, FE_MEM(FE_DX, 1, FE_R11, 0)); +TEST("\xc4\xc1\x74\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_R10, 1, FE_BX, 0)); +TEST("\xc4\x41\x74\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM8, FE_XMM1, FE_MEM(FE_R10, 1, FE_BX, 0)); +TEST("\xc4\x81\x74\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_R10, 1, FE_R11, 0)); +TEST("\xc4\x01\x74\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM8, FE_XMM1, FE_MEM(FE_R10, 1, FE_R11, 0)); +TEST("\xc4\xc1\x34\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM0, FE_XMM9, FE_MEM(FE_R10, 1, FE_BX, 0)); +TEST("\xc4\x41\x34\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM8, FE_XMM9, FE_MEM(FE_R10, 1, FE_BX, 0)); +TEST("\xc4\x81\x34\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM0, FE_XMM9, FE_MEM(FE_R10, 1, FE_R11, 0)); +TEST("\xc4\x01\x34\x58\x04\x1a", VADDPS256rrm, 0, FE_XMM8, FE_XMM9, FE_MEM(FE_R10, 1, FE_R11, 0)); + +// Test RVMR encoding +TEST("\xc4\xe3\x71\x4a\xc2\x30", VBLENDVPS128rrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2, FE_XMM3); +TEST("\xc4\xe3\x75\x4a\xc2\x30", VBLENDVPS256rrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2, FE_XMM3); +TEST("\xc4\xe3\x71\x4a\x05\x00\x00\x00\x00\x20", VBLENDVPS128rrmr, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_IP, 0, FE_NOREG, 10), FE_XMM2); +TEST("\xc4\xe3\x75\x4a\x05\x00\x00\x00\x00\x20", VBLENDVPS256rrmr, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_IP, 0, FE_NOREG, 10), FE_XMM2); + +// Make sure that high registers fail with VEX-only instructions +TEST("", VBLENDVPS128rrrr, 0, FE_XMM16, FE_XMM1, FE_XMM2, FE_XMM3); +TEST("", VBLENDVPS128rrrr, 0, FE_XMM0, FE_XMM17, FE_XMM2, FE_XMM3); +TEST("", VBLENDVPS128rrrr, 0, FE_XMM0, FE_XMM1, FE_XMM18, FE_XMM3); +TEST("", VBLENDVPS128rrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2, FE_XMM19); +TEST("", VGATHERDPS128rmr, 0, FE_XMM16, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("", VGATHERDPS128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM17, 0), FE_XMM1); +TEST("", VGATHERDPS128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM18); + +TEST("\xc4\xe2\x71\x96\xc2", VFMADDSUB132PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x96\x06", VFMADDSUB132PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\x96\xc2", VFMADDSUB132PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x96\x06", VFMADDSUB132PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x96\xc2", VFMADDSUB132PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x96\x06", VFMADDSUB132PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\x96\xc2", VFMADDSUB132PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\x96\x06", VFMADDSUB132PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\x97\xc2", VFMSUBADD132PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x97\x06", VFMSUBADD132PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\x97\xc2", VFMSUBADD132PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x97\x06", VFMSUBADD132PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x97\xc2", VFMSUBADD132PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x97\x06", VFMSUBADD132PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\x97\xc2", VFMSUBADD132PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\x97\x06", VFMSUBADD132PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\x98\xc2", VFMADD132PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x98\x06", VFMADD132PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\x98\xc2", VFMADD132PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x98\x06", VFMADD132PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x98\xc2", VFMADD132PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x98\x06", VFMADD132PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\x98\xc2", VFMADD132PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\x98\x06", VFMADD132PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\x99\xc2", VFMADD132SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x99\x06", VFMADD132SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x99\xc2", VFMADD132SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x99\x06", VFMADD132SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\x9a\xc2", VFMSUB132PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x9a\x06", VFMSUB132PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\x9a\xc2", VFMSUB132PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x9a\x06", VFMSUB132PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x9a\xc2", VFMSUB132PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x9a\x06", VFMSUB132PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\x9a\xc2", VFMSUB132PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\x9a\x06", VFMSUB132PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\x9b\xc2", VFMSUB132SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x9b\x06", VFMSUB132SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x9b\xc2", VFMSUB132SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x9b\x06", VFMSUB132SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\x9c\xc2", VFNMADD132PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x9c\x06", VFNMADD132PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\x9c\xc2", VFNMADD132PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x9c\x06", VFNMADD132PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x9c\xc2", VFNMADD132PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x9c\x06", VFNMADD132PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\x9c\xc2", VFNMADD132PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\x9c\x06", VFNMADD132PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\x9d\xc2", VFNMADD132SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x9d\x06", VFNMADD132SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x9d\xc2", VFNMADD132SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x9d\x06", VFNMADD132SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\x9e\xc2", VFNMSUB132PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x9e\x06", VFNMSUB132PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\x9e\xc2", VFNMSUB132PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x9e\x06", VFNMSUB132PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x9e\xc2", VFNMSUB132PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x9e\x06", VFNMSUB132PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\x9e\xc2", VFNMSUB132PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\x9e\x06", VFNMSUB132PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\x9f\xc2", VFNMSUB132SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x9f\x06", VFNMSUB132SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\x9f\xc2", VFNMSUB132SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\x9f\x06", VFNMSUB132SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xa6\xc2", VFMADDSUB213PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xa6\x06", VFMADDSUB213PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xa6\xc2", VFMADDSUB213PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xa6\x06", VFMADDSUB213PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xa6\xc2", VFMADDSUB213PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xa6\x06", VFMADDSUB213PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xa6\xc2", VFMADDSUB213PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xa6\x06", VFMADDSUB213PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xa7\xc2", VFMSUBADD213PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xa7\x06", VFMSUBADD213PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xa7\xc2", VFMSUBADD213PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xa7\x06", VFMSUBADD213PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xa7\xc2", VFMSUBADD213PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xa7\x06", VFMSUBADD213PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xa7\xc2", VFMSUBADD213PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xa7\x06", VFMSUBADD213PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xa8\xc2", VFMADD213PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xa8\x06", VFMADD213PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xa8\xc2", VFMADD213PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xa8\x06", VFMADD213PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xa8\xc2", VFMADD213PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xa8\x06", VFMADD213PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xa8\xc2", VFMADD213PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xa8\x06", VFMADD213PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xa9\xc2", VFMADD213SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xa9\x06", VFMADD213SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xa9\xc2", VFMADD213SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xa9\x06", VFMADD213SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xaa\xc2", VFMSUB213PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xaa\x06", VFMSUB213PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xaa\xc2", VFMSUB213PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xaa\x06", VFMSUB213PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xaa\xc2", VFMSUB213PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xaa\x06", VFMSUB213PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xaa\xc2", VFMSUB213PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xaa\x06", VFMSUB213PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xab\xc2", VFMSUB213SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xab\x06", VFMSUB213SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xab\xc2", VFMSUB213SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xab\x06", VFMSUB213SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xac\xc2", VFNMADD213PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xac\x06", VFNMADD213PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xac\xc2", VFNMADD213PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xac\x06", VFNMADD213PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xac\xc2", VFNMADD213PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xac\x06", VFNMADD213PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xac\xc2", VFNMADD213PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xac\x06", VFNMADD213PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xad\xc2", VFNMADD213SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xad\x06", VFNMADD213SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xad\xc2", VFNMADD213SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xad\x06", VFNMADD213SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xae\xc2", VFNMSUB213PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xae\x06", VFNMSUB213PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xae\xc2", VFNMSUB213PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xae\x06", VFNMSUB213PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xae\xc2", VFNMSUB213PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xae\x06", VFNMSUB213PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xae\xc2", VFNMSUB213PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xae\x06", VFNMSUB213PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xaf\xc2", VFNMSUB213SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xaf\x06", VFNMSUB213SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xaf\xc2", VFNMSUB213SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xaf\x06", VFNMSUB213SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xb6\xc2", VFMADDSUB231PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xb6\x06", VFMADDSUB231PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xb6\xc2", VFMADDSUB231PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xb6\x06", VFMADDSUB231PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xb6\xc2", VFMADDSUB231PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xb6\x06", VFMADDSUB231PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xb6\xc2", VFMADDSUB231PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xb6\x06", VFMADDSUB231PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xb7\xc2", VFMSUBADD231PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xb7\x06", VFMSUBADD231PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xb7\xc2", VFMSUBADD231PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xb7\x06", VFMSUBADD231PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xb7\xc2", VFMSUBADD231PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xb7\x06", VFMSUBADD231PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xb7\xc2", VFMSUBADD231PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xb7\x06", VFMSUBADD231PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xb8\xc2", VFMADD231PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xb8\x06", VFMADD231PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xb8\xc2", VFMADD231PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xb8\x06", VFMADD231PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xb8\xc2", VFMADD231PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xb8\x06", VFMADD231PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xb8\xc2", VFMADD231PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xb8\x06", VFMADD231PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xb9\xc2", VFMADD231SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xb9\x06", VFMADD231SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xb9\xc2", VFMADD231SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xb9\x06", VFMADD231SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xba\xc2", VFMSUB231PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xba\x06", VFMSUB231PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xba\xc2", VFMSUB231PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xba\x06", VFMSUB231PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xba\xc2", VFMSUB231PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xba\x06", VFMSUB231PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xba\xc2", VFMSUB231PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xba\x06", VFMSUB231PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xbb\xc2", VFMSUB231SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xbb\x06", VFMSUB231SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xbb\xc2", VFMSUB231SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xbb\x06", VFMSUB231SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xbc\xc2", VFNMADD231PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xbc\x06", VFNMADD231PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xbc\xc2", VFNMADD231PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xbc\x06", VFNMADD231PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xbc\xc2", VFNMADD231PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xbc\x06", VFNMADD231PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xbc\xc2", VFNMADD231PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xbc\x06", VFNMADD231PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xbd\xc2", VFNMADD231SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xbd\x06", VFNMADD231SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xbd\xc2", VFNMADD231SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xbd\x06", VFNMADD231SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xbe\xc2", VFNMSUB231PS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xbe\x06", VFNMSUB231PS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x75\xbe\xc2", VFNMSUB231PS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xbe\x06", VFNMSUB231PS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xbe\xc2", VFNMSUB231PD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xbe\x06", VFNMSUB231PD128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf5\xbe\xc2", VFNMSUB231PD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xbe\x06", VFNMSUB231PD256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x71\xbf\xc2", VFNMSUB231SSrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xbf\x06", VFNMSUB231SSrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\xf1\xbf\xc2", VFNMSUB231SDrrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xbf\x06", VFNMSUB231SDrrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_SI, 0, FE_NOREG, 0)); + +// VSIB encodings +#ifndef ENC_TEST_TYPESAFE +TEST("", VGATHERDPS128rmr, 0, FE_XMM0, FE_MEM(FE_DI, 8, FE_NOREG, 0), FE_XMM1); // must have SIB +TEST("", VGATHERDPS128rmr, 0, FE_XMM0, FE_MEM(FE_IP, 0, FE_NOREG, 0), FE_XMM1); // must have SIB +TEST("", VGATHERDPS128rmr, 0, FE_XMM0, FE_MEM(FE_DI, 0, FE_AX, 0), FE_XMM1); // must have XMM index +#endif +TEST("\xc4\xe2\x71\x92\x04\xff", VGATHERDPS128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\x71\x92\x04\xe7", VGATHERDPS128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\x75\x92\x04\xff", VGATHERDPS256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\x75\x92\x04\xe7", VGATHERDPS256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\x71\x93\x04\xff", VGATHERQPS128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\x71\x93\x04\xe7", VGATHERQPS128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\x75\x93\x04\xff", VGATHERQPS256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\x75\x93\x04\xe7", VGATHERQPS256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\xf1\x92\x04\xff", VGATHERDPD128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\xf1\x92\x04\xe7", VGATHERDPD128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\xf5\x92\x04\xff", VGATHERDPD256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\xf5\x92\x04\xe7", VGATHERDPD256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\xf1\x93\x04\xff", VGATHERQPD128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\xf1\x93\x04\xe7", VGATHERQPD128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\xf5\x93\x04\xff", VGATHERQPD256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\xf5\x93\x04\xe7", VGATHERQPD256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\x71\x90\x04\xff", VPGATHERDD128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\x71\x90\x04\xe7", VPGATHERDD128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\x75\x90\x04\xff", VPGATHERDD256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\x75\x90\x04\xe7", VPGATHERDD256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\x71\x91\x04\xff", VPGATHERQD128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\x71\x91\x04\xe7", VPGATHERQD128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\x75\x91\x04\xff", VPGATHERQD256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\x75\x91\x04\xe7", VPGATHERQD256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\xf1\x90\x04\xff", VPGATHERDQ128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\xf1\x90\x04\xe7", VPGATHERDQ128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\xf5\x90\x04\xff", VPGATHERDQ256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\xf5\x90\x04\xe7", VPGATHERDQ256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\xf1\x91\x04\xff", VPGATHERQQ128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\xf1\x91\x04\xe7", VPGATHERQQ128rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); +TEST("\xc4\xe2\xf5\x91\x04\xff", VPGATHERQQ256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM7, 0), FE_XMM1); +TEST("\xc4\xe2\xf5\x91\x04\xe7", VPGATHERQQ256rmr, 0, FE_XMM0, FE_MEMV(FE_DI, 8, FE_XMM4, 0), FE_XMM1); + +TEST("\xc4\xe2\x79\xdb\xc1", VAESIMCrr, 0, FE_XMM0, FE_XMM1); +TEST("\xc4\xe3\x79\xdf\xc1\xae", VAESKEYGENASSISTrri, 0, FE_XMM0, FE_XMM1, (int8_t) 0xae); +TEST("\xc4\xe2\x71\xdc\xc2", VAESENC128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xdc\xc2", VAESENC256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xdd\xc2", VAESENCLAST128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xdd\xc2", VAESENCLAST256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xde\xc2", VAESDEC128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xde\xc2", VAESDEC256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\xdf\xc2", VAESDECLAST128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\xdf\xc2", VAESDECLAST256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); + +TEST("\xc4\xe2\x70\x50\xc2", VPDPBUUD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x74\x50\xc2", VPDPBUUD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x50\xc2", VPDPBUSD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x50\xc2", VPDPBUSD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x72\x50\xc2", VPDPBSUD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x76\x50\xc2", VPDPBSUD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x73\x50\xc2", VPDPBSSD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x77\x50\xc2", VPDPBSSD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x70\x51\xc2", VPDPBUUDS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x74\x51\xc2", VPDPBUUDS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x51\xc2", VPDPBUSDS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x51\xc2", VPDPBUSDS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x72\x51\xc2", VPDPBSUDS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x76\x51\xc2", VPDPBSUDS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x73\x51\xc2", VPDPBSSDS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x77\x51\xc2", VPDPBSSDS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x52\xc2", VPDPWSSD128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x52\xc2", VPDPWSSD256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x71\x53\xc2", VPDPWSSDS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\x75\x53\xc2", VPDPWSSDS256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); + +TEST("\xc4\xe2\x78\xb0\x08", VCVTNEOPH2PS128rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7c\xb0\x08", VCVTNEOPH2PS256rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x79\xb0\x08", VCVTNEEPH2PS128rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7d\xb0\x08", VCVTNEEPH2PS256rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7a\xb0\x08", VCVTNEEBF162PS128rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7e\xb0\x08", VCVTNEEBF162PS256rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7b\xb0\x08", VCVTNEOBF162PS128rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7f\xb0\x08", VCVTNEOBF162PS256rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x79\xb1\x08", VBCSTNESH2PS128rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7d\xb1\x08", VBCSTNESH2PS256rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7a\xb1\x08", VBCSTNEBF162PS128rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7e\xb1\x08", VBCSTNEBF162PS256rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x7a\x72\xc1", VCVTNEPS2BF16_128rr, 0, FE_XMM0, FE_XMM1); +TEST("\xc4\xe2\x7e\x72\xc1", VCVTNEPS2BF16_256rr, 0, FE_XMM0, FE_XMM1); + +TEST("\xc4\xe2\xf1\xb4\xc2", VPMADD52LUQ128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xb4\xc2", VPMADD52LUQ256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf1\xb5\xc2", VPMADD52HUQ128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc4\xe2\xf5\xb5\xc2", VPMADD52HUQ256rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); + +// AVX-512 +// NB: VEX instructions are here to test automatic downgrading from EVEX to VEX. + +// EVEX functionality; VEX-downgrade occasionally prevented with mask +// Part 1: register extension bits for rrr/rri +TEST("\xc5\xf0\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x09\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\xc5\x70\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM1, FE_XMM2); +TEST("\x62\x71\x74\x09\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM1, FE_XMM2); +TEST("\x62\xe1\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM1, FE_XMM2); +TEST("\x62\x61\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM1, FE_XMM2); +TEST("\xc5\xb0\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM9, FE_XMM2); +TEST("\x62\xf1\x34\x09\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM9, FE_XMM2); +TEST("\xc5\x30\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM9, FE_XMM2); +TEST("\x62\x71\x34\x09\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM9, FE_XMM2); +TEST("\x62\xe1\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM9, FE_XMM2); +TEST("\x62\x61\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM9, FE_XMM2); +TEST("\x62\xf1\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM17, FE_XMM2); +TEST("\x62\x71\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM17, FE_XMM2); +TEST("\x62\xe1\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM17, FE_XMM2); +TEST("\x62\x61\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM17, FE_XMM2); +TEST("\x62\xf1\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM25, FE_XMM2); +TEST("\x62\x71\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM25, FE_XMM2); +TEST("\x62\xe1\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM25, FE_XMM2); +TEST("\x62\x61\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM25, FE_XMM2); +TEST("\xc4\xc1\x70\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM10); +TEST("\xc4\x41\x70\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM1, FE_XMM10); +TEST("\x62\xc1\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM1, FE_XMM10); +TEST("\x62\x41\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM1, FE_XMM10); +TEST("\xc4\xc1\x30\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM9, FE_XMM10); +TEST("\xc4\x41\x30\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM9, FE_XMM10); +TEST("\x62\xc1\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM9, FE_XMM10); +TEST("\x62\x41\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM9, FE_XMM10); +TEST("\x62\xd1\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM17, FE_XMM10); +TEST("\x62\x51\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM17, FE_XMM10); +TEST("\x62\xc1\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM17, FE_XMM10); +TEST("\x62\x41\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM17, FE_XMM10); +TEST("\x62\xd1\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM25, FE_XMM10); +TEST("\x62\x51\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM25, FE_XMM10); +TEST("\x62\xc1\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM25, FE_XMM10); +TEST("\x62\x41\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM25, FE_XMM10); +TEST("\x62\xb1\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM18); +TEST("\x62\x31\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM1, FE_XMM18); +TEST("\x62\xa1\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM1, FE_XMM18); +TEST("\x62\x21\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM1, FE_XMM18); +TEST("\x62\xb1\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM9, FE_XMM18); +TEST("\x62\x31\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM9, FE_XMM18); +TEST("\x62\xa1\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM9, FE_XMM18); +TEST("\x62\x21\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM9, FE_XMM18); +TEST("\x62\xb1\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM17, FE_XMM18); +TEST("\x62\x31\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM17, FE_XMM18); +TEST("\x62\xa1\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM17, FE_XMM18); +TEST("\x62\x21\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM17, FE_XMM18); +TEST("\x62\xb1\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM25, FE_XMM18); +TEST("\x62\x31\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM25, FE_XMM18); +TEST("\x62\xa1\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM25, FE_XMM18); +TEST("\x62\x21\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM25, FE_XMM18); +TEST("\x62\x91\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM1, FE_XMM26); +TEST("\x62\x11\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM1, FE_XMM26); +TEST("\x62\x81\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM1, FE_XMM26); +TEST("\x62\x01\x74\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM1, FE_XMM26); +TEST("\x62\x91\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM9, FE_XMM26); +TEST("\x62\x11\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM9, FE_XMM26); +TEST("\x62\x81\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM9, FE_XMM26); +TEST("\x62\x01\x34\x08\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM9, FE_XMM26); +TEST("\x62\x91\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM17, FE_XMM26); +TEST("\x62\x11\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM17, FE_XMM26); +TEST("\x62\x81\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM17, FE_XMM26); +TEST("\x62\x01\x74\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM17, FE_XMM26); +TEST("\x62\x91\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM0, FE_XMM25, FE_XMM26); +TEST("\x62\x11\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM8, FE_XMM25, FE_XMM26); +TEST("\x62\x81\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM16, FE_XMM25, FE_XMM26); +TEST("\x62\x01\x34\x00\x58\xc2", VADDPS128rrr, 0, FE_XMM24, FE_XMM25, FE_XMM26); +TEST("\xc5\xf9\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM0, FE_XMM1, 1); +TEST("\xc5\xb9\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM8, FE_XMM1, 1); +TEST("\x62\xf1\x7d\x00\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM16, FE_XMM1, 1); +TEST("\x62\xf1\x3d\x00\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM24, FE_XMM1, 1); +TEST("\xc4\xc1\x79\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM0, FE_XMM9, 1); +TEST("\xc4\xc1\x39\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM8, FE_XMM9, 1); +TEST("\x62\xd1\x7d\x00\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM16, FE_XMM9, 1); +TEST("\x62\xd1\x3d\x00\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM24, FE_XMM9, 1); +TEST("\x62\xb1\x7d\x08\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM0, FE_XMM17, 1); +TEST("\x62\xb1\x3d\x08\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM8, FE_XMM17, 1); +TEST("\x62\xb1\x7d\x00\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM16, FE_XMM17, 1); +TEST("\x62\xb1\x3d\x00\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM24, FE_XMM17, 1); +TEST("\x62\x91\x7d\x08\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM0, FE_XMM25, 1); +TEST("\x62\x91\x3d\x08\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM8, FE_XMM25, 1); +TEST("\x62\x91\x7d\x00\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM16, FE_XMM25, 1); +TEST("\x62\x91\x3d\x00\x71\xd1\x01", VPSRLW128rri, 0, FE_XMM24, FE_XMM25, 1); +TEST("\xc5\xfd\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM0, FE_XMM1, 1); +TEST("\xc5\xbd\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM8, FE_XMM1, 1); +TEST("\x62\xf1\x7d\x20\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM16, FE_XMM1, 1); +TEST("\x62\xf1\x3d\x20\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM24, FE_XMM1, 1); +TEST("\xc4\xc1\x7d\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM0, FE_XMM9, 1); +TEST("\xc4\xc1\x3d\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM8, FE_XMM9, 1); +TEST("\x62\xd1\x7d\x20\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM16, FE_XMM9, 1); +TEST("\x62\xd1\x3d\x20\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM24, FE_XMM9, 1); +TEST("\x62\xb1\x7d\x28\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM0, FE_XMM17, 1); +TEST("\x62\xb1\x3d\x28\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM8, FE_XMM17, 1); +TEST("\x62\xb1\x7d\x20\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM16, FE_XMM17, 1); +TEST("\x62\xb1\x3d\x20\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM24, FE_XMM17, 1); +TEST("\x62\x91\x7d\x28\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM0, FE_XMM25, 1); +TEST("\x62\x91\x3d\x28\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM8, FE_XMM25, 1); +TEST("\x62\x91\x7d\x20\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM16, FE_XMM25, 1); +TEST("\x62\x91\x3d\x20\x71\xd1\x01", VPSRLW256rri, 0, FE_XMM24, FE_XMM25, 1); +TEST("\x62\xf1\x7d\x48\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM0, FE_XMM1, 1); +TEST("\x62\xf1\x3d\x48\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM8, FE_XMM1, 1); +TEST("\x62\xf1\x7d\x40\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM16, FE_XMM1, 1); +TEST("\x62\xf1\x3d\x40\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM24, FE_XMM1, 1); +TEST("\x62\xd1\x7d\x48\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM0, FE_XMM9, 1); +TEST("\x62\xd1\x3d\x48\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM8, FE_XMM9, 1); +TEST("\x62\xd1\x7d\x40\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM16, FE_XMM9, 1); +TEST("\x62\xd1\x3d\x40\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM24, FE_XMM9, 1); +TEST("\x62\xb1\x7d\x48\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM0, FE_XMM17, 1); +TEST("\x62\xb1\x3d\x48\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM8, FE_XMM17, 1); +TEST("\x62\xb1\x7d\x40\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM16, FE_XMM17, 1); +TEST("\x62\xb1\x3d\x40\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM24, FE_XMM17, 1); +TEST("\x62\x91\x7d\x48\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM0, FE_XMM25, 1); +TEST("\x62\x91\x3d\x48\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM8, FE_XMM25, 1); +TEST("\x62\x91\x7d\x40\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM16, FE_XMM25, 1); +TEST("\x62\x91\x3d\x40\x71\xd1\x01", VPSRLW512rri, 0, FE_XMM24, FE_XMM25, 1); +// Part 2: register extension bits with rrm +TEST("\xc5\xf0\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\xf1\x74\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\xc5\x70\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM8, FE_XMM1, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\x71\x74\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM1, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\xe1\x74\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM1, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\x61\x74\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM1, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\xc5\xb0\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM0, FE_XMM9, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\xf1\x34\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM9, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\xc5\x30\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM8, FE_XMM9, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\x71\x34\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM9, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\xe1\x34\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM9, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\x61\x34\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM9, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\xf1\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM0, FE_XMM17, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\xf1\x74\x01\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM17, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\x71\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM8, FE_XMM17, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\x71\x74\x01\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM17, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\xe1\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM17, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\x61\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM17, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\xf1\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM0, FE_XMM25, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\x71\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM8, FE_XMM25, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\xe1\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM25, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\x62\x61\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM25, FE_MEM(FE_DX, 1, FE_BX, 0x40)); +TEST("\xc4\xa1\x70\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\xb1\x74\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\xc4\x21\x70\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM8, FE_XMM1, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\x31\x74\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM1, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\xa1\x74\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM1, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\x21\x74\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM1, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\xc4\xa1\x30\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM0, FE_XMM9, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\xb1\x34\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM9, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\xc4\x21\x30\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM8, FE_XMM9, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\x31\x34\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM9, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\xa1\x34\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM9, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\x21\x34\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM9, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\xb1\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM0, FE_XMM17, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\xb1\x74\x01\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM17, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\x31\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM8, FE_XMM17, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\x31\x74\x01\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM17, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\xa1\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM17, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\x21\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM17, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\xb1\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM0, FE_XMM25, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\x31\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM8, FE_XMM25, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\xa1\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM25, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\x62\x21\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM25, FE_MEM(FE_DX, 1, FE_R11, 0x40)); +TEST("\xc4\xc1\x70\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\xd1\x74\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\xc4\x41\x70\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM8, FE_XMM1, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\x51\x74\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM1, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\xc1\x74\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM1, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\x41\x74\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM1, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\xc4\xc1\x30\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM0, FE_XMM9, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\xd1\x34\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM9, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\xc4\x41\x30\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM8, FE_XMM9, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\x51\x34\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM9, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\xc1\x34\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM9, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\x41\x34\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM9, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\xd1\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM0, FE_XMM17, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\xd1\x74\x01\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM17, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\x51\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM8, FE_XMM17, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\x51\x74\x01\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM17, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\xc1\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM17, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\x41\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM17, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\xd1\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM0, FE_XMM25, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\x51\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM8, FE_XMM25, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\xc1\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM25, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\x62\x41\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM25, FE_MEM(FE_R10, 1, FE_BX, 0x40)); +TEST("\xc4\x81\x70\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x91\x74\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\xc4\x01\x70\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM8, FE_XMM1, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x11\x74\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM1, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x81\x74\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM1, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x01\x74\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM1, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\xc4\x81\x30\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM0, FE_XMM9, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x91\x34\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM9, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\xc4\x01\x30\x58\x44\x1a\x40", VADDPS128rrm, 0, FE_XMM8, FE_XMM9, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x11\x34\x09\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM9, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x81\x34\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM9, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x01\x34\x08\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM9, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x91\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM0, FE_XMM17, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x91\x74\x01\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM17, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x11\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM8, FE_XMM17, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x11\x74\x01\x58\x44\x1a\x04", VADDPS128rrm_mask, FLAGMASK(0, FE_K1), FE_XMM8, FE_XMM17, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x81\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM17, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x01\x74\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM17, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x91\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM0, FE_XMM25, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x11\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM8, FE_XMM25, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x81\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM16, FE_XMM25, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +TEST("\x62\x01\x34\x00\x58\x44\x1a\x04", VADDPS128rrm, 0, FE_XMM24, FE_XMM25, FE_MEM(FE_R10, 1, FE_R11, 0x40)); +// Part 3: register extension bits with general-purpose register +TEST("\xc4\xe3\x71\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM1, FE_DX, 1); +TEST("\xc4\xc3\x71\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM1, FE_R10, 1); +TEST("\xc4\x63\x71\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM8, FE_XMM1, FE_DX, 1); +TEST("\xc4\x43\x71\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM8, FE_XMM1, FE_R10, 1); +TEST("\x62\xe3\x75\x08\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM16, FE_XMM1, FE_DX, 1); +TEST("\x62\xc3\x75\x08\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM16, FE_XMM1, FE_R10, 1); +TEST("\x62\x63\x75\x08\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM24, FE_XMM1, FE_DX, 1); +TEST("\x62\x43\x75\x08\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM24, FE_XMM1, FE_R10, 1); +TEST("\xc4\xe3\x31\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM9, FE_DX, 1); +TEST("\xc4\xc3\x31\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM9, FE_R10, 1); +TEST("\xc4\x63\x31\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM8, FE_XMM9, FE_DX, 1); +TEST("\xc4\x43\x31\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM8, FE_XMM9, FE_R10, 1); +TEST("\x62\xe3\x35\x08\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM16, FE_XMM9, FE_DX, 1); +TEST("\x62\xc3\x35\x08\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM16, FE_XMM9, FE_R10, 1); +TEST("\x62\x63\x35\x08\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM24, FE_XMM9, FE_DX, 1); +TEST("\x62\x43\x35\x08\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM24, FE_XMM9, FE_R10, 1); +TEST("\x62\xf3\x75\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM17, FE_DX, 1); +TEST("\x62\xd3\x75\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM17, FE_R10, 1); +TEST("\x62\x73\x75\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM8, FE_XMM17, FE_DX, 1); +TEST("\x62\x53\x75\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM8, FE_XMM17, FE_R10, 1); +TEST("\x62\xe3\x75\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM16, FE_XMM17, FE_DX, 1); +TEST("\x62\xc3\x75\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM16, FE_XMM17, FE_R10, 1); +TEST("\x62\x63\x75\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM24, FE_XMM17, FE_DX, 1); +TEST("\x62\x43\x75\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM24, FE_XMM17, FE_R10, 1); +TEST("\x62\xf3\x35\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM25, FE_DX, 1); +TEST("\x62\xd3\x35\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM25, FE_R10, 1); +TEST("\x62\x73\x35\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM8, FE_XMM25, FE_DX, 1); +TEST("\x62\x53\x35\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM8, FE_XMM25, FE_R10, 1); +TEST("\x62\xe3\x35\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM16, FE_XMM25, FE_DX, 1); +TEST("\x62\xc3\x35\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM16, FE_XMM25, FE_R10, 1); +TEST("\x62\x63\x35\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM24, FE_XMM25, FE_DX, 1); +TEST("\x62\x43\x35\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM24, FE_XMM25, FE_R10, 1); +// Part 4: register extensions with unusual VEX fallbacks +TEST("\xc5\xfa\x7e\xc1", VMOVQrr, 0, FE_XMM0, FE_XMM1); +TEST("\x62\xb1\xfe\x08\x7e\xc1", VMOVQrr, 0, FE_XMM0, FE_XMM17); +TEST("\xc5\xf9\x7e\xc8", VMOVD_X2Grr, 0, FE_AX, FE_XMM1); +TEST("\x62\xe1\x7d\x08\x7e\xc8", VMOVD_X2Grr, 0, FE_AX, FE_XMM17); +TEST("\xc5\xf9\x7e\x08", VMOVDmr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_XMM1); +TEST("\x62\xe1\x7d\x08\x7e\x08", VMOVDmr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_XMM17); +TEST("\xc5\xf9\x6e\xc8", VMOVD_G2Xrr, 0, FE_XMM1, FE_AX); +TEST("\x62\xe1\x7d\x08\x6e\xc8", VMOVD_G2Xrr, 0, FE_XMM17, FE_AX); +TEST("\xc5\xf9\x6e\x08", VMOVDrm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x62\xe1\x7d\x08\x6e\x08", VMOVDrm, 0, FE_XMM17, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe1\xf9\x7e\xc8", VMOVQ_X2Grr, 0, FE_AX, FE_XMM1); +TEST("\x62\xe1\xfd\x08\x7e\xc8", VMOVQ_X2Grr, 0, FE_AX, FE_XMM17); +TEST("\xc5\xf9\xd6\x08", VMOVQmr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_XMM1); +TEST("\x62\xe1\xfd\x08\xd6\x08", VMOVQmr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_XMM17); +TEST("\xc4\xe1\xf9\x6e\xc8", VMOVQ_G2Xrr, 0, FE_XMM1, FE_AX); +TEST("\x62\xe1\xfd\x08\x6e\xc8", VMOVQ_G2Xrr, 0, FE_XMM17, FE_AX); +TEST("\xc5\xfa\x7e\x08", VMOVQrm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\x62\xe1\xfe\x08\x7e\x08", VMOVQrm, 0, FE_XMM17, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe3\x71\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM1, FE_DX, 1); +TEST("\x62\xf3\x75\x00\x20\xc2\x01", VPINSRBrrri, 0, FE_XMM0, FE_XMM17, FE_DX, 1); +TEST("\xc4\xe3\x71\x20\x42\x20\x01", VPINSRBrrmi, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), 1); +TEST("\x62\xf3\x75\x00\x20\x42\x20\x01", VPINSRBrrmi, 0, FE_XMM0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), 1); +TEST("\xc5\xf1\xc4\xc2\x01", VPINSRWrrri, 0, FE_XMM0, FE_XMM1, FE_DX, 1); +TEST("\x62\xf1\x75\x00\xc4\xc2\x01", VPINSRWrrri, 0, FE_XMM0, FE_XMM17, FE_DX, 1); +TEST("\xc5\xf1\xc4\x42\x20\x01", VPINSRWrrmi, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), 1); +TEST("\x62\xf1\x75\x00\xc4\x42\x10\x01", VPINSRWrrmi, 0, FE_XMM0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), 1); +TEST("\xc4\xe3\x71\x22\xc2\x01", VPINSRDrrri, 0, FE_XMM0, FE_XMM1, FE_DX, 1); +TEST("\x62\xf3\x75\x00\x22\xc2\x01", VPINSRDrrri, 0, FE_XMM0, FE_XMM17, FE_DX, 1); +TEST("\xc4\xe3\x71\x22\x42\x20\x01", VPINSRDrrmi, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), 1); +TEST("\x62\xf3\x75\x00\x22\x42\x08\x01", VPINSRDrrmi, 0, FE_XMM0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), 1); +TEST("\xc4\xe3\xf1\x22\xc2\x01", VPINSRQrrri, 0, FE_XMM0, FE_XMM1, FE_DX, 1); +TEST("\x62\xf3\xf5\x00\x22\xc2\x01", VPINSRQrrri, 0, FE_XMM0, FE_XMM17, FE_DX, 1); +TEST("\xc4\xe3\xf1\x22\x42\x20\x01", VPINSRQrrmi, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), 1); +TEST("\x62\xf3\xf5\x00\x22\x42\x04\x01", VPINSRQrrmi, 0, FE_XMM0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), 1); +TEST("\xc4\xe3\x79\x14\xca\x01", VPEXTRBrri, 0, FE_DX, FE_XMM1, 1); +TEST("\x62\xe3\x7d\x08\x14\xca\x01", VPEXTRBrri, 0, FE_DX, FE_XMM17, 1); +TEST("\xc4\xe3\x79\x14\x4a\x20\x01", VPEXTRBmri, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), FE_XMM1, 1); +TEST("\x62\xe3\x7d\x08\x14\x4a\x20\x01", VPEXTRBmri, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), FE_XMM17, 1); +TEST("\xc5\xf9\xc5\xd1\x01", VPEXTRWrri, 0, FE_DX, FE_XMM1, 1); +TEST("\x62\xb1\x7d\x08\xc5\xd1\x01", VPEXTRWrri, 0, FE_DX, FE_XMM17, 1); +TEST("\xc4\xe3\x79\x15\x4a\x20\x01", VPEXTRWmri, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), FE_XMM1, 1); +TEST("\x62\xe3\x7d\x08\x15\x4a\x10\x01", VPEXTRWmri, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), FE_XMM17, 1); +TEST("\xc4\xe3\x79\x16\xca\x01", VPEXTRDrri, 0, FE_DX, FE_XMM1, 1); +TEST("\x62\xe3\x7d\x08\x16\xca\x01", VPEXTRDrri, 0, FE_DX, FE_XMM17, 1); +TEST("\xc4\xe3\x79\x16\x4a\x20\x01", VPEXTRDmri, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), FE_XMM1, 1); +TEST("\x62\xe3\x7d\x08\x16\x4a\x08\x01", VPEXTRDmri, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), FE_XMM17, 1); +TEST("\xc4\xe3\xf9\x16\xca\x01", VPEXTRQrri, 0, FE_DX, FE_XMM1, 1); +TEST("\x62\xe3\xfd\x08\x16\xca\x01", VPEXTRQrri, 0, FE_DX, FE_XMM17, 1); +TEST("\xc4\xe3\xf9\x16\x4a\x20\x01", VPEXTRQmri, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), FE_XMM1, 1); +TEST("\x62\xe3\xfd\x08\x16\x4a\x04\x01", VPEXTRQmri, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x20), FE_XMM17, 1); +TEST("\xc4\xe2\x79\x78\xc8", VPBROADCASTB128rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\x7d\x08\x78\xc8", VPBROADCASTB128rr, 0, FE_XMM17, FE_XMM0); +TEST("\xc4\xe2\x7d\x78\xc8", VPBROADCASTB256rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\x7d\x28\x78\xc8", VPBROADCASTB256rr, 0, FE_XMM17, FE_XMM0); +TEST("\x62\xf2\x7d\x48\x78\xc8", VPBROADCASTB512rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\x7d\x48\x78\xc8", VPBROADCASTB512rr, 0, FE_XMM17, FE_XMM0); +TEST("\xc4\xe2\x79\x78\x4a\x20", VPBROADCASTB128rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x08\x78\x4a\x20", VPBROADCASTB128rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\xc4\xe2\x7d\x78\x4a\x20", VPBROADCASTB256rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x28\x78\x4a\x20", VPBROADCASTB256rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x48\x78\x4a\x20", VPBROADCASTB512rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x48\x78\x4a\x20", VPBROADCASTB512rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\xc4\xe2\x79\x79\xc8", VPBROADCASTW128rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\x7d\x08\x79\xc8", VPBROADCASTW128rr, 0, FE_XMM17, FE_XMM0); +TEST("\xc4\xe2\x7d\x79\xc8", VPBROADCASTW256rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\x7d\x28\x79\xc8", VPBROADCASTW256rr, 0, FE_XMM17, FE_XMM0); +TEST("\x62\xf2\x7d\x48\x79\xc8", VPBROADCASTW512rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\x7d\x48\x79\xc8", VPBROADCASTW512rr, 0, FE_XMM17, FE_XMM0); +TEST("\xc4\xe2\x79\x79\x4a\x20", VPBROADCASTW128rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x08\x79\x4a\x10", VPBROADCASTW128rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\xc4\xe2\x7d\x79\x4a\x20", VPBROADCASTW256rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x28\x79\x4a\x10", VPBROADCASTW256rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x48\x79\x4a\x10", VPBROADCASTW512rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x48\x79\x4a\x10", VPBROADCASTW512rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\xc4\xe2\x79\x58\xc8", VPBROADCASTD128rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\x7d\x08\x58\xc8", VPBROADCASTD128rr, 0, FE_XMM17, FE_XMM0); +TEST("\xc4\xe2\x7d\x58\xc8", VPBROADCASTD256rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\x7d\x28\x58\xc8", VPBROADCASTD256rr, 0, FE_XMM17, FE_XMM0); +TEST("\x62\xf2\x7d\x48\x58\xc8", VPBROADCASTD512rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\x7d\x48\x58\xc8", VPBROADCASTD512rr, 0, FE_XMM17, FE_XMM0); +TEST("\xc4\xe2\x79\x58\x4a\x20", VPBROADCASTD128rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x08\x58\x4a\x08", VPBROADCASTD128rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\xc4\xe2\x7d\x58\x4a\x20", VPBROADCASTD256rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x28\x58\x4a\x08", VPBROADCASTD256rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x48\x58\x4a\x08", VPBROADCASTD512rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x48\x58\x4a\x08", VPBROADCASTD512rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\xc4\xe2\x79\x59\xc8", VPBROADCASTQ128rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\xfd\x08\x59\xc8", VPBROADCASTQ128rr, 0, FE_XMM17, FE_XMM0); +TEST("\xc4\xe2\x7d\x59\xc8", VPBROADCASTQ256rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\xfd\x28\x59\xc8", VPBROADCASTQ256rr, 0, FE_XMM17, FE_XMM0); +TEST("\x62\xf2\xfd\x48\x59\xc8", VPBROADCASTQ512rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xe2\xfd\x48\x59\xc8", VPBROADCASTQ512rr, 0, FE_XMM17, FE_XMM0); +TEST("\xc4\xe2\x79\x59\x4a\x20", VPBROADCASTQ128rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\xfd\x08\x59\x4a\x04", VPBROADCASTQ128rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\xc4\xe2\x7d\x59\x4a\x20", VPBROADCASTQ256rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\xfd\x28\x59\x4a\x04", VPBROADCASTQ256rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x48\x59\x4a\x04", VPBROADCASTQ512rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\xfd\x48\x59\x4a\x04", VPBROADCASTQ512rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\xc4\xe2\x7d\x5a\x4a\x20", VBROADCASTI128rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("", VBROADCASTI128rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); // no EVEX version exists +TEST("\x62\xf2\x7d\x28\x5a\x4a\x02", VBROADCASTI32X4_256rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x28\x5a\x4a\x02", VBROADCASTI32X4_256rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x48\x5a\x4a\x02", VBROADCASTI32X4_512rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x48\x5a\x4a\x02", VBROADCASTI32X4_512rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x28\x5a\x4a\x02", VBROADCASTI64X2_256rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\xfd\x28\x5a\x4a\x02", VBROADCASTI64X2_256rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x48\x5a\x4a\x02", VBROADCASTI64X2_512rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\xfd\x48\x5a\x4a\x02", VBROADCASTI64X2_512rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x48\x5b\x4a\x01", VBROADCASTI32X8_512rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\x7d\x48\x5b\x4a\x01", VBROADCASTI32X8_512rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x48\x5b\x4a\x01", VBROADCASTI64X4_512rm, 0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xe2\xfd\x48\x5b\x4a\x01", VBROADCASTI64X4_512rm, 0, FE_XMM17, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x08\x7a\xca", VPBROADCASTB_GP128rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\x7d\x08\x7a\xca", VPBROADCASTB_GP128rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\x7d\x28\x7a\xca", VPBROADCASTB_GP256rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\x7d\x28\x7a\xca", VPBROADCASTB_GP256rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\x7d\x48\x7a\xca", VPBROADCASTB_GP512rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\x7d\x48\x7a\xca", VPBROADCASTB_GP512rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\x7d\x08\x7b\xca", VPBROADCASTW_GP128rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\x7d\x08\x7b\xca", VPBROADCASTW_GP128rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\x7d\x28\x7b\xca", VPBROADCASTW_GP256rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\x7d\x28\x7b\xca", VPBROADCASTW_GP256rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\x7d\x48\x7b\xca", VPBROADCASTW_GP512rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\x7d\x48\x7b\xca", VPBROADCASTW_GP512rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\x7d\x08\x7c\xca", VPBROADCASTD_GP128rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\x7d\x08\x7c\xca", VPBROADCASTD_GP128rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\x7d\x28\x7c\xca", VPBROADCASTD_GP256rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\x7d\x28\x7c\xca", VPBROADCASTD_GP256rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\x7d\x48\x7c\xca", VPBROADCASTD_GP512rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\x7d\x48\x7c\xca", VPBROADCASTD_GP512rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\xfd\x08\x7c\xca", VPBROADCASTQ_GP128rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\xfd\x08\x7c\xca", VPBROADCASTQ_GP128rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\xfd\x28\x7c\xca", VPBROADCASTQ_GP256rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\xfd\x28\x7c\xca", VPBROADCASTQ_GP256rr, 0, FE_XMM17, FE_DX); +TEST("\x62\xf2\xfd\x48\x7c\xca", VPBROADCASTQ_GP512rr, 0, FE_XMM1, FE_DX); +TEST("\x62\xe2\xfd\x48\x7c\xca", VPBROADCASTQ_GP512rr, 0, FE_XMM17, FE_DX); +// Part 5: masks +TEST("\x62\xf1\x74\x09\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x89\x58\xc2", VADDPS128rrr_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x0a\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K2), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x8a\x58\xc2", VADDPS128rrr_maskz, FLAGMASK(0, FE_K2), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x0b\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K3), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x8b\x58\xc2", VADDPS128rrr_maskz, FLAGMASK(0, FE_K3), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x0c\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K4), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x8c\x58\xc2", VADDPS128rrr_maskz, FLAGMASK(0, FE_K4), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x0d\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K5), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x8d\x58\xc2", VADDPS128rrr_maskz, FLAGMASK(0, FE_K5), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x0e\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K6), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x8e\x58\xc2", VADDPS128rrr_maskz, FLAGMASK(0, FE_K6), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x0f\x58\xc2", VADDPS128rrr_mask, FLAGMASK(0, FE_K7), FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x8f\x58\xc2", VADDPS128rrr_maskz, FLAGMASK(0, FE_K7), FE_XMM0, FE_XMM1, FE_XMM2); +// Part 6: memory operands: disp8 compression + broadcast +TEST("\xc5\xf0\x58\x02", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\xc5\xf0\x58\x42\x01", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\xc5\xf0\x58\x42\xff", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\xc5\xf0\x58\x42\x10", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x10)); +TEST("\xc5\xf0\x58\x42\xf0", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x10)); +TEST("\xc5\xf0\x58\x82\xf0\x07\x00\x00", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x7f0)); +TEST("\xc5\xf0\x58\x82\x00\x08\x00\x00", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x800)); +TEST("\xc5\xf0\x58\x82\x00\xf8\xff\xff", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x800)); +TEST("\xc5\xf0\x58\x82\xf0\xf7\xff\xff", VADDPS128rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x810)); +TEST("\x62\xf1\x74\x89\x58\x02", VADDPS128rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\x89\x58\x82\x01\x00\x00\x00", VADDPS128rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\x89\x58\x82\xff\xff\xff\xff", VADDPS128rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\x89\x58\x42\x01", VADDPS128rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x10)); +TEST("\x62\xf1\x74\x89\x58\x42\xff", VADDPS128rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x10)); +TEST("\x62\xf1\x74\x89\x58\x42\x7f", VADDPS128rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x7f0)); +TEST("\x62\xf1\x74\x89\x58\x82\x00\x08\x00\x00", VADDPS128rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x800)); +TEST("\x62\xf1\x74\x89\x58\x42\x80", VADDPS128rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x800)); +TEST("\x62\xf1\x74\x89\x58\x82\xf0\xf7\xff\xff", VADDPS128rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x810)); +TEST("\x62\xf1\x74\x18\x58\x02", VADDPS128rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\x18\x58\x82\x01\x00\x00\x00", VADDPS128rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\x18\x58\x82\xff\xff\xff\xff", VADDPS128rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\x18\x58\x42\x01", VADDPS128rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x4)); +TEST("\x62\xf1\x74\x18\x58\x42\xff", VADDPS128rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x4)); +TEST("\x62\xf1\x74\x18\x58\x42\x7f", VADDPS128rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1fc)); +TEST("\x62\xf1\x74\x18\x58\x82\x00\x02\x00\x00", VADDPS128rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x200)); +TEST("\x62\xf1\x74\x18\x58\x42\x80", VADDPS128rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x200)); +TEST("\x62\xf1\x74\x18\x58\x82\xfc\xfd\xff\xff", VADDPS128rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x204)); +TEST("\x62\xf1\x74\x99\x58\x02", VADDPS128rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\x99\x58\x82\x01\x00\x00\x00", VADDPS128rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\x99\x58\x82\xff\xff\xff\xff", VADDPS128rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\x99\x58\x42\x01", VADDPS128rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x4)); +TEST("\x62\xf1\x74\x99\x58\x42\xff", VADDPS128rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x4)); +TEST("\x62\xf1\x74\x99\x58\x42\x7f", VADDPS128rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1fc)); +TEST("\x62\xf1\x74\x99\x58\x82\x00\x02\x00\x00", VADDPS128rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x200)); +TEST("\x62\xf1\x74\x99\x58\x42\x80", VADDPS128rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x200)); +TEST("\x62\xf1\x74\x99\x58\x82\xfc\xfd\xff\xff", VADDPS128rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x204)); +TEST("\xc5\xf4\x58\x02", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\xc5\xf4\x58\x42\x01", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\xc5\xf4\x58\x42\xff", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\xc5\xf4\x58\x42\x20", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\xc5\xf4\x58\x42\xe0", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x20)); +TEST("\xc5\xf4\x58\x82\xe0\x0f\x00\x00", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0xfe0)); +TEST("\xc5\xf4\x58\x82\x00\x10\x00\x00", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1000)); +TEST("\xc5\xf4\x58\x82\x00\xf0\xff\xff", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x1000)); +TEST("\xc5\xf4\x58\x82\xe0\xef\xff\xff", VADDPS256rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x1020)); +TEST("\x62\xf1\x74\xa9\x58\x02", VADDPS256rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\xa9\x58\x82\x01\x00\x00\x00", VADDPS256rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\xa9\x58\x82\xff\xff\xff\xff", VADDPS256rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\xa9\x58\x42\x01", VADDPS256rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf1\x74\xa9\x58\x42\xff", VADDPS256rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x20)); +TEST("\x62\xf1\x74\xa9\x58\x42\x7f", VADDPS256rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0xfe0)); +TEST("\x62\xf1\x74\xa9\x58\x82\x00\x10\x00\x00", VADDPS256rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1000)); +TEST("\x62\xf1\x74\xa9\x58\x42\x80", VADDPS256rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x1000)); +TEST("\x62\xf1\x74\xa9\x58\x82\xe0\xef\xff\xff", VADDPS256rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x1020)); +TEST("\x62\xf1\x74\x38\x58\x02", VADDPS256rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\x38\x58\x82\x01\x00\x00\x00", VADDPS256rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\x38\x58\x82\xff\xff\xff\xff", VADDPS256rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\x38\x58\x42\x01", VADDPS256rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x4)); +TEST("\x62\xf1\x74\x38\x58\x42\xff", VADDPS256rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x4)); +TEST("\x62\xf1\x74\x38\x58\x42\x7f", VADDPS256rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1fc)); +TEST("\x62\xf1\x74\x38\x58\x82\x00\x02\x00\x00", VADDPS256rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x200)); +TEST("\x62\xf1\x74\x38\x58\x42\x80", VADDPS256rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x200)); +TEST("\x62\xf1\x74\x38\x58\x82\xfc\xfd\xff\xff", VADDPS256rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x204)); +TEST("\x62\xf1\x74\xb9\x58\x02", VADDPS256rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\xb9\x58\x82\x01\x00\x00\x00", VADDPS256rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\xb9\x58\x82\xff\xff\xff\xff", VADDPS256rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\xb9\x58\x42\x01", VADDPS256rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x4)); +TEST("\x62\xf1\x74\xb9\x58\x42\xff", VADDPS256rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x4)); +TEST("\x62\xf1\x74\xb9\x58\x42\x7f", VADDPS256rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1fc)); +TEST("\x62\xf1\x74\xb9\x58\x82\x00\x02\x00\x00", VADDPS256rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x200)); +TEST("\x62\xf1\x74\xb9\x58\x42\x80", VADDPS256rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x200)); +TEST("\x62\xf1\x74\xb9\x58\x82\xfc\xfd\xff\xff", VADDPS256rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x204)); +TEST("\x62\xf1\x74\x48\x58\x02", VADDPS512rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\x48\x58\x82\x01\x00\x00\x00", VADDPS512rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\x48\x58\x82\xff\xff\xff\xff", VADDPS512rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\x48\x58\x42\x01", VADDPS512rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x40)); +TEST("\x62\xf1\x74\x48\x58\x42\xff", VADDPS512rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x40)); +TEST("\x62\xf1\x74\x48\x58\x42\x7f", VADDPS512rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1fc0)); +TEST("\x62\xf1\x74\x48\x58\x82\x00\x20\x00\x00", VADDPS512rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x2000)); +TEST("\x62\xf1\x74\x48\x58\x42\x80", VADDPS512rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x2000)); +TEST("\x62\xf1\x74\x48\x58\x82\xc0\xdf\xff\xff", VADDPS512rrm, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x2040)); +TEST("\x62\xf1\x74\xc9\x58\x02", VADDPS512rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\xc9\x58\x82\x01\x00\x00\x00", VADDPS512rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\xc9\x58\x82\xff\xff\xff\xff", VADDPS512rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\xc9\x58\x42\x01", VADDPS512rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x40)); +TEST("\x62\xf1\x74\xc9\x58\x42\xff", VADDPS512rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x40)); +TEST("\x62\xf1\x74\xc9\x58\x42\x7f", VADDPS512rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1fc0)); +TEST("\x62\xf1\x74\xc9\x58\x82\x00\x20\x00\x00", VADDPS512rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x2000)); +TEST("\x62\xf1\x74\xc9\x58\x42\x80", VADDPS512rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x2000)); +TEST("\x62\xf1\x74\xc9\x58\x82\xc0\xdf\xff\xff", VADDPS512rrm_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x2040)); +TEST("\x62\xf1\x74\x58\x58\x02", VADDPS512rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\x58\x58\x82\x01\x00\x00\x00", VADDPS512rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\x58\x58\x82\xff\xff\xff\xff", VADDPS512rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\x58\x58\x42\x01", VADDPS512rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x4)); +TEST("\x62\xf1\x74\x58\x58\x42\xff", VADDPS512rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x4)); +TEST("\x62\xf1\x74\x58\x58\x42\x7f", VADDPS512rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1fc)); +TEST("\x62\xf1\x74\x58\x58\x82\x00\x02\x00\x00", VADDPS512rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x200)); +TEST("\x62\xf1\x74\x58\x58\x42\x80", VADDPS512rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x200)); +TEST("\x62\xf1\x74\x58\x58\x82\xfc\xfd\xff\xff", VADDPS512rrb, 0, FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x204)); +TEST("\x62\xf1\x74\xd9\x58\x02", VADDPS512rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0)); +TEST("\x62\xf1\x74\xd9\x58\x82\x01\x00\x00\x00", VADDPS512rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 1)); +TEST("\x62\xf1\x74\xd9\x58\x82\xff\xff\xff\xff", VADDPS512rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -1)); +TEST("\x62\xf1\x74\xd9\x58\x42\x01", VADDPS512rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x4)); +TEST("\x62\xf1\x74\xd9\x58\x42\xff", VADDPS512rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x4)); +TEST("\x62\xf1\x74\xd9\x58\x42\x7f", VADDPS512rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x1fc)); +TEST("\x62\xf1\x74\xd9\x58\x82\x00\x02\x00\x00", VADDPS512rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x200)); +TEST("\x62\xf1\x74\xd9\x58\x42\x80", VADDPS512rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x200)); +TEST("\x62\xf1\x74\xd9\x58\x82\xfc\xfd\xff\xff", VADDPS512rrb_maskz, FLAGMASK(0, FE_K1), FE_XMM0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, -0x204)); +// Part 7: ER/SAE +TEST("\x62\xf1\x74\x48\x58\xc2", VADDPS512rrr, 0, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x18\x58\xc2", VADDPS512rrr_er, FE_RC_RN, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x38\x58\xc2", VADDPS512rrr_er, FE_RC_RD, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x58\x58\xc2", VADDPS512rrr_er, FE_RC_RU, FE_XMM0, FE_XMM1, FE_XMM2); +TEST("\x62\xf1\x74\x78\x58\xc2", VADDPS512rrr_er, FE_RC_RZ, FE_XMM0, FE_XMM1, FE_XMM2); +// Part 8: VSIB +TEST("", VPGATHERDD128rm, FLAGMASK(0, FE_K0), FE_XMM0, FE_MEMV(FE_AX, 1, FE_XMM1, 0)); // k0 not allowed +TEST("\x62\xf2\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_AX, 1, FE_XMM1, 0)); +TEST("\x62\xf2\x7d\x09\x90\x44\x08\x04", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_AX, 1, FE_XMM1, 0x10)); +TEST("\x62\xf2\x7d\x09\x90\x84\x08\x11\x00\x00\x00", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_AX, 1, FE_XMM1, 0x11)); +TEST("\x62\xf2\x7d\x09\x90\x04\x0d\x00\x00\x00\x00", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_NOREG, 1, FE_XMM1, 0)); +TEST("\x62\xf2\x7d\x09\x90\x84\xc8\x11\x00\x00\x00", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_AX, 8, FE_XMM1, 0x11)); +TEST("\x62\xf2\x7d\x09\x90\x04\xcd\x00\x00\x00\x00", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_NOREG, 8, FE_XMM1, 0)); +TEST("\x62\xf2\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_AX, 1, FE_XMM1, 0)); +TEST("\x62\xd2\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_R8, 1, FE_XMM1, 0)); +TEST("\x62\xb2\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_AX, 1, FE_XMM9, 0)); +TEST("\x62\x92\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_R8, 1, FE_XMM9, 0)); +TEST("\x62\xf2\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_AX, 1, FE_XMM17, 0)); +TEST("\x62\xd2\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_R8, 1, FE_XMM17, 0)); +TEST("\x62\xb2\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_AX, 1, FE_XMM25, 0)); +TEST("\x62\x92\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM0, FE_MEMV(FE_R8, 1, FE_XMM25, 0)); +TEST("\x62\x72\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM8, FE_MEMV(FE_AX, 1, FE_XMM1, 0)); +TEST("\x62\x52\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM8, FE_MEMV(FE_R8, 1, FE_XMM1, 0)); +TEST("\x62\x32\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM8, FE_MEMV(FE_AX, 1, FE_XMM9, 0)); +TEST("\x62\x12\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM8, FE_MEMV(FE_R8, 1, FE_XMM9, 0)); +TEST("\x62\x72\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM8, FE_MEMV(FE_AX, 1, FE_XMM17, 0)); +TEST("\x62\x52\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM8, FE_MEMV(FE_R8, 1, FE_XMM17, 0)); +TEST("\x62\x32\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM8, FE_MEMV(FE_AX, 1, FE_XMM25, 0)); +TEST("\x62\x12\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM8, FE_MEMV(FE_R8, 1, FE_XMM25, 0)); +TEST("\x62\xe2\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM16, FE_MEMV(FE_AX, 1, FE_XMM1, 0)); +TEST("\x62\xc2\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM16, FE_MEMV(FE_R8, 1, FE_XMM1, 0)); +TEST("\x62\xa2\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM16, FE_MEMV(FE_AX, 1, FE_XMM9, 0)); +TEST("\x62\x82\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM16, FE_MEMV(FE_R8, 1, FE_XMM9, 0)); +TEST("\x62\xe2\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM16, FE_MEMV(FE_AX, 1, FE_XMM17, 0)); +TEST("\x62\xc2\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM16, FE_MEMV(FE_R8, 1, FE_XMM17, 0)); +TEST("\x62\xa2\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM16, FE_MEMV(FE_AX, 1, FE_XMM25, 0)); +TEST("\x62\x82\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM16, FE_MEMV(FE_R8, 1, FE_XMM25, 0)); +TEST("\x62\x62\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM24, FE_MEMV(FE_AX, 1, FE_XMM1, 0)); +TEST("\x62\x42\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM24, FE_MEMV(FE_R8, 1, FE_XMM1, 0)); +TEST("\x62\x22\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM24, FE_MEMV(FE_AX, 1, FE_XMM9, 0)); +TEST("\x62\x02\x7d\x09\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM24, FE_MEMV(FE_R8, 1, FE_XMM9, 0)); +TEST("\x62\x62\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM24, FE_MEMV(FE_AX, 1, FE_XMM17, 0)); +TEST("\x62\x42\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM24, FE_MEMV(FE_R8, 1, FE_XMM17, 0)); +TEST("\x62\x22\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM24, FE_MEMV(FE_AX, 1, FE_XMM25, 0)); +TEST("\x62\x02\x7d\x01\x90\x04\x08", VPGATHERDD128rm, FLAGMASK(0, FE_K1), FE_XMM24, FE_MEMV(FE_R8, 1, FE_XMM25, 0)); + +// VCVTTPD2DQ has different W bit for VEX/EVEX, so fallback is implemented using +// REXW flip. Test that this works. +TEST("\xc4\x41\x79\xe6\xf7", VCVTTPD2DQ128rr, 0, FE_XMM14, FE_XMM15); +TEST("\xc4\x41\x7d\xe6\xf7", VCVTTPD2DQ256rr, 0, FE_XMM14, FE_XMM15); +TEST("\x62\x51\xfd\x48\xe6\xf7", VCVTTPD2DQ512rr, 0, FE_XMM14, FE_XMM15); +TEST("\x62\x51\xfd\x18\xe6\xf7", VCVTTPD2DQ512rr_sae, 0, FE_XMM14, FE_XMM15); +TEST("\xc4\x01\x79\xe6\x74\x37\x40", VCVTTPD2DQ128rm, 0, FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\xc4\x01\x7d\xe6\x74\x37\x40", VCVTTPD2DQ256rm, 0, FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x48\xe6\x74\x37\x01", VCVTTPD2DQ512rm, 0, FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x18\xe6\x74\x37\x08", VCVTTPD2DQ128rb, 0, FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x38\xe6\x74\x37\x08", VCVTTPD2DQ256rb, 0, FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x58\xe6\x74\x37\x08", VCVTTPD2DQ512rb, 0, FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x51\xfd\x09\xe6\xf7", VCVTTPD2DQ128rr_mask, FLAGMASK(0, FE_K1), FE_XMM14, FE_XMM15); +TEST("\x62\x51\xfd\x29\xe6\xf7", VCVTTPD2DQ256rr_mask, FLAGMASK(0, FE_K1), FE_XMM14, FE_XMM15); +TEST("\x62\x51\xfd\x49\xe6\xf7", VCVTTPD2DQ512rr_mask, FLAGMASK(0, FE_K1), FE_XMM14, FE_XMM15); +TEST("\x62\x51\xfd\x19\xe6\xf7", VCVTTPD2DQ512rr_mask_sae, FLAGMASK(0, FE_K1), FE_XMM14, FE_XMM15); +TEST("\x62\x11\xfd\x09\xe6\x74\x37\x04", VCVTTPD2DQ128rm_mask, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x29\xe6\x74\x37\x02", VCVTTPD2DQ256rm_mask, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x49\xe6\x74\x37\x01", VCVTTPD2DQ512rm_mask, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x19\xe6\x74\x37\x08", VCVTTPD2DQ128rb_mask, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x39\xe6\x74\x37\x08", VCVTTPD2DQ256rb_mask, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x59\xe6\x74\x37\x08", VCVTTPD2DQ512rb_mask, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x51\xfd\x89\xe6\xf7", VCVTTPD2DQ128rr_maskz, FLAGMASK(0, FE_K1), FE_XMM14, FE_XMM15); +TEST("\x62\x51\xfd\xa9\xe6\xf7", VCVTTPD2DQ256rr_maskz, FLAGMASK(0, FE_K1), FE_XMM14, FE_XMM15); +TEST("\x62\x51\xfd\xc9\xe6\xf7", VCVTTPD2DQ512rr_maskz, FLAGMASK(0, FE_K1), FE_XMM14, FE_XMM15); +TEST("\x62\x51\xfd\x99\xe6\xf7", VCVTTPD2DQ512rr_maskz_sae, FLAGMASK(0, FE_K1), FE_XMM14, FE_XMM15); +TEST("\x62\x11\xfd\x89\xe6\x74\x37\x04", VCVTTPD2DQ128rm_maskz, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\xa9\xe6\x74\x37\x02", VCVTTPD2DQ256rm_maskz, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\xc9\xe6\x74\x37\x01", VCVTTPD2DQ512rm_maskz, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\x99\xe6\x74\x37\x08", VCVTTPD2DQ128rb_maskz, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\xb9\xe6\x74\x37\x08", VCVTTPD2DQ256rb_maskz, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x11\xfd\xd9\xe6\x74\x37\x08", VCVTTPD2DQ512rb_maskz, FLAGMASK(0, FE_K1), FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); + +TEST("\xc4\x42\x7d\x19\xf7", VBROADCASTSD256rr, 0, FE_XMM14, FE_XMM15); +TEST("\xc4\x02\x7d\x19\x74\x37\x40", VBROADCASTSD256rm, 0, FE_XMM14, FE_MEM(FE_R15, 1, FE_R14, 0x40)); +TEST("\x62\x82\xfd\x28\x19\x44\x37\x08", VBROADCASTSD256rm, 0, FE_XMM16, FE_MEM(FE_R15, 1, FE_R14, 0x40)); + +// VMOVDDUP has special tuple size for L0. +TEST("\xc5\xfb\x12\x48\x08", VMOVDDUP128rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0x8)); +TEST("\x62\xf1\xff\x09\x12\x48\x01", VMOVDDUP128rm_mask, FLAGMASK(0, FE_K1), FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0x8)); +TEST("\xc5\xfb\x12\xc8", VMOVDDUP128rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xf1\xff\x09\x12\xc8", VMOVDDUP128rr_mask, FLAGMASK(0, FE_K1), FE_XMM1, FE_XMM0); +TEST("\xc5\xff\x12\x48\x20", VMOVDDUP256rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf1\xff\x29\x12\x48\x01", VMOVDDUP256rm_mask, FLAGMASK(0, FE_K1), FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\xc5\xff\x12\xc8", VMOVDDUP256rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xf1\xff\x29\x12\xc8", VMOVDDUP256rr_mask, FLAGMASK(0, FE_K1), FE_XMM1, FE_XMM0); +TEST("\x62\xf1\xff\x48\x12\x48\x01", VMOVDDUP512rm, 0, FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0x40)); +TEST("\x62\xf1\xff\x49\x12\x48\x01", VMOVDDUP512rm_mask, FLAGMASK(0, FE_K1), FE_XMM1, FE_MEM(FE_AX, 0, FE_NOREG, 0x40)); +TEST("\x62\xf1\xff\x48\x12\xc8", VMOVDDUP512rr, 0, FE_XMM1, FE_XMM0); +TEST("\x62\xf1\xff\x49\x12\xc8", VMOVDDUP512rr_mask, FLAGMASK(0, FE_K1), FE_XMM1, FE_XMM0); + +// VPCOMPRESS and VPEXPAND have different scale size +TEST("\x62\xf2\x7d\x08\x63\x40\x20", VPCOMPRESSB128mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\x7d\x28\x63\x40\x20", VPCOMPRESSB256mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\x7d\x48\x63\x40\x20", VPCOMPRESSB512mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\xfd\x08\x63\x40\x10", VPCOMPRESSW128mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\xfd\x28\x63\x40\x10", VPCOMPRESSW256mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\xfd\x48\x63\x40\x10", VPCOMPRESSW512mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\x7d\x08\x8b\x40\x08", VPCOMPRESSD128mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\x7d\x28\x8b\x40\x08", VPCOMPRESSD256mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\x7d\x48\x8b\x40\x08", VPCOMPRESSD512mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\xfd\x08\x8b\x40\x04", VPCOMPRESSQ128mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\xfd\x28\x8b\x40\x04", VPCOMPRESSQ256mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\xfd\x48\x8b\x40\x04", VPCOMPRESSQ512mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20), FE_XMM0); +TEST("\x62\xf2\x7d\x08\x62\x40\x20", VPEXPANDB128rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x28\x62\x40\x20", VPEXPANDB256rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x48\x62\x40\x20", VPEXPANDB512rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x08\x62\x40\x10", VPEXPANDW128rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x28\x62\x40\x10", VPEXPANDW256rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x48\x62\x40\x10", VPEXPANDW512rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x08\x89\x40\x08", VPEXPANDD128rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x28\x89\x40\x08", VPEXPANDD256rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\x7d\x48\x89\x40\x08", VPEXPANDD512rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x08\x89\x40\x04", VPEXPANDQ128rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x28\x89\x40\x04", VPEXPANDQ256rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); +TEST("\x62\xf2\xfd\x48\x89\x40\x04", VPEXPANDQ512rm, 0, FE_XMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0x20)); + +// Mask can also be destination +TEST("\x62\xf1\x74\x08\xc2\xc2\x01", VCMPPS128krri, 0, FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x74\x09\xc2\xc2\x01", VCMPPS128krri_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x74\x08\xc2\x02\x01", VCMPPS128krmi, 0, FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0), 1); +TEST("\x62\xf1\x74\x09\xc2\x02\x01", VCMPPS128krmi_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0), 1); +TEST("\x62\xf1\x74\x08\xc2\x42\x08\x01", VCMPPS128krmi, 0, FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x09\xc2\x42\x08\x01", VCMPPS128krmi_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x18\xc2\x42\x20\x01", VCMPPS128krbi, 0, FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x19\xc2\x42\x20\x01", VCMPPS128krbi_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x28\xc2\xc2\x01", VCMPPS256krri, 0, FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x74\x29\xc2\xc2\x01", VCMPPS256krri_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x74\x28\xc2\x02\x01", VCMPPS256krmi, 0, FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0), 1); +TEST("\x62\xf1\x74\x29\xc2\x02\x01", VCMPPS256krmi_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0), 1); +TEST("\x62\xf1\x74\x28\xc2\x42\x04\x01", VCMPPS256krmi, 0, FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x29\xc2\x42\x04\x01", VCMPPS256krmi_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x38\xc2\x42\x20\x01", VCMPPS256krbi, 0, FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x39\xc2\x42\x20\x01", VCMPPS256krbi_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x48\xc2\xc2\x01", VCMPPS512krri, 0, FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x74\x49\xc2\xc2\x01", VCMPPS512krri_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x74\x48\xc2\x02\x01", VCMPPS512krmi, 0, FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0), 1); +TEST("\x62\xf1\x74\x49\xc2\x02\x01", VCMPPS512krmi_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0), 1); +TEST("\x62\xf1\x74\x48\xc2\x42\x02\x01", VCMPPS512krmi, 0, FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x49\xc2\x42\x02\x01", VCMPPS512krmi_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x58\xc2\x42\x20\x01", VCMPPS512krbi, 0, FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x59\xc2\x42\x20\x01", VCMPPS512krbi_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_MEM(FE_DX, 0, FE_NOREG, 0x80), 1); +TEST("\x62\xf1\x74\x18\xc2\xc2\x01", VCMPPS512krri_sae, 0, FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x74\x19\xc2\xc2\x01", VCMPPS512krri_mask_sae, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x76\x08\xc2\xc2\x01", VCMPSSkrri, 0, FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x76\x09\xc2\xc2\x01", VCMPSSkrri_mask, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x76\x18\xc2\xc2\x01", VCMPSSkrri_sae, 0, FE_K0, FE_XMM1, FE_XMM2, 1); +TEST("\x62\xf1\x76\x19\xc2\xc2\x01", VCMPSSkrri_mask_sae, FLAGMASK(0, FE_K1), FE_K0, FE_XMM1, FE_XMM2, 1); + +// Mask instructions +TEST("\xc5\xcd\x41\xef", KANDBkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcc\x41\xef", KANDWkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcd\x41\xef", KANDDkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcc\x41\xef", KANDQkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcd\x42\xef", KANDNBkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcc\x42\xef", KANDNWkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcd\x42\xef", KANDNDkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcc\x42\xef", KANDNQkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xf9\x44\xee", KNOTBkk, 0, FE_K5, FE_K6); +TEST("\xc5\xf8\x44\xee", KNOTWkk, 0, FE_K5, FE_K6); +TEST("\xc4\xe1\xf9\x44\xee", KNOTDkk, 0, FE_K5, FE_K6); +TEST("\xc4\xe1\xf8\x44\xee", KNOTQkk, 0, FE_K5, FE_K6); +TEST("\xc5\xcd\x45\xef", KORBkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcc\x45\xef", KORWkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcd\x45\xef", KORDkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcc\x45\xef", KORQkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcd\x46\xef", KXNORBkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcc\x46\xef", KXNORWkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcd\x46\xef", KXNORDkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcc\x46\xef", KXNORQkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcd\x47\xef", KXORBkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcc\x47\xef", KXORWkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcd\x47\xef", KXORDkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcc\x47\xef", KXORQkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcd\x4a\xef", KADDBkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcc\x4a\xef", KADDWkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcd\x4a\xef", KADDDkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcc\x4a\xef", KADDQkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcd\x4b\xef", KUNPCKBWkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xcc\x4b\xef", KUNPCKWDkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc4\xe1\xcc\x4b\xef", KUNPCKDQkkk, 0, FE_K5, FE_K6, FE_K7); +TEST("\xc5\xf9\x98\xee", KORTESTBkk, 0, FE_K5, FE_K6); +TEST("\xc5\xf8\x98\xee", KORTESTWkk, 0, FE_K5, FE_K6); +TEST("\xc4\xe1\xf9\x98\xee", KORTESTDkk, 0, FE_K5, FE_K6); +TEST("\xc4\xe1\xf8\x98\xee", KORTESTQkk, 0, FE_K5, FE_K6); +TEST("\xc5\xf9\x90\xee", KMOVBkk, 0, FE_K5, FE_K6); +TEST("\xc5\xf8\x90\xee", KMOVWkk, 0, FE_K5, FE_K6); +TEST("\xc4\xe1\xf9\x90\xee", KMOVDkk, 0, FE_K5, FE_K6); +TEST("\xc4\xe1\xf8\x90\xee", KMOVQkk, 0, FE_K5, FE_K6); +TEST("\xc5\xf9\x90\x7a\x10", KMOVBkm, 0, FE_K7, FE_MEM(FE_DX, 0, FE_NOREG, 0x10)); +TEST("\xc5\xf8\x90\x7a\x10", KMOVWkm, 0, FE_K7, FE_MEM(FE_DX, 0, FE_NOREG, 0x10)); +TEST("\xc4\xe1\xf9\x90\x7a\x10", KMOVDkm, 0, FE_K7, FE_MEM(FE_DX, 0, FE_NOREG, 0x10)); +TEST("\xc4\xe1\xf8\x90\x7a\x10", KMOVQkm, 0, FE_K7, FE_MEM(FE_DX, 0, FE_NOREG, 0x10)); +TEST("\xc5\xf9\x91\x7a\x10", KMOVBmk, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x10), FE_K7); +TEST("\xc5\xf8\x91\x7a\x10", KMOVWmk, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x10), FE_K7); +TEST("\xc4\xe1\xf9\x91\x7a\x10", KMOVDmk, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x10), FE_K7); +TEST("\xc4\xe1\xf8\x91\x7a\x10", KMOVQmk, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x10), FE_K7); +TEST("\xc5\xf9\x92\xe8", KMOVBkr, 0, FE_K5, FE_AX); +TEST("\xc5\xf8\x92\xe8", KMOVWkr, 0, FE_K5, FE_AX); +TEST("\xc5\xfb\x92\xe8", KMOVDkr, 0, FE_K5, FE_AX); +TEST("\xc4\xe1\xfb\x92\xe8", KMOVQkr, 0, FE_K5, FE_AX); +TEST("\xc5\xf9\x93\xc7", KMOVBrk, 0, FE_AX, FE_K7); +TEST("\xc5\xf8\x93\xc7", KMOVWrk, 0, FE_AX, FE_K7); +TEST("\xc5\xfb\x93\xc7", KMOVDrk, 0, FE_AX, FE_K7); +TEST("\xc4\xe1\xfb\x93\xc7", KMOVQrk, 0, FE_AX, FE_K7); +TEST("\xc5\xf9\x99\xee", KTESTBkk, 0, FE_K5, FE_K6); +TEST("\xc5\xf8\x99\xee", KTESTWkk, 0, FE_K5, FE_K6); +TEST("\xc4\xe1\xf9\x99\xee", KTESTDkk, 0, FE_K5, FE_K6); +TEST("\xc4\xe1\xf8\x99\xee", KTESTQkk, 0, FE_K5, FE_K6); +TEST("\xc4\xe3\x79\x30\xee\x0b", KSHIFTRBkki, 0, FE_K5, FE_K6, 11); +TEST("\xc4\xe3\xf9\x30\xee\x0b", KSHIFTRWkki, 0, FE_K5, FE_K6, 11); +TEST("\xc4\xe3\x79\x31\xee\x0b", KSHIFTRDkki, 0, FE_K5, FE_K6, 11); +TEST("\xc4\xe3\xf9\x31\xee\x0b", KSHIFTRQkki, 0, FE_K5, FE_K6, 11); +TEST("\xc4\xe3\x79\x32\xee\x0b", KSHIFTLBkki, 0, FE_K5, FE_K6, 11); +TEST("\xc4\xe3\xf9\x32\xee\x0b", KSHIFTLWkki, 0, FE_K5, FE_K6, 11); +TEST("\xc4\xe3\x79\x33\xee\x0b", KSHIFTLDkki, 0, FE_K5, FE_K6, 11); +TEST("\xc4\xe3\xf9\x33\xee\x0b", KSHIFTLQkki, 0, FE_K5, FE_K6, 11); + +// Test REX prefix +TEST("\x00\x01", ADD8mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\x00\x21", ADD8mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AH); +TEST("\x40\x00\x21", ADD8mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_SP); +TEST("\x41\x00\x01", ADD8mr, 0, FE_MEM(FE_R9, 0, FE_NOREG, 0), FE_AX); +TEST("", ADD8mr, 0, FE_MEM(FE_R9, 0, FE_NOREG, 0), FE_AH); +TEST("\x41\x00\x21", ADD8mr, 0, FE_MEM(FE_R9, 0, FE_NOREG, 0), FE_SP); +TEST("\x44\x00\x01", ADD8mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_R8); +TEST("\x45\x00\x01", ADD8mr, 0, FE_MEM(FE_R9, 0, FE_NOREG, 0), FE_R8); +TEST("", ADD8mr, 0, FE_MEM(FE_R9, 0, FE_NOREG, 0), FE_AH); +TEST("\x00\x04\x11", ADD8mr, 0, FE_MEM(FE_CX, 1, FE_DX, 0), FE_AX); +TEST("\x00\x24\x11", ADD8mr, 0, FE_MEM(FE_CX, 1, FE_DX, 0), FE_AH); +TEST("\x40\x00\x24\x11", ADD8mr, 0, FE_MEM(FE_CX, 1, FE_DX, 0), FE_SP); +TEST("\x41\x00\x04\x11", ADD8mr, 0, FE_MEM(FE_R9, 1, FE_DX, 0), FE_AX); +TEST("\x41\x00\x24\x11", ADD8mr, 0, FE_MEM(FE_R9, 1, FE_DX, 0), FE_SP); +TEST("", ADD8mr, 0, FE_MEM(FE_R9, 1, FE_DX, 0), FE_AH); +TEST("\x42\x00\x04\x11", ADD8mr, 0, FE_MEM(FE_CX, 1, FE_R10, 0), FE_AX); +TEST("\x42\x00\x24\x11", ADD8mr, 0, FE_MEM(FE_CX, 1, FE_R10, 0), FE_SP); +TEST("", ADD8mr, 0, FE_MEM(FE_CX, 1, FE_R10, 0), FE_AH); +TEST("\x43\x00\x04\x11", ADD8mr, 0, FE_MEM(FE_R9, 1, FE_R10, 0), FE_AX); +TEST("\x43\x00\x24\x11", ADD8mr, 0, FE_MEM(FE_R9, 1, FE_R10, 0), FE_SP); +TEST("", ADD8mr, 0, FE_MEM(FE_R9, 1, FE_R10, 0), FE_AH); +TEST("\x44\x00\x04\x11", ADD8mr, 0, FE_MEM(FE_CX, 1, FE_DX, 0), FE_R8); +TEST("\x45\x00\x04\x11", ADD8mr, 0, FE_MEM(FE_R9, 1, FE_DX, 0), FE_R8); +TEST("\x46\x00\x04\x11", ADD8mr, 0, FE_MEM(FE_CX, 1, FE_R10, 0), FE_R8); +TEST("\x47\x00\x04\x11", ADD8mr, 0, FE_MEM(FE_R9, 1, FE_R10, 0), FE_R8); +TEST("\x00\xc1", ADD8rr, 0, FE_CX, FE_AX); +TEST("\x00\xc5", ADD8rr, 0, FE_CH, FE_AX); +TEST("\x40\x00\xc5", ADD8rr, 0, FE_BP, FE_AX); +TEST("\x41\x00\xc1", ADD8rr, 0, FE_R9, FE_AX); +TEST("\x00\xe1", ADD8rr, 0, FE_CX, FE_AH); +TEST("\x00\xe5", ADD8rr, 0, FE_CH, FE_AH); +TEST("", ADD8rr, 0, FE_BP, FE_AH); +TEST("", ADD8rr, 0, FE_R9, FE_AH); +TEST("\x40\x00\xe1", ADD8rr, 0, FE_CX, FE_SP); +TEST("", ADD8rr, 0, FE_CH, FE_SP); +TEST("\x40\x00\xe5", ADD8rr, 0, FE_BP, FE_SP); +TEST("\x41\x00\xe1", ADD8rr, 0, FE_R9, FE_SP); +TEST("\x44\x00\xc1", ADD8rr, 0, FE_CX, FE_R8); +TEST("", ADD8rr, 0, FE_CH, FE_R8); +TEST("\x44\x00\xc5", ADD8rr, 0, FE_BP, FE_R8); +TEST("\x45\x00\xc1", ADD8rr, 0, FE_R9, FE_R8); +TEST("\x01\x01", ADD32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\x41\x01\x01", ADD32mr, 0, FE_MEM(FE_R9, 0, FE_NOREG, 0), FE_AX); +TEST("\x44\x01\x01", ADD32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_R8); +TEST("\x45\x01\x01", ADD32mr, 0, FE_MEM(FE_R9, 0, FE_NOREG, 0), FE_R8); +TEST("\x01\x04\x11", ADD32mr, 0, FE_MEM(FE_CX, 1, FE_DX, 0), FE_AX); +TEST("\x41\x01\x04\x11", ADD32mr, 0, FE_MEM(FE_R9, 1, FE_DX, 0), FE_AX); +TEST("\x42\x01\x04\x11", ADD32mr, 0, FE_MEM(FE_CX, 1, FE_R10, 0), FE_AX); +TEST("\x43\x01\x04\x11", ADD32mr, 0, FE_MEM(FE_R9, 1, FE_R10, 0), FE_AX); +TEST("\x44\x01\x04\x11", ADD32mr, 0, FE_MEM(FE_CX, 1, FE_DX, 0), FE_R8); +TEST("\x45\x01\x04\x11", ADD32mr, 0, FE_MEM(FE_R9, 1, FE_DX, 0), FE_R8); +TEST("\x46\x01\x04\x11", ADD32mr, 0, FE_MEM(FE_CX, 1, FE_R10, 0), FE_R8); +TEST("\x47\x01\x04\x11", ADD32mr, 0, FE_MEM(FE_R9, 1, FE_R10, 0), FE_R8); +TEST("\x48\x01\x01", ADD64mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\x49\x01\x01", ADD64mr, 0, FE_MEM(FE_R9, 0, FE_NOREG, 0), FE_AX); +TEST("\x4c\x01\x01", ADD64mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_R8); +TEST("\x4d\x01\x01", ADD64mr, 0, FE_MEM(FE_R9, 0, FE_NOREG, 0), FE_R8); +TEST("\x48\x01\x04\x11", ADD64mr, 0, FE_MEM(FE_CX, 1, FE_DX, 0), FE_AX); +TEST("\x49\x01\x04\x11", ADD64mr, 0, FE_MEM(FE_R9, 1, FE_DX, 0), FE_AX); +TEST("\x4a\x01\x04\x11", ADD64mr, 0, FE_MEM(FE_CX, 1, FE_R10, 0), FE_AX); +TEST("\x4b\x01\x04\x11", ADD64mr, 0, FE_MEM(FE_R9, 1, FE_R10, 0), FE_AX); +TEST("\x4c\x01\x04\x11", ADD64mr, 0, FE_MEM(FE_CX, 1, FE_DX, 0), FE_R8); +TEST("\x4d\x01\x04\x11", ADD64mr, 0, FE_MEM(FE_R9, 1, FE_DX, 0), FE_R8); +TEST("\x4e\x01\x04\x11", ADD64mr, 0, FE_MEM(FE_CX, 1, FE_R10, 0), FE_R8); +TEST("\x4f\x01\x04\x11", ADD64mr, 0, FE_MEM(FE_R9, 1, FE_R10, 0), FE_R8); +TEST("\x01\xc1", ADD32rr, 0, FE_CX, FE_AX); +TEST("\x41\x01\xc1", ADD32rr, 0, FE_R9, FE_AX); +TEST("\x44\x01\xc1", ADD32rr, 0, FE_CX, FE_R8); +TEST("\x45\x01\xc1", ADD32rr, 0, FE_R9, FE_R8); +TEST("\x48\x01\xc1", ADD64rr, 0, FE_CX, FE_AX); +TEST("\x49\x01\xc1", ADD64rr, 0, FE_R9, FE_AX); +TEST("\x4c\x01\xc1", ADD64rr, 0, FE_CX, FE_R8); +TEST("\x4d\x01\xc1", ADD64rr, 0, FE_R9, FE_R8); + +// Test ModRM encoding +TEST("\x01\x00", ADD32mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); +TEST("\x01\x04\x24", ADD32mr, 0, FE_MEM(FE_SP, 0, FE_NOREG, 0), FE_AX); +TEST("\x01\x45\x00", ADD32mr, 0, FE_MEM(FE_BP, 0, FE_NOREG, 0), FE_AX); +TEST("\x41\x01\x45\x00", ADD32mr, 0, FE_MEM(FE_R13, 0, FE_NOREG, 0), FE_AX); +TEST("\x41\x01\x45\x80", ADD32mr, 0, FE_MEM(FE_R13, 0, FE_NOREG, -0x80), FE_AX); +TEST("\x41\x01\x85\x80\x00\x00\x00", ADD32mr, 0, FE_MEM(FE_R13, 0, FE_NOREG, 0x80), FE_AX); +TEST("\x01\x04\x25\x01\x00\x00\x00", ADD32mr, 0, FE_MEM(FE_NOREG, 0, FE_NOREG, 0x1), FE_AX); +TEST("\x01\x04\x25\x00\x00\x00\x00", ADD32mr, 0, FE_MEM(FE_NOREG, 0, FE_NOREG, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 0, FE_AX, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 3, FE_AX, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 5, FE_AX, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 9, FE_AX, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 15, FE_AX, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 1, FE_NOREG, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 2, FE_NOREG, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 3, FE_NOREG, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 4, FE_NOREG, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 8, FE_NOREG, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 15, FE_NOREG, 0), FE_AX); +TEST("\x01\x04\x05\x00\x00\x00\x00", ADD32mr, 0, FE_MEM(FE_NOREG, 1, FE_AX, 0), FE_AX); +TEST("\x01\x04\xc5\x00\x00\x00\x00", ADD32mr, 0, FE_MEM(FE_NOREG, 8, FE_AX, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 8, FE_SP, 0), FE_AX); +TEST("\x42\x01\x04\x05\x00\x00\x00\x00", ADD32mr, 0, FE_MEM(FE_NOREG, 1, FE_R8, 0), FE_AX); +// RIP-relative addressing, adds instruction size to offset. +TEST("\x01\x05\x01\x00\x00\x00", ADD32mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x7), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_IP, 1, FE_AX, 0x7), FE_AX); +TEST("\x0f\xaf\x05\xf9\xff\xff\xff", IMUL32rm, 0, FE_AX, FE_MEM(FE_IP, 0, FE_NOREG, 0)); +TEST("\x6b\x05\xf9\xff\xff\xff\x02", IMUL32rmi, 0, FE_AX, FE_MEM(FE_IP, 0, FE_NOREG, 0), 2); +TEST("\x66\x6b\x05\xf8\xff\xff\xff\x02", IMUL16rmi, 0, FE_AX, FE_MEM(FE_IP, 0, FE_NOREG, 0), 2); +TEST("\x69\x05\xf6\xff\xff\xff\x80\x00\x00\x00", IMUL32rmi, 0, FE_AX, FE_MEM(FE_IP, 0, FE_NOREG, 0), 0x80); +TEST("\x66\x69\x05\xf7\xff\xff\xff\x80\x00", IMUL16rmi, 0, FE_AX, FE_MEM(FE_IP, 0, FE_NOREG, 0), 0x80); +// Test RIP-relative addressing with various prefixes +TEST("\x01\x05\x0a\x00\x00\x00", ADD32mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x44\x01\x05\x09\x00\x00\x00", ADD32mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x67\x01\x05\x09\x00\x00\x00", ADD32mr, FE_ADDR32, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x67\x44\x01\x05\x08\x00\x00\x00", ADD32mr, FE_ADDR32, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x64\x01\x05\x09\x00\x00\x00", ADD32mr, FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x64\x44\x01\x05\x08\x00\x00\x00", ADD32mr, FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x64\x67\x01\x05\x08\x00\x00\x00", ADD32mr, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x64\x67\x44\x01\x05\x07\x00\x00\x00", ADD32mr, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x66\x01\x05\x09\x00\x00\x00", ADD16mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x66\x44\x01\x05\x08\x00\x00\x00", ADD16mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x67\x66\x01\x05\x08\x00\x00\x00", ADD16mr, FE_ADDR32, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x67\x66\x44\x01\x05\x07\x00\x00\x00", ADD16mr, FE_ADDR32, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x64\x66\x01\x05\x08\x00\x00\x00", ADD16mr, FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x64\x66\x44\x01\x05\x07\x00\x00\x00", ADD16mr, FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x64\x67\x66\x01\x05\x07\x00\x00\x00", ADD16mr, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x64\x67\x66\x44\x01\x05\x06\x00\x00\x00", ADD16mr, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\xf0\x01\x05\x09\x00\x00\x00", LOCK_ADD32mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\xf0\x44\x01\x05\x08\x00\x00\x00", LOCK_ADD32mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x67\xf0\x01\x05\x08\x00\x00\x00", LOCK_ADD32mr, FE_ADDR32, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x67\xf0\x44\x01\x05\x07\x00\x00\x00", LOCK_ADD32mr, FE_ADDR32, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x64\xf0\x01\x05\x08\x00\x00\x00", LOCK_ADD32mr, FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x64\xf0\x44\x01\x05\x07\x00\x00\x00", LOCK_ADD32mr, FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x64\x67\xf0\x01\x05\x07\x00\x00\x00", LOCK_ADD32mr, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x64\x67\xf0\x44\x01\x05\x06\x00\x00\x00", LOCK_ADD32mr, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\xf0\x66\x01\x05\x08\x00\x00\x00", LOCK_ADD16mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\xf0\x66\x44\x01\x05\x07\x00\x00\x00", LOCK_ADD16mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x67\xf0\x66\x01\x05\x07\x00\x00\x00", LOCK_ADD16mr, FE_ADDR32, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x67\xf0\x66\x44\x01\x05\x06\x00\x00\x00", LOCK_ADD16mr, FE_ADDR32, FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x64\xf0\x66\x01\x05\x07\x00\x00\x00", LOCK_ADD16mr, FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x64\xf0\x66\x44\x01\x05\x06\x00\x00\x00", LOCK_ADD16mr, FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\x64\x67\xf0\x66\x01\x05\x06\x00\x00\x00", LOCK_ADD16mr, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_AX); +TEST("\x64\x67\xf0\x66\x44\x01\x05\x05\x00\x00\x00", LOCK_ADD16mr, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_IP, 0, FE_NOREG, 0x10), FE_R8); +TEST("\xc5\xf9\x6e\x05\x08\x00\x00\x00", VMOVDrm, 0, FE_XMM0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\xc4\xe1\xf9\x6e\x05\x07\x00\x00\x00", VMOVQ_G2Xrm, 0, FE_XMM0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x67\xc5\xf9\x6e\x05\x07\x00\x00\x00", VMOVDrm, FE_ADDR32, FE_XMM0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x67\xc4\xe1\xf9\x6e\x05\x06\x00\x00\x00", VMOVQ_G2Xrm, FE_ADDR32, FE_XMM0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x64\xc5\xf9\x6e\x05\x07\x00\x00\x00", VMOVDrm, FE_SEG(FE_FS), FE_XMM0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x64\xc4\xe1\xf9\x6e\x05\x06\x00\x00\x00", VMOVQ_G2Xrm, FE_SEG(FE_FS), FE_XMM0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x64\x67\xc5\xf9\x6e\x05\x06\x00\x00\x00", VMOVDrm, FE_ADDR32|FE_SEG(FE_FS), FE_XMM0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x64\x67\xc4\xe1\xf9\x6e\x05\x05\x00\x00\x00", VMOVQ_G2Xrm, FE_ADDR32|FE_SEG(FE_FS), FE_XMM0, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x62\xe1\x7d\x08\x6e\x05\x06\x00\x00\x00", VMOVDrm, 0, FE_XMM16, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x67\x62\xe1\x7d\x08\x6e\x05\x05\x00\x00\x00", VMOVDrm, FE_ADDR32, FE_XMM16, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x64\x62\xe1\x7d\x08\x6e\x05\x05\x00\x00\x00", VMOVDrm, FE_SEG(FE_FS), FE_XMM16, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); +TEST("\x64\x67\x62\xe1\x7d\x08\x6e\x05\x04\x00\x00\x00", VMOVDrm, FE_ADDR32|FE_SEG(FE_FS), FE_XMM16, FE_MEM(FE_IP, 0, FE_NOREG, 0x10)); + +TEST("\x01\x00", ADD32mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_AX); +TEST("\x01\x01", ADD32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); +TEST("\x01\x02", ADD32mr, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0), FE_AX); +TEST("\x01\x03", ADD32mr, 0, FE_MEM(FE_BX, 0, FE_NOREG, 0), FE_AX); +TEST("\x01\x04\x80", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_AX, 0), FE_AX); +TEST("\x01\x04\x81", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_AX, 0), FE_AX); +TEST("\x01\x04\x82", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_AX, 0), FE_AX); +TEST("\x01\x04\x83", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_AX, 0), FE_AX); +TEST("\x01\x04\x84", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_AX, 0), FE_AX); +TEST("\x01\x04\x85\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_NOREG, 4, FE_AX, 0x44332211), FE_AX); +TEST("\x01\x04\x86", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_AX, 0), FE_AX); +TEST("\x01\x04\x87", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_AX, 0), FE_AX); +TEST("\x01\x04\x88", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_CX, 0), FE_AX); +TEST("\x01\x04\x89", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_CX, 0), FE_AX); +TEST("\x01\x04\x8a", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_CX, 0), FE_AX); +TEST("\x01\x04\x8b", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_CX, 0), FE_AX); +TEST("\x01\x04\x8c", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_CX, 0), FE_AX); +TEST("\x01\x04\x8d\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_NOREG, 4, FE_CX, 0x44332211), FE_AX); +TEST("\x01\x04\x8e", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_CX, 0), FE_AX); +TEST("\x01\x04\x8f", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_CX, 0), FE_AX); +TEST("\x01\x04\x90", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_DX, 0), FE_AX); +TEST("\x01\x04\x91", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_DX, 0), FE_AX); +TEST("\x01\x04\x92", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_DX, 0), FE_AX); +TEST("\x01\x04\x93", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_DX, 0), FE_AX); +TEST("\x01\x04\x94", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_DX, 0), FE_AX); +TEST("\x01\x04\x95\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_NOREG, 4, FE_DX, 0x44332211), FE_AX); +TEST("\x01\x04\x96", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_DX, 0), FE_AX); +TEST("\x01\x04\x97", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_DX, 0), FE_AX); +TEST("\x01\x04\x98", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_BX, 0), FE_AX); +TEST("\x01\x04\x99", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_BX, 0), FE_AX); +TEST("\x01\x04\x9a", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_BX, 0), FE_AX); +TEST("\x01\x04\x9b", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_BX, 0), FE_AX); +TEST("\x01\x04\x9c", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_BX, 0), FE_AX); +TEST("\x01\x04\x9d\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_NOREG, 4, FE_BX, 0x44332211), FE_AX); +TEST("\x01\x04\x9e", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_BX, 0), FE_AX); +TEST("\x01\x04\x9f", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_BX, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_SP, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_SP, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_SP, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_SP, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_SP, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_NOREG, 4, FE_SP, 0x44332211), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_SP, 0), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_SP, 0), FE_AX); +TEST("\x01\x04\xa8", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_BP, 0), FE_AX); +TEST("\x01\x04\xa9", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_BP, 0), FE_AX); +TEST("\x01\x04\xaa", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_BP, 0), FE_AX); +TEST("\x01\x04\xab", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_BP, 0), FE_AX); +TEST("\x01\x04\xac", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_BP, 0), FE_AX); +TEST("\x01\x04\xad\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_NOREG, 4, FE_BP, 0x44332211), FE_AX); +TEST("\x01\x04\xae", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_BP, 0), FE_AX); +TEST("\x01\x04\xaf", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_BP, 0), FE_AX); +TEST("\x01\x04\xb0", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_SI, 0), FE_AX); +TEST("\x01\x04\xb1", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_SI, 0), FE_AX); +TEST("\x01\x04\xb2", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_SI, 0), FE_AX); +TEST("\x01\x04\xb3", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_SI, 0), FE_AX); +TEST("\x01\x04\xb4", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_SI, 0), FE_AX); +TEST("\x01\x04\xb5\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_NOREG, 4, FE_SI, 0x44332211), FE_AX); +TEST("\x01\x04\xb6", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_SI, 0), FE_AX); +TEST("\x01\x04\xb7", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_SI, 0), FE_AX); +TEST("\x01\x04\xb8", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_DI, 0), FE_AX); +TEST("\x01\x04\xb9", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_DI, 0), FE_AX); +TEST("\x01\x04\xba", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_DI, 0), FE_AX); +TEST("\x01\x04\xbb", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_DI, 0), FE_AX); +TEST("\x01\x04\xbc", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_DI, 0), FE_AX); +TEST("\x01\x04\xbd\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_NOREG, 4, FE_DI, 0x44332211), FE_AX); +TEST("\x01\x04\xbe", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_DI, 0), FE_AX); +TEST("\x01\x04\xbf", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_DI, 0), FE_AX); +TEST("\x01\x05\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_IP, 0, FE_NOREG, 0x44332217), FE_AX); +TEST("\x01\x06", ADD32mr, 0, FE_MEM(FE_SI, 0, FE_NOREG, 0), FE_AX); +TEST("\x01\x07", ADD32mr, 0, FE_MEM(FE_DI, 0, FE_NOREG, 0), FE_AX); +TEST("\x01\x40\x99", ADD32mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, -0x67), FE_AX); +TEST("\x01\x41\x99", ADD32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, -0x67), FE_AX); +TEST("\x01\x42\x99", ADD32mr, 0, FE_MEM(FE_DX, 0, FE_NOREG, -0x67), FE_AX); +TEST("\x01\x43\x99", ADD32mr, 0, FE_MEM(FE_BX, 0, FE_NOREG, -0x67), FE_AX); +TEST("\x01\x44\x80\x99", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_AX, -0x67), FE_AX); +TEST("\x01\x44\x81\x99", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_AX, -0x67), FE_AX); +TEST("\x01\x44\x82\x99", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_AX, -0x67), FE_AX); +TEST("\x01\x44\x83\x99", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_AX, -0x67), FE_AX); +TEST("\x01\x44\x84\x99", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_AX, -0x67), FE_AX); +TEST("\x01\x44\x85\x99", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_AX, -0x67), FE_AX); +TEST("\x01\x44\x86\x99", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_AX, -0x67), FE_AX); +TEST("\x01\x44\x87\x99", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_AX, -0x67), FE_AX); +TEST("\x01\x44\x88\x99", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_CX, -0x67), FE_AX); +TEST("\x01\x44\x89\x99", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_CX, -0x67), FE_AX); +TEST("\x01\x44\x8a\x99", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_CX, -0x67), FE_AX); +TEST("\x01\x44\x8b\x99", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_CX, -0x67), FE_AX); +TEST("\x01\x44\x8c\x99", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_CX, -0x67), FE_AX); +TEST("\x01\x44\x8d\x99", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_CX, -0x67), FE_AX); +TEST("\x01\x44\x8e\x99", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_CX, -0x67), FE_AX); +TEST("\x01\x44\x8f\x99", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_CX, -0x67), FE_AX); +TEST("\x01\x44\x90\x99", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_DX, -0x67), FE_AX); +TEST("\x01\x44\x91\x99", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_DX, -0x67), FE_AX); +TEST("\x01\x44\x92\x99", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_DX, -0x67), FE_AX); +TEST("\x01\x44\x93\x99", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_DX, -0x67), FE_AX); +TEST("\x01\x44\x94\x99", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_DX, -0x67), FE_AX); +TEST("\x01\x44\x95\x99", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_DX, -0x67), FE_AX); +TEST("\x01\x44\x96\x99", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_DX, -0x67), FE_AX); +TEST("\x01\x44\x97\x99", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_DX, -0x67), FE_AX); +TEST("\x01\x44\x98\x99", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_BX, -0x67), FE_AX); +TEST("\x01\x44\x99\x99", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_BX, -0x67), FE_AX); +TEST("\x01\x44\x9a\x99", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_BX, -0x67), FE_AX); +TEST("\x01\x44\x9b\x99", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_BX, -0x67), FE_AX); +TEST("\x01\x44\x9c\x99", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_BX, -0x67), FE_AX); +TEST("\x01\x44\x9d\x99", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_BX, -0x67), FE_AX); +TEST("\x01\x44\x9e\x99", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_BX, -0x67), FE_AX); +TEST("\x01\x44\x9f\x99", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_BX, -0x67), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_SP, -0x67), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_SP, -0x67), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_SP, -0x67), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_SP, -0x67), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_SP, -0x67), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_SP, -0x67), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_SP, -0x67), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_SP, -0x67), FE_AX); +TEST("\x01\x44\xa8\x99", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_BP, -0x67), FE_AX); +TEST("\x01\x44\xa9\x99", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_BP, -0x67), FE_AX); +TEST("\x01\x44\xaa\x99", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_BP, -0x67), FE_AX); +TEST("\x01\x44\xab\x99", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_BP, -0x67), FE_AX); +TEST("\x01\x44\xac\x99", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_BP, -0x67), FE_AX); +TEST("\x01\x44\xad\x99", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_BP, -0x67), FE_AX); +TEST("\x01\x44\xae\x99", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_BP, -0x67), FE_AX); +TEST("\x01\x44\xaf\x99", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_BP, -0x67), FE_AX); +TEST("\x01\x44\xb0\x99", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_SI, -0x67), FE_AX); +TEST("\x01\x44\xb1\x99", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_SI, -0x67), FE_AX); +TEST("\x01\x44\xb2\x99", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_SI, -0x67), FE_AX); +TEST("\x01\x44\xb3\x99", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_SI, -0x67), FE_AX); +TEST("\x01\x44\xb4\x99", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_SI, -0x67), FE_AX); +TEST("\x01\x44\xb5\x99", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_SI, -0x67), FE_AX); +TEST("\x01\x44\xb6\x99", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_SI, -0x67), FE_AX); +TEST("\x01\x44\xb7\x99", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_SI, -0x67), FE_AX); +TEST("\x01\x44\xb8\x99", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_DI, -0x67), FE_AX); +TEST("\x01\x44\xb9\x99", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_DI, -0x67), FE_AX); +TEST("\x01\x44\xba\x99", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_DI, -0x67), FE_AX); +TEST("\x01\x44\xbb\x99", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_DI, -0x67), FE_AX); +TEST("\x01\x44\xbc\x99", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_DI, -0x67), FE_AX); +TEST("\x01\x44\xbd\x99", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_DI, -0x67), FE_AX); +TEST("\x01\x44\xbe\x99", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_DI, -0x67), FE_AX); +TEST("\x01\x44\xbf\x99", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_DI, -0x67), FE_AX); +TEST("\x01\x45\x99", ADD32mr, 0, FE_MEM(FE_BP, 0, FE_NOREG, -0x67), FE_AX); +TEST("\x01\x46\x99", ADD32mr, 0, FE_MEM(FE_SI, 0, FE_NOREG, -0x67), FE_AX); +TEST("\x01\x47\x99", ADD32mr, 0, FE_MEM(FE_DI, 0, FE_NOREG, -0x67), FE_AX); +TEST("\x01\x80\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0x44332211), FE_AX); +TEST("\x01\x81\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0x44332211), FE_AX); +TEST("\x01\x82\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DX, 0, FE_NOREG, 0x44332211), FE_AX); +TEST("\x01\x83\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BX, 0, FE_NOREG, 0x44332211), FE_AX); +TEST("\x01\x84\x80\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_AX, 0x44332211), FE_AX); +TEST("\x01\x84\x81\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_AX, 0x44332211), FE_AX); +TEST("\x01\x84\x82\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_AX, 0x44332211), FE_AX); +TEST("\x01\x84\x83\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_AX, 0x44332211), FE_AX); +TEST("\x01\x84\x84\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_AX, 0x44332211), FE_AX); +TEST("\x01\x84\x85\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_AX, 0x44332211), FE_AX); +TEST("\x01\x84\x86\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_AX, 0x44332211), FE_AX); +TEST("\x01\x84\x87\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_AX, 0x44332211), FE_AX); +TEST("\x01\x84\x88\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_CX, 0x44332211), FE_AX); +TEST("\x01\x84\x89\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_CX, 0x44332211), FE_AX); +TEST("\x01\x84\x8a\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_CX, 0x44332211), FE_AX); +TEST("\x01\x84\x8b\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_CX, 0x44332211), FE_AX); +TEST("\x01\x84\x8c\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_CX, 0x44332211), FE_AX); +TEST("\x01\x84\x8d\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_CX, 0x44332211), FE_AX); +TEST("\x01\x84\x8e\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_CX, 0x44332211), FE_AX); +TEST("\x01\x84\x8f\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_CX, 0x44332211), FE_AX); +TEST("\x01\x84\x90\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_DX, 0x44332211), FE_AX); +TEST("\x01\x84\x91\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_DX, 0x44332211), FE_AX); +TEST("\x01\x84\x92\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_DX, 0x44332211), FE_AX); +TEST("\x01\x84\x93\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_DX, 0x44332211), FE_AX); +TEST("\x01\x84\x94\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_DX, 0x44332211), FE_AX); +TEST("\x01\x84\x95\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_DX, 0x44332211), FE_AX); +TEST("\x01\x84\x96\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_DX, 0x44332211), FE_AX); +TEST("\x01\x84\x97\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_DX, 0x44332211), FE_AX); +TEST("\x01\x84\x98\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_BX, 0x44332211), FE_AX); +TEST("\x01\x84\x99\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_BX, 0x44332211), FE_AX); +TEST("\x01\x84\x9a\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_BX, 0x44332211), FE_AX); +TEST("\x01\x84\x9b\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_BX, 0x44332211), FE_AX); +TEST("\x01\x84\x9c\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_BX, 0x44332211), FE_AX); +TEST("\x01\x84\x9d\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_BX, 0x44332211), FE_AX); +TEST("\x01\x84\x9e\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_BX, 0x44332211), FE_AX); +TEST("\x01\x84\x9f\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_BX, 0x44332211), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_SP, 0x44332211), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_SP, 0x44332211), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_SP, 0x44332211), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_SP, 0x44332211), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_SP, 0x44332211), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_SP, 0x44332211), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_SP, 0x44332211), FE_AX); +TEST("", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_SP, 0x44332211), FE_AX); +TEST("\x01\x84\xa8\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_BP, 0x44332211), FE_AX); +TEST("\x01\x84\xa9\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_BP, 0x44332211), FE_AX); +TEST("\x01\x84\xaa\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_BP, 0x44332211), FE_AX); +TEST("\x01\x84\xab\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_BP, 0x44332211), FE_AX); +TEST("\x01\x84\xac\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_BP, 0x44332211), FE_AX); +TEST("\x01\x84\xad\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_BP, 0x44332211), FE_AX); +TEST("\x01\x84\xae\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_BP, 0x44332211), FE_AX); +TEST("\x01\x84\xaf\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_BP, 0x44332211), FE_AX); +TEST("\x01\x84\xb0\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_SI, 0x44332211), FE_AX); +TEST("\x01\x84\xb1\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_SI, 0x44332211), FE_AX); +TEST("\x01\x84\xb2\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_SI, 0x44332211), FE_AX); +TEST("\x01\x84\xb3\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_SI, 0x44332211), FE_AX); +TEST("\x01\x84\xb4\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_SI, 0x44332211), FE_AX); +TEST("\x01\x84\xb5\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_SI, 0x44332211), FE_AX); +TEST("\x01\x84\xb6\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_SI, 0x44332211), FE_AX); +TEST("\x01\x84\xb7\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_SI, 0x44332211), FE_AX); +TEST("\x01\x84\xb8\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_AX, 4, FE_DI, 0x44332211), FE_AX); +TEST("\x01\x84\xb9\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_CX, 4, FE_DI, 0x44332211), FE_AX); +TEST("\x01\x84\xba\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DX, 4, FE_DI, 0x44332211), FE_AX); +TEST("\x01\x84\xbb\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BX, 4, FE_DI, 0x44332211), FE_AX); +TEST("\x01\x84\xbc\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SP, 4, FE_DI, 0x44332211), FE_AX); +TEST("\x01\x84\xbd\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BP, 4, FE_DI, 0x44332211), FE_AX); +TEST("\x01\x84\xbe\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SI, 4, FE_DI, 0x44332211), FE_AX); +TEST("\x01\x84\xbf\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DI, 4, FE_DI, 0x44332211), FE_AX); +TEST("\x01\x85\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_BP, 0, FE_NOREG, 0x44332211), FE_AX); +TEST("\x01\x86\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_SI, 0, FE_NOREG, 0x44332211), FE_AX); +TEST("\x01\x87\x11\x22\x33\x44", ADD32mr, 0, FE_MEM(FE_DI, 0, FE_NOREG, 0x44332211), FE_AX); +TEST("\x01\xc0", ADD32rr, 0, FE_AX, FE_AX); +TEST("\x01\xc1", ADD32rr, 0, FE_CX, FE_AX); +TEST("\x01\xc2", ADD32rr, 0, FE_DX, FE_AX); +TEST("\x01\xc3", ADD32rr, 0, FE_BX, FE_AX); +TEST("\x01\xc4", ADD32rr, 0, FE_SP, FE_AX); +TEST("\x01\xc5", ADD32rr, 0, FE_BP, FE_AX); +TEST("\x01\xc6", ADD32rr, 0, FE_SI, FE_AX); +TEST("\x01\xc7", ADD32rr, 0, FE_DI, FE_AX); + +// AMX +TEST("\xc4\xe2\x78\x49\x00", LDTILECFGm, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x79\x49\x00", STTILECFGm, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); +TEST("\xc4\xe2\x78\x49\xc0", TILERELEASE, 0); +TEST("\xc4\xe2\x7b\x49\xc0", TILEZEROr, 0, FE_TMM0); +TEST("\xc4\xe2\x7b\x49\xc8", TILEZEROr, 0, FE_TMM1); +TEST("\xc4\xe2\x7b\x49\xf8", TILEZEROr, 0, FE_TMM7); +TEST("\xc4\xe2\x7b\x4b\x04\x10", TILELOADDrm, 0, FE_TMM0, FE_MEM(FE_AX, 1, FE_DX, 0)); +TEST("\xc4\xe2\x7b\x4b\x04\x20", TILELOADDrm, 0, FE_TMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); // has SIB +TEST("\xc4\xe2\x79\x4b\x04\x10", TILELOADDT1rm, 0, FE_TMM0, FE_MEM(FE_AX, 1, FE_DX, 0)); +TEST("\xc4\xe2\x79\x4b\x04\x20", TILELOADDT1rm, 0, FE_TMM0, FE_MEM(FE_AX, 0, FE_NOREG, 0)); // has SIB +TEST("\xc4\xe2\x7a\x4b\x04\x10", TILESTOREDmr, 0, FE_MEM(FE_AX, 1, FE_DX, 0), FE_TMM0); +TEST("\xc4\xe2\x7a\x4b\x04\x20", TILESTOREDmr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_TMM0); // has SIB +// TODO: enforce that all registers must be different +//TEST("", TDPBUUDrrr, 0, FE_TMM0, FE_TMM0, FE_TMM2"); +//TEST("", TDPBUUDrrr, 0, FE_TMM2, FE_TMM0, FE_TMM2"); +//TEST("", TDPBUUDrrr, 0, FE_TMM1, FE_TMM2, FE_TMM2"); +TEST("\xc4\xe2\x6a\x5c\xc8", TDPBF16PSrrr, 0, FE_TMM1, FE_TMM0, FE_TMM2); +TEST("\xc4\xe2\x6b\x5c\xc8", TDPFP16PSrrr, 0, FE_TMM1, FE_TMM0, FE_TMM2); +TEST("\xc4\xe2\x68\x5e\xc8", TDPBUUDrrr, 0, FE_TMM1, FE_TMM0, FE_TMM2); +TEST("\xc4\xe2\x69\x5e\xc8", TDPBUSDrrr, 0, FE_TMM1, FE_TMM0, FE_TMM2); +TEST("\xc4\xe2\x6a\x5e\xc8", TDPBSUDrrr, 0, FE_TMM1, FE_TMM0, FE_TMM2); +TEST("\xc4\xe2\x6b\x5e\xc8", TDPBSSDrrr, 0, FE_TMM1, FE_TMM0, FE_TMM2); +TEST("\xc4\xe2\x68\x6c\xc8", TCMMRLFP16PSrrr, 0, FE_TMM1, FE_TMM0, FE_TMM2); +TEST("\xc4\xe2\x69\x6c\xc8", TCMMIMFP16PSrrr, 0, FE_TMM1, FE_TMM0, FE_TMM2); + +// Test LOCK prefix +TEST("\xf0\x87\x08", LOCK_XCHG32mr, 0, FE_MEM(FE_AX, 0, FE_NOREG, 0), FE_CX); +TEST("\xf0\x0f\xc1\x01", LOCK_XADD32mr, 0, FE_MEM(FE_CX, 0, FE_NOREG, 0), FE_AX); + +// Test long instructions +TEST("\x64\x67\xf0\x41\x81\x84\x00\x00\xff\xff\xff\x78\x56\x34\x12", LOCK_ADD32mi, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_R8, 1, FE_AX, -0x100), 0x12345678); +TEST("\x64\xf0\x66\x41\x81\x84\x00\x00\xff\xff\xff\x34\x12", LOCK_ADD16mi, FE_SEG(FE_FS), FE_MEM(FE_R8, 1, FE_AX, -0x100), 0x1234); +TEST("\x64\x67\xf0\x41\x0f\xba\xac\x00\x00\xff\xff\xff\x78", LOCK_BTS32mi, FE_ADDR32|FE_SEG(FE_FS), FE_MEM(FE_R8, 1, FE_AX, -0x100), 0x78); + +// PBNDKB +TEST("\x0f\x01\xc7", PBNDKB, 0); + +// SM4 +TEST("\xc4\xe2\x6a\xda\xc1", VSM4KEY4_128rrr, 0, FE_XMM0, FE_XMM2, FE_XMM1); +TEST("\x62\xf2\x6e\x00\xda\xc1", VSM4KEY4_128rrr, 0, FE_XMM0, FE_XMM18, FE_XMM1); +TEST("\xc4\xe2\x6e\xda\xc1", VSM4KEY4_256rrr, 0, FE_XMM0, FE_XMM2, FE_XMM1); +TEST("\x62\xf2\x6e\x20\xda\xc1", VSM4KEY4_256rrr, 0, FE_XMM0, FE_XMM18, FE_XMM1); +TEST("\x62\xf2\x6e\x48\xda\xc1", VSM4KEY4_512rrr, 0, FE_XMM0, FE_XMM2, FE_XMM1); +TEST("\x62\xf2\x6e\x40\xda\xc1", VSM4KEY4_512rrr, 0, FE_XMM0, FE_XMM18, FE_XMM1); +TEST("\xc4\xe2\x6b\xda\xc1", VSM4RNDS4_128rrr, 0, FE_XMM0, FE_XMM2, FE_XMM1); +TEST("\x62\xf2\x6f\x00\xda\xc1", VSM4RNDS4_128rrr, 0, FE_XMM0, FE_XMM18, FE_XMM1); +TEST("\xc4\xe2\x6f\xda\xc1", VSM4RNDS4_256rrr, 0, FE_XMM0, FE_XMM2, FE_XMM1); +TEST("\x62\xf2\x6f\x20\xda\xc1", VSM4RNDS4_256rrr, 0, FE_XMM0, FE_XMM18, FE_XMM1); +TEST("\x62\xf2\x6f\x48\xda\xc1", VSM4RNDS4_512rrr, 0, FE_XMM0, FE_XMM2, FE_XMM1); +TEST("\x62\xf2\x6f\x40\xda\xc1", VSM4RNDS4_512rrr, 0, FE_XMM0, FE_XMM18, FE_XMM1); diff --git a/third_party/fadec/encode.c b/third_party/fadec/encode.c new file mode 100644 index 0000000..abc57b0 --- /dev/null +++ b/third_party/fadec/encode.c @@ -0,0 +1,460 @@ + +#include +#include +#include + +#include + + +#ifdef __GNUC__ +#define LIKELY(x) __builtin_expect((x), 1) +#define UNLIKELY(x) __builtin_expect((x), 0) +#else +#define LIKELY(x) (x) +#define UNLIKELY(x) (x) +#endif + +#define OPC_66 0x80000 +#define OPC_F2 0x100000 +#define OPC_F3 0x200000 +#define OPC_REXW 0x400000 +#define OPC_LOCK 0x800000 +#define OPC_VEXL0 0x1000000 +#define OPC_VEXL1 0x1800000 +#define OPC_EVEXL0 0x2000000 +#define OPC_EVEXL1 0x2800000 +#define OPC_EVEXL2 0x3000000 +#define OPC_EVEXL3 0x3800000 +#define OPC_EVEXB 0x4000000 +#define OPC_VSIB 0x8000000 +#define OPC_67 FE_ADDR32 +#define OPC_SEG_MSK 0xe0000000 +#define OPC_JMPL FE_JMPL +#define OPC_MASK_MSK 0xe00000000 +#define OPC_EVEXZ 0x1000000000 +#define OPC_USER_MSK (OPC_67|OPC_SEG_MSK|OPC_MASK_MSK) +#define OPC_FORCE_SIB 0x2000000000 +#define OPC_DOWNGRADE_VEX 0x4000000000 +#define OPC_DOWNGRADE_VEX_FLIPW 0x40000000000 +#define OPC_EVEX_DISP8SCALE 0x38000000000 +#define OPC_GPH_OP0 0x200000000000 +#define OPC_GPH_OP1 0x400000000000 + +#define EPFX_REX_MSK 0x43f +#define EPFX_REX 0x20 +#define EPFX_EVEX 0x40 +#define EPFX_REXR 0x10 +#define EPFX_REXX 0x08 +#define EPFX_REXB 0x04 +#define EPFX_REXR4 0x02 +#define EPFX_REXB4 0x01 +#define EPFX_REXX4 0x400 +#define EPFX_VVVV_IDX 11 + +static bool op_mem(FeOp op) { return op < 0; } +static bool op_reg(FeOp op) { return op >= 0; } +static bool op_reg_gpl(FeOp op) { return (op & ~0x1f) == 0x100; } +static bool op_reg_gph(FeOp op) { return (op & ~0x3) == 0x204; } +static bool op_reg_xmm(FeOp op) { return (op & ~0x1f) == 0x600; } +static int64_t op_mem_offset(FeOp op) { return (int32_t) op; } +static unsigned op_mem_base(FeOp op) { return (op >> 32) & 0xfff; } +static unsigned op_mem_idx(FeOp op) { return (op >> 44) & 0xfff; } +static unsigned op_mem_scale(FeOp op) { return (op >> 56) & 0xf; } +static unsigned op_reg_idx(FeOp op) { return op & 0xff; } +static bool op_imm_n(FeOp imm, unsigned immsz) { + if (immsz == 0 && !imm) return true; + if (immsz == 1 && (int8_t) imm == imm) return true; + if (immsz == 2 && (int16_t) imm == imm) return true; + if (immsz == 3 && (imm&0xffffff) == imm) return true; + if (immsz == 4 && (int32_t) imm == imm) return true; + if (immsz == 8 && (int64_t) imm == imm) return true; + return false; +} + +static +unsigned +opc_size(uint64_t opc, uint64_t epfx) +{ + unsigned res = 1; + if (UNLIKELY(opc & OPC_EVEXL0)) { + res += 4; + } else if (UNLIKELY(opc & OPC_VEXL0)) { + if (opc & (OPC_REXW|0x20000) || epfx & (EPFX_REXX|EPFX_REXB)) + res += 3; + else + res += 2; + } else { + if (opc & OPC_LOCK) res++; + if (opc & OPC_66) res++; + if (opc & (OPC_F2|OPC_F3)) res++; + if (opc & OPC_REXW || epfx & EPFX_REX_MSK) res++; + if (opc & 0x30000) res++; + if (opc & 0x20000) res++; + } + if (opc & OPC_SEG_MSK) res++; + if (opc & OPC_67) res++; + if (opc & 0x8000) res++; + return res; +} + +static +int +enc_opc(uint8_t** restrict buf, uint64_t opc, uint64_t epfx) +{ + if (opc & OPC_SEG_MSK) + *(*buf)++ = (0x65643e362e2600 >> (8 * ((opc >> 29) & 7))) & 0xff; + if (opc & OPC_67) *(*buf)++ = 0x67; + if (opc & OPC_EVEXL0) { + *(*buf)++ = 0x62; + unsigned b1 = opc >> 16 & 7; + if (!(epfx & EPFX_REXR)) b1 |= 0x80; + if (!(epfx & EPFX_REXX)) b1 |= 0x40; + if (!(epfx & EPFX_REXB)) b1 |= 0x20; + if (!(epfx & EPFX_REXR4)) b1 |= 0x10; + if ((epfx & EPFX_REXB4)) b1 |= 0x08; + *(*buf)++ = b1; + unsigned b2 = opc >> 20 & 3; + if (!(epfx & EPFX_REXX4)) b2 |= 0x04; + b2 |= (~(epfx >> EPFX_VVVV_IDX) & 0xf) << 3; + if (opc & OPC_REXW) b2 |= 0x80; + *(*buf)++ = b2; + unsigned b3 = opc >> 33 & 7; + b3 |= (~(epfx >> EPFX_VVVV_IDX) & 0x10) >> 1; + if (opc & OPC_EVEXB) b3 |= 0x10; + b3 |= (opc >> 23 & 3) << 5; + if (opc & OPC_EVEXZ) b3 |= 0x80; + *(*buf)++ = b3; + } else if (opc & OPC_VEXL0) { + if (epfx & (EPFX_REXR4|EPFX_REXX4|EPFX_REXB4|(0x10<> 20 & 3; + *(*buf)++ = 0xc4 | !vex3; + unsigned b2 = pp | (opc & 0x800000 ? 0x4 : 0); + if (vex3) { + unsigned b1 = opc >> 16 & 7; + if (!(epfx & EPFX_REXR)) b1 |= 0x80; + if (!(epfx & EPFX_REXX)) b1 |= 0x40; + if (!(epfx & EPFX_REXB)) b1 |= 0x20; + *(*buf)++ = b1; + if (opc & OPC_REXW) b2 |= 0x80; + } else { + if (!(epfx & EPFX_REXR)) b2 |= 0x80; + } + b2 |= (~(epfx >> EPFX_VVVV_IDX) & 0xf) << 3; + *(*buf)++ = b2; + } else { + if (opc & OPC_LOCK) *(*buf)++ = 0xF0; + if (opc & OPC_66) *(*buf)++ = 0x66; + if (opc & OPC_F2) *(*buf)++ = 0xF2; + if (opc & OPC_F3) *(*buf)++ = 0xF3; + if (opc & OPC_REXW || epfx & (EPFX_REX_MSK)) { + unsigned rex = 0x40; + if (opc & OPC_REXW) rex |= 8; + if (epfx & EPFX_REXR) rex |= 4; + if (epfx & EPFX_REXX) rex |= 2; + if (epfx & EPFX_REXB) rex |= 1; + *(*buf)++ = rex; + } + if (opc & 0x30000) *(*buf)++ = 0x0F; + if ((opc & 0x30000) == 0x20000) *(*buf)++ = 0x38; + if ((opc & 0x30000) == 0x30000) *(*buf)++ = 0x3A; + } + *(*buf)++ = opc & 0xff; + if (opc & 0x8000) *(*buf)++ = (opc >> 8) & 0xff; + return 0; +} + +static +int +enc_imm(uint8_t** restrict buf, uint64_t imm, unsigned immsz) +{ + if (!op_imm_n(imm, immsz)) return -1; + for (unsigned i = 0; i < immsz; i++) + *(*buf)++ = imm >> 8 * i; + return 0; +} + +static +int +enc_o(uint8_t** restrict buf, uint64_t opc, uint64_t epfx, uint64_t op0) +{ + if (op_reg_idx(op0) & 0x8) epfx |= EPFX_REXB; + + // NB: this cannot happen. There is only one O-encoded instruction which + // accepts high-byte registers (b0+/MOVABS Rb,Ib), which will never have a + // REx prefix if the operand is a high-byte register. + // bool has_rex = opc & OPC_REXW || epfx & EPFX_REX_MSK; + // if (has_rex && op_reg_gph(op0)) return -1; + + if (enc_opc(buf, opc, epfx)) return -1; + *(*buf - 1) = (*(*buf - 1) & 0xf8) | (op_reg_idx(op0) & 0x7); + return 0; +} + +static +int +enc_mr(uint8_t** restrict buf, uint64_t opc, uint64_t epfx, uint64_t op0, + uint64_t op1, unsigned immsz) +{ + // If !op_reg(op1), it is a constant value for ModRM.reg + if (op_reg(op0) && (op_reg_idx(op0) & 0x8)) epfx |= EPFX_REXB; + if (op_reg(op0) && (op_reg_idx(op0) & 0x10)) + epfx |= 0 ? EPFX_REXB4 : EPFX_REXX|EPFX_EVEX; + if (op_mem(op0) && (op_mem_base(op0) & 0x8)) epfx |= EPFX_REXB; + if (op_mem(op0) && (op_mem_base(op0) & 0x10)) epfx |= EPFX_REXB4; + if (op_mem(op0) && (op_mem_idx(op0) & 0x8)) epfx |= EPFX_REXX; + if (op_mem(op0) && (op_mem_idx(op0) & 0x10)) + epfx |= opc & OPC_VSIB ? 0x10<> 39; + if (!(off & ((1 << disp8scale) - 1)) && op_imm_n(off >> disp8scale, 1)) { + mod = 0x40; + dispsz = 1; + off >>= disp8scale; + } else { + mod = 0x80; + dispsz = 4; + } + } else if (rm == 5) { + mod = 0x40; + dispsz = 1; + } + } + + if (opcsz + 1 + (rm == 4) + dispsz + immsz > 15) return -1; + + if (enc_opc(buf, opc, epfx)) return -1; + *(*buf)++ = mod | (reg << 3) | rm; + if (UNLIKELY(rm == 4)) + *(*buf)++ = (scale << 6) | (idx << 3) | base; + return enc_imm(buf, off, dispsz); +} + +typedef enum { + ENC_NP, ENC_M, ENC_R, ENC_M1, ENC_MC, ENC_MR, ENC_RM, ENC_RMA, ENC_MRC, + ENC_AM, ENC_MA, ENC_I, ENC_O, ENC_OA, ENC_S, ENC_A, ENC_D, ENC_FD, ENC_TD, + ENC_IM, + ENC_RVM, ENC_RVMR, ENC_RMV, ENC_VM, ENC_MVR, ENC_MRV, + ENC_MAX +} Encoding; + +struct EncodingInfo { + uint8_t modrm : 2; + uint8_t modreg : 2; + uint8_t vexreg : 2; + uint8_t immidx : 2; + // 0 = normal or jump, 1 = constant 1, 2 = address-size, 3 = RVMR + uint8_t immctl : 3; + uint8_t zregidx : 2; + uint8_t zregval : 1; +}; + +const struct EncodingInfo encoding_infos[ENC_MAX] = { + [ENC_NP] = { 0 }, + [ENC_M] = { .modrm = 0x0^3, .immidx = 1 }, + [ENC_R] = { .modreg = 0x0^3 }, + [ENC_M1] = { .modrm = 0x0^3, .immctl = 1, .immidx = 1 }, + [ENC_MC] = { .modrm = 0x0^3, .zregidx = 0x1^3, .zregval = 1 }, + [ENC_MR] = { .modrm = 0x0^3, .modreg = 0x1^3, .immidx = 2 }, + [ENC_RM] = { .modrm = 0x1^3, .modreg = 0x0^3, .immidx = 2 }, + [ENC_RMA] = { .modrm = 0x1^3, .modreg = 0x0^3, .zregidx = 0x2^3, .zregval = 0 }, + [ENC_MRC] = { .modrm = 0x0^3, .modreg = 0x1^3, .zregidx = 0x2^3, .zregval = 1 }, + [ENC_AM] = { .modrm = 0x1^3, .zregidx = 0x0^3, .zregval = 0 }, + [ENC_MA] = { .modrm = 0x0^3, .zregidx = 0x1^3, .zregval = 0 }, + [ENC_I] = { .immidx = 0 }, + [ENC_O] = { .modreg = 0x0^3, .immidx = 1 }, + [ENC_OA] = { .modreg = 0x0^3, .zregidx = 0x1^3, .zregval = 0 }, + [ENC_S] = { 0 }, + [ENC_A] = { .zregidx = 0x0^3, .zregval = 0, .immidx = 1 }, + [ENC_D] = { .immidx = 0 }, + [ENC_FD] = { .zregidx = 0x0^3, .zregval = 0, .immctl = 2, .immidx = 1 }, + [ENC_TD] = { .zregidx = 0x1^3, .zregval = 0, .immctl = 2, .immidx = 0 }, + [ENC_IM] = { .modrm = 0x1^3, .immidx = 0 }, + [ENC_RVM] = { .modrm = 0x2^3, .modreg = 0x0^3, .vexreg = 0x1^3, .immidx = 3 }, + [ENC_RVMR] = { .modrm = 0x2^3, .modreg = 0x0^3, .vexreg = 0x1^3, .immctl = 3, .immidx = 3 }, + [ENC_RMV] = { .modrm = 0x1^3, .modreg = 0x0^3, .vexreg = 0x2^3 }, + [ENC_VM] = { .modrm = 0x1^3, .vexreg = 0x0^3, .immidx = 2 }, + [ENC_MVR] = { .modrm = 0x0^3, .modreg = 0x2^3, .vexreg = 0x1^3 }, + [ENC_MRV] = { .modrm = 0x0^3, .modreg = 0x1^3, .vexreg = 0x2^3 }, +}; + +static const uint64_t alt_tab[] = { +#include +}; + +int +fe_enc64_impl(uint8_t** restrict buf, uint64_t opc, FeOp op0, FeOp op1, + FeOp op2, FeOp op3) +{ + uint8_t* buf_start = *buf; + uint64_t ops[4] = {op0, op1, op2, op3}; + + uint64_t epfx = 0; + // Doesn't change between variants + if ((opc & OPC_GPH_OP0) && op_reg_gpl(op0) && op0 >= FE_SP) + epfx |= EPFX_REX; + else if (!(opc & OPC_GPH_OP0) && op_reg_gph(op0)) + goto fail; + if ((opc & OPC_GPH_OP1) && op_reg_gpl(op1) && op1 >= FE_SP) + epfx |= EPFX_REX; + else if (!(opc & OPC_GPH_OP1) && op_reg_gph(op1)) + goto fail; + +try_encode:; + unsigned enc = (opc >> 51) & 0x1f; + const struct EncodingInfo* ei = &encoding_infos[enc]; + + int64_t imm = 0xcc; + unsigned immsz = (opc >> 47) & 0xf; + + if (UNLIKELY(ei->zregidx && op_reg_idx(ops[ei->zregidx^3]) != ei->zregval)) + goto next; + + if (UNLIKELY(enc == ENC_S)) { + if ((op_reg_idx(op0) << 3 & 0x20) != (opc & 0x20)) goto next; + opc |= op_reg_idx(op0) << 3; + } + + if (immsz) { + imm = ops[ei->immidx]; + if (UNLIKELY(ei->immctl)) { + if (ei->immctl == 2) { + immsz = UNLIKELY(opc & OPC_67) ? 4 : 8; + if (immsz == 4) imm = (int32_t) imm; // address are zero-extended + } else if (ei->immctl == 3) { + if (!op_reg_xmm(imm)) goto fail; + imm = op_reg_idx(imm) << 4; + if (!op_imm_n(imm, 1)) goto fail; + } else if (ei->immctl == 1) { + if (imm != 1) goto next; + immsz = 0; + } + } else if (enc == ENC_D) { + imm -= (int64_t) *buf + opc_size(opc, epfx) + immsz; + bool has_alt = opc >> 56 != 0; + bool skip_to_alt = has_alt && UNLIKELY(opc & FE_JMPL); + if (skip_to_alt || !op_imm_n(imm, immsz)) { + if (!has_alt) goto fail; + // JMP/Jcc special case + immsz = 4; + if (opc & 0x80) { // JMP + opc -= 2; // Convert opcode 0xeb to 0xe9 + imm -= 3; // 3 extra immediate bytes + } else { // Jcc + opc += 0x10010; // Add 0f escape + 0x10 to opcode + imm -= 4; // 0f escape + 3 extra immediate bytes + } + if (!op_imm_n(imm, immsz)) goto fail; + } + } else { + if (!op_imm_n(imm, immsz)) goto next; + } + } + + // NOP has no operands, so this must be the 32-bit OA XCHG + if ((opc & 0xfffffff) == 0x90 && ops[0] == FE_AX) goto next; + + if (UNLIKELY(enc == ENC_R)) { + if (enc_mr(buf, opc, epfx, 0, ops[0], immsz)) goto fail; + } else if (ei->modrm) { + FeOp modreg = ei->modreg ? ops[ei->modreg^3] : (opc & 0xff00) >> 8; + if (ei->vexreg) + epfx |= ((uint64_t) op_reg_idx(ops[ei->vexreg^3])) << EPFX_VVVV_IDX; + // Can fail for upgrade to EVEX due to high register numbers + if (enc_mr(buf, opc, epfx, ops[ei->modrm^3], modreg, immsz)) goto next; + } else if (ei->modreg) { + if (enc_o(buf, opc, epfx, ops[ei->modreg^3])) goto fail; + } else { + if (enc_opc(buf, opc, epfx)) goto fail; + } + + if (immsz) + if (enc_imm(buf, imm, immsz)) goto fail; + + return 0; + +next:; + uint64_t alt = opc >> 56; + if (alt) { // try alternative encoding, if available + opc = alt_tab[alt] | (opc & OPC_USER_MSK); + goto try_encode; + } + +fail: + // Don't advance buffer on error; though we shouldn't write anything. + *buf = buf_start; + return -1; +} diff --git a/third_party/fadec/encode2-test.c b/third_party/fadec/encode2-test.c new file mode 100644 index 0000000..c807f47 --- /dev/null +++ b/third_party/fadec/encode2-test.c @@ -0,0 +1,64 @@ + +#include +#include +#include +#include + +#include + + +static +void print_hex(const uint8_t* buf, size_t len) { + for (size_t i = 0; i < len; i++) + printf("%02x", buf[i]); +} + +static int +check(const uint8_t* buf, const void* exp, size_t exp_len, unsigned res, const char* name) { + if (res == exp_len && !memcmp(buf, exp, exp_len)) + return 0; + printf("Failed case (new) %s:\n", name); + printf(" Exp (%2zu): ", exp_len); + print_hex((const uint8_t*)exp, exp_len); + printf("\n Got (%2u): ", res); + print_hex(buf, res); + printf("\n"); + return -1; +} + +#define TEST1(str, exp, name, ...) do { \ + memset(buf, 0, sizeof buf); \ + unsigned res = fe64_ ## name(buf, __VA_ARGS__); \ + failed |= check(buf, exp, sizeof(exp) - 1, res, str); \ + } while (0) +#define TEST(exp, ...) TEST1(#__VA_ARGS__, exp, __VA_ARGS__) + +int +main(void) { + int failed = 0; + uint8_t buf[16]; + + // This API is type safe and prohibits compilation of reg-type mismatches +#define ENC_TEST_TYPESAFE + // Silence -Warray-bounds with double cast +#define FE_PTR(off) (const void*) ((uintptr_t) buf + (off)) +#define FLAGMASK(flags, mask) flags, mask +#include "encode-test.inc" + + TEST("\x90", NOP, 0); + TEST("\x90", NOP, 1); + TEST("\x66\x90", NOP, 2); + TEST("\x0f\x1f\x00", NOP, 3); + TEST("\x0f\x1f\x40\x00", NOP, 4); + TEST("\x0f\x1f\x44\x00\x00", NOP, 5); + TEST("\x66\x0f\x1f\x44\x00\x00", NOP, 6); + TEST("\x0f\x1f\x80\x00\x00\x00\x00", NOP, 7); + TEST("\x0f\x1f\x84\x00\x00\x00\x00\x00", NOP, 8); + TEST("\x66\x0f\x1f\x84\x00\x00\x00\x00\x00", NOP, 9); + TEST("\x66\x0f\x1f\x84\x00\x00\x00\x00\x00\x90", NOP, 10); + TEST("\x66\x0f\x1f\x84\x00\x00\x00\x00\x00\x66\x90", NOP, 11); + TEST("\x66\x0f\x1f\x84\x00\x00\x00\x00\x00\x0f\x1f\x00", NOP, 12); + + puts(failed ? "Some tests FAILED" : "All tests PASSED"); + return failed ? EXIT_FAILURE : EXIT_SUCCESS; +} diff --git a/third_party/fadec/encode2-test.cc b/third_party/fadec/encode2-test.cc new file mode 100644 index 0000000..78005f2 --- /dev/null +++ b/third_party/fadec/encode2-test.cc @@ -0,0 +1,64 @@ + +#include +#include +#include +#include + +#include + + +using Buffer = std::array; + +static +void print_hex(const uint8_t* buf, size_t len) { + for (size_t i = 0; i < len; i++) + std::printf("%02x", buf[i]); +} + +static int +check(const Buffer& buf, const char* exp, size_t exp_len, unsigned res, const char* name) { + if (res == exp_len && !std::memcmp(buf.data(), exp, exp_len)) + return 0; + std::printf("Failed case (new) %s:\n", name); + std::printf(" Exp (%2zu): ", exp_len); + print_hex(reinterpret_cast(exp), exp_len); + std::printf("\n Got (%2u): ", res); + print_hex(buf.data(), res); + std::printf("\n"); + return -1; +} + +#define TEST1(str, exp, name, ...) do { \ + buf.fill(0); \ + unsigned res = fe64_ ## name(buf.data(), __VA_ARGS__); \ + failed |= check(buf, exp, sizeof(exp) - 1, res, str); \ + } while (0) +#define TEST(exp, ...) TEST1(#__VA_ARGS__, exp, __VA_ARGS__) + +#define TEST_CPP1(str, exp, expr) do { \ + buf.fill(0); \ + unsigned res = (expr); \ + failed |= check(buf, exp, sizeof(exp) - 1, res, str); \ + } while (0) +#define TEST_CPP(exp, ...) TEST_CPP1(#__VA_ARGS__, exp, __VA_ARGS__) + +int main() { + int failed = 0; + Buffer buf{}; + + // This API is type safe and prohibits compilation of reg-type mismatches +#define ENC_TEST_TYPESAFE + // Silence -Warray-bounds with double cast +#define FE_PTR(off) (const void*) ((uintptr_t) buf.data() + (off)) +#define FLAGMASK(flags, mask) flags, mask +#include "encode-test.inc" + + // Test implicit conversion of parameters also on the actual functions + TEST_CPP("\x0f\x90\xc0", fe64_SETO8r(buf.data(), 0, FE_AX)); + TEST_CPP("\x0f\x90\xc0", (fe64_SETO8r)(buf.data(), 0, FE_AX)); + TEST_CPP("\x0f\x90\xc4", fe64_SETO8r(buf.data(), 0, FE_AH)); + TEST_CPP("\x0f\x90\xc4", (fe64_SETO8r)(buf.data(), 0, FE_AH)); + + std::puts(failed ? "Some tests FAILED" : "All tests PASSED"); + return failed ? EXIT_FAILURE : EXIT_SUCCESS; +} diff --git a/third_party/fadec/encode2.c b/third_party/fadec/encode2.c new file mode 100644 index 0000000..0a318c8 --- /dev/null +++ b/third_party/fadec/encode2.c @@ -0,0 +1,345 @@ + +#include +#include +#include + +#include + + +#ifdef __GNUC__ +#define LIKELY(x) __builtin_expect(!!(x), 1) +#define UNLIKELY(x) __builtin_expect(!!(x), 0) +#if __has_attribute(cold) && __has_attribute(preserve_most) +#define HINT_COLD __attribute__((cold,preserve_most,noinline)) +#elif __has_attribute(cold) +#define HINT_COLD __attribute__((cold,noinline)) +#else +#define HINT_COLD +#endif +#else +#define LIKELY(x) (x) +#define UNLIKELY(x) (x) +#define HINT_COLD +#endif + +#define op_reg_idx(op) (op).idx +#define op_reg_gph(op) (((op).idx & ~0x3) == 0x24) +#define op_mem_base(mem) op_reg_idx((mem).base) +#define op_mem_idx(mem) op_reg_idx((mem).idx) + +static bool +op_imm_n(int64_t imm, unsigned immsz) { + if (immsz == 0 && !imm) return true; + if (immsz == 1 && (int8_t) imm == imm) return true; + if (immsz == 2 && (int16_t) imm == imm) return true; + if (immsz == 3 && (imm&0xffffff) == imm) return true; + if (immsz == 4 && (int32_t) imm == imm) return true; + if (immsz == 8 && (int64_t) imm == imm) return true; + return false; +} + +HINT_COLD static unsigned +enc_seg67(uint8_t* buf, unsigned flags) { + unsigned idx = 0; + if (UNLIKELY(flags & FE_SEG_MASK)) { + unsigned seg = (0x65643e362e2600 >> (8 * (flags & FE_SEG_MASK))) & 0xff; + buf[idx++] = seg; + } + if (UNLIKELY(flags & FE_ADDR32)) buf[idx++] = 0x67; + return idx; +} + +static unsigned +enc_rex_mem(FeMem op0, uint64_t op1) { + // Essentially just an and+or due to struct layout. + uint32_t val = op1 | op0.flags | (op_mem_base(op0) << 8) | + ((uint32_t)op_mem_idx(op0) << 24); + // Combine REX.RXB using multiplication for branch-less code. + uint32_t masked = val & 0x08000808; + return masked ? (uint8_t) (masked * (1|(1<<15)|(1<<25)) >> 26) + 0x40 : 0; +} + +static void +enc_imm(uint8_t* buf, uint64_t imm, unsigned immsz) { +#ifdef __GNUC__ + // Clang doesn't fold the loop into a single store. + // See: https://github.com/llvm/llvm-project/issues/154696 + if (__builtin_constant_p(immsz)) { + __builtin_memcpy(buf, &imm, immsz); + return; + } +#endif + for (unsigned i = 0; i < immsz; i++) + *buf++ = imm >> 8 * i; +} + +static int +enc_mem_common(uint8_t* buf, unsigned ripoff, FeMem op0, uint64_t op1, + unsigned disp8scale) { + int mod = 0, reg = op1 & 7, rm; + unsigned sib = 0x20; + bool withsib = false; + unsigned dispsz = 0; + int32_t off = op0.off; + + if (op_reg_idx(op0.idx) < 0x80) { + int scalabs = op0.scale; + if (UNLIKELY((unsigned) (op0.scale - 1) >= 8 || + (op0.scale & (op0.scale - 1)))) + return 0; + unsigned scale = (scalabs & 0xA ? 1 : 0) | (scalabs & 0xC ? 2 : 0); + sib = scale << 6 | (op_reg_idx(op0.idx) & 7) << 3; + withsib = true; + } else if (UNLIKELY(op0.scale != 0)) { + return 0; + } + + if (UNLIKELY(op0.base.idx >= 0x20)) { + if (UNLIKELY(op0.base.idx >= op_reg_idx(FE_NOREG))) { + *buf++ = (reg << 3) | 4; + *buf++ = sib | 5; + enc_imm(buf, off, 4); + return ripoff + 6; + } else if (LIKELY(op0.base.idx == FE_IP.idx)) { + if (withsib) + return 0; + *buf++ = (reg << 3) | 5; + // Adjust offset, caller doesn't know instruction length. + enc_imm(buf, off - ripoff - 5, 4); + return ripoff + 5; + } else { + return 0; + } + } + + rm = op_reg_idx(op0.base) & 7; + + if (off) { + if (LIKELY(!disp8scale)) { + mod = (int8_t) off == off ? 0x40 : 0x80; + dispsz = (int8_t) off == off ? 1 : 4; + } else { + if (!(off & ((1 << disp8scale) - 1)) && op_imm_n(off >> disp8scale, 1)) + off >>= disp8scale, mod = 0x40, dispsz = 1; + else + mod = 0x80, dispsz = 4; + } + } else if (rm == 5) { + dispsz = 1; + mod = 0x40; + } + + // Always write four bytes of displacement. The buffer is always large + // enough, and we truncate by returning a smaller "written bytes" count. + if (withsib || rm == 4) { + *buf++ = mod | (reg << 3) | 4; + *buf++ = sib | rm; + enc_imm(buf, off, 4); + return ripoff + 2 + dispsz; + } else { + *buf++ = mod | (reg << 3) | rm; + enc_imm(buf, off, 4); + return ripoff + 1 + dispsz; + } +} + +static int +enc_mem(uint8_t* buf, unsigned ripoff, FeMem op0, uint64_t op1, bool forcesib, + unsigned disp8scale) { + if (UNLIKELY(op_reg_idx(op0.idx) == 4)) + return 0; + if (forcesib && op_reg_idx(op0.idx) == op_reg_idx(FE_NOREG)) { + op0.scale = 1; + op0.idx = FE_GP(4); + } + return enc_mem_common(buf, ripoff, op0, op1, disp8scale); +} + +static int +enc_mem_vsib(uint8_t* buf, unsigned ripoff, FeMemV op0, uint64_t op1, + bool forcesib, unsigned disp8scale) { + (void) forcesib; + FeMem mem = FE_MEM(op0.base, op0.scale, FE_GP(op_reg_idx(op0.idx)), op0.off); + return enc_mem_common(buf, ripoff, mem, op1, disp8scale); +} + +// EVEX/VEX "Opcode" format: +// +// | EVEX byte 4 | P P M M M - - W | Opcode byte | VEX-D VEX-D-FLIPW +// 0 8 16 24 + +enum { + FE_OPC_VEX_WPP_SHIFT = 8, + FE_OPC_VEX_WPP_MASK = 0x83 << FE_OPC_VEX_WPP_SHIFT, + FE_OPC_VEX_MMM_SHIFT = 10, + FE_OPC_VEX_MMM_MASK = 0x1f << FE_OPC_VEX_MMM_SHIFT, + FE_OPC_VEX_DOWNGRADE_VEX = 1 << 24, + FE_OPC_VEX_DOWNGRADE_VEX_FLIPW = 1 << 25, +}; + +static int +enc_vex_common(uint8_t* buf, unsigned opcode, unsigned base, + unsigned idx, unsigned reg, unsigned vvvv) { + if ((base | idx | reg | vvvv) & 0x10) return 0; + bool vex3 = ((base | idx) & 0x08) || (opcode & 0xfc00) != 0x0400; + if (vex3) { + *buf++ = 0xc4; + unsigned b1 = (opcode & FE_OPC_VEX_MMM_MASK) >> FE_OPC_VEX_MMM_SHIFT; + if (!(reg & 0x08)) b1 |= 0x80; + if (!(idx & 0x08)) b1 |= 0x40; + if (!(base & 0x08)) b1 |= 0x20; + *buf++ = b1; + unsigned b2 = (opcode & FE_OPC_VEX_WPP_MASK) >> FE_OPC_VEX_WPP_SHIFT; + if (opcode & 0x20) b2 |= 0x04; + b2 |= (vvvv ^ 0xf) << 3; + *buf++ = b2; + } else { + *buf++ = 0xc5; + unsigned b2 = opcode >> FE_OPC_VEX_WPP_SHIFT & 3; + if (opcode & 0x20) b2 |= 0x04; + if (!(reg & 0x08)) b2 |= 0x80; + b2 |= (vvvv ^ 0xf) << 3; + *buf++ = b2; + } + *buf++ = (opcode & 0xff0000) >> 16; + return 3 + vex3; +} + +static int +enc_vex_reg(uint8_t* buf, unsigned opcode, uint64_t rm, uint64_t reg, + uint64_t vvvv) { + unsigned off = enc_vex_common(buf, opcode, rm, 0, reg, vvvv); + buf[off] = 0xc0 | (reg << 3 & 0x38) | (rm & 7); + return off ? off + 1 : 0; +} + +static int +enc_vex_mem(uint8_t* buf, unsigned opcode, FeMem rm, uint64_t reg, + uint64_t vvvv, unsigned ripoff, bool forcesib, unsigned disp8scale) { + unsigned off = enc_vex_common(buf, opcode, op_reg_idx(rm.base), op_reg_idx(rm.idx), reg, vvvv); + unsigned memoff = enc_mem(buf + off, ripoff + off, rm, reg, forcesib, disp8scale); + return off && memoff ? memoff : 0; +} + +static int +enc_vex_vsib(uint8_t* buf, unsigned opcode, FeMemV rm, uint64_t reg, + uint64_t vvvv, unsigned ripoff, bool forcesib, unsigned disp8scale) { + unsigned off = enc_vex_common(buf, opcode, op_reg_idx(rm.base), op_reg_idx(rm.idx), reg, vvvv); + unsigned memoff = enc_mem_vsib(buf + off, ripoff + off, rm, reg, forcesib, disp8scale); + return off && memoff ? memoff : 0; +} + +static int +enc_evex_common(uint8_t* buf, unsigned opcode, unsigned base, + unsigned idx, unsigned reg, unsigned vvvv) { + *buf++ = 0x62; + bool evexr3 = reg & 0x08; + bool evexr4 = reg & 0x10; + bool evexb3 = base & 0x08; + bool evexb4 = base & 0x10; // evexb4 is unused in AVX-512 encoding + bool evexx3 = idx & 0x08; + bool evexx4 = idx & 0x10; + bool evexv4 = vvvv & 0x10; + unsigned b1 = (opcode & FE_OPC_VEX_MMM_MASK) >> FE_OPC_VEX_MMM_SHIFT; + if (!evexr3) b1 |= 0x80; + if (!evexx3) b1 |= 0x40; + if (!evexb3) b1 |= 0x20; + if (!evexr4) b1 |= 0x10; + if (evexb4) b1 |= 0x08; + *buf++ = b1; + unsigned b2 = (opcode & FE_OPC_VEX_WPP_MASK) >> FE_OPC_VEX_WPP_SHIFT; + if (!evexx4) b2 |= 0x04; + b2 |= (~vvvv & 0xf) << 3; + *buf++ = b2; + unsigned b3 = opcode & 0xff; + if (!evexv4) b3 |= 0x08; + *buf++ = b3; + *buf++ = (opcode & 0xff0000) >> 16; + return 5; +} + +static unsigned +enc_evex_to_vex(unsigned opcode) { + return opcode & FE_OPC_VEX_DOWNGRADE_VEX_FLIPW ? opcode ^ 0x8000 : opcode; +} + +// Encode AVX-512 EVEX r/m-reg, non-xmm reg, vvvv, prefer vex +static int +enc_evex_reg(uint8_t* buf, unsigned opcode, unsigned rm, + unsigned reg, unsigned vvvv) { + unsigned off; + if (!((rm | reg | vvvv) & 0x10) && (opcode & FE_OPC_VEX_DOWNGRADE_VEX)) + off = enc_vex_common(buf, enc_evex_to_vex(opcode), rm, 0, reg, vvvv); + else + off = enc_evex_common(buf, opcode, rm, 0, reg, vvvv); + buf[off] = 0xc0 | (reg << 3 & 0x38) | (rm & 7); + return off + 1; +} + +// Encode AVX-512 EVEX r/m-reg, xmm reg, vvvv, prefer vex +static int +enc_evex_xmm(uint8_t* buf, unsigned opcode, unsigned rm, + unsigned reg, unsigned vvvv) { + unsigned off; + if (!((rm | reg | vvvv) & 0x10) && (opcode & FE_OPC_VEX_DOWNGRADE_VEX)) + off = enc_vex_common(buf, enc_evex_to_vex(opcode), rm, 0, reg, vvvv); + else + // AVX-512 XMM reg encoding uses X3 instead of B4. + off = enc_evex_common(buf, opcode, rm & 0x0f, rm >> 1, reg, vvvv); + buf[off] = 0xc0 | (reg << 3 & 0x38) | (rm & 7); + return off + 1; +} + +static int +enc_evex_mem(uint8_t* buf, unsigned opcode, FeMem rm, uint64_t reg, + uint64_t vvvv, unsigned ripoff, bool forcesib, unsigned disp8scale) { + unsigned off; + if (!((op_reg_idx(rm.base) | op_reg_idx(rm.idx) | reg | vvvv) & 0x10) && + (opcode & FE_OPC_VEX_DOWNGRADE_VEX)) { + disp8scale = 0; // Only AVX-512 EVEX compresses displacement + off = enc_vex_common(buf, enc_evex_to_vex(opcode), op_reg_idx(rm.base), op_reg_idx(rm.idx), reg, vvvv); + } else { + off = enc_evex_common(buf, opcode, op_reg_idx(rm.base), op_reg_idx(rm.idx), reg, vvvv); + } + unsigned memoff = enc_mem(buf + off, ripoff + off, rm, reg, forcesib, disp8scale); + return off && memoff ? memoff : 0; +} + +static int +enc_evex_vsib(uint8_t* buf, unsigned opcode, FeMemV rm, uint64_t reg, + uint64_t vvvv, unsigned ripoff, bool forcesib, unsigned disp8scale) { + (void) vvvv; + // EVEX VSIB requires non-zero mask operand + if (!(opcode & 0x7)) return 0; + // EVEX.X4 is encoded in EVEX.V4 + unsigned idx = op_reg_idx(rm.idx); + unsigned off = enc_evex_common(buf, opcode, op_reg_idx(rm.base), idx & 0x0f, reg, idx & 0x10); + unsigned memoff = enc_mem_vsib(buf + off, ripoff + off, rm, reg, forcesib, disp8scale); + return off && memoff ? memoff : 0; +} + +unsigned fe64_NOP(uint8_t* buf, unsigned flags) { + unsigned len = flags ? flags : 1; + // Taken from Intel SDM + static const uint8_t tbl[] = { + 0x90, + 0x66, 0x90, + 0x0f, 0x1f, 0x00, + 0x0f, 0x1f, 0x40, 0x00, + 0x0f, 0x1f, 0x44, 0x00, 0x00, + 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00, + 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + unsigned remain = len; + for (; remain > 9; remain -= 9) + for (unsigned i = 0; i < 9; i++) + *(buf++) = tbl[36 + i]; + const uint8_t* src = tbl + (remain * (remain - 1)) / 2; + for (unsigned i = 0; i < remain; i++) + *(buf++) = src[i]; + return len; +} + +#include diff --git a/third_party/fadec/fadec-decode-private.inc b/third_party/fadec/fadec-decode-private.inc new file mode 100644 index 0000000..b31fe90 --- /dev/null +++ b/third_party/fadec/fadec-decode-private.inc @@ -0,0 +1,18 @@ +// Auto-generated file -- do not modify! +#if defined(FD_DECODE_TABLE_DATA) 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+#elif defined(FD_DECODE_TABLE_DESCS) +{0},{FDI_ADD, 2059, 1280, 16393},{FDI_ADD, 2059, 1034, 16393},{FDI_ADD, 14, 1280, 16393},{FDI_ADD, 14, 1034, 16393},{FDI_ADD, 20656, 1344, 64},{FDI_ADD, 16560, 1184, 64},{FDI_PUSH, 12, 1032, 24},{FDI_POP, 12, 1032, 24},{FDI_OR, 2059, 1280, 16393},{FDI_OR, 2059, 1034, 16393},{FDI_OR, 14, 1280, 16393},{FDI_OR, 14, 1034, 16393},{FDI_OR, 20656, 1344, 64},{FDI_OR, 16560, 1184, 64},{FDI_ADC, 2059, 1280, 16393},{FDI_ADC, 2059, 1034, 16393},{FDI_ADC, 14, 1280, 16393},{FDI_ADC, 14, 1034, 16393},{FDI_ADC, 20656, 1344, 64},{FDI_ADC, 16560, 1184, 64},{FDI_SBB, 2059, 1280, 16393},{FDI_SBB, 2059, 1034, 16393},{FDI_SBB, 14, 1280, 16393},{FDI_SBB, 14, 1034, 16393},{FDI_SBB, 20656, 1344, 64},{FDI_SBB, 16560, 1184, 64},{FDI_AND, 2059, 1280, 16393},{FDI_AND, 2059, 1034, 16393},{FDI_AND, 14, 1280, 16393},{FDI_AND, 14, 1034, 16393},{FDI_AND, 20656, 1344, 64},{FDI_AND, 16560, 1184, 64},{FDI_DAA, 0, 1024, 0},{FDI_SUB, 2059, 1280, 16393},{FDI_SUB, 2059, 1034, 16393},{FDI_SUB, 14, 1280, 16393},{FDI_SUB, 14, 1034, 16393},{FDI_SUB, 20656, 1344, 64},{FDI_SUB, 16560, 1184, 64},{FDI_DAS, 0, 1024, 0},{FDI_XOR, 2059, 1280, 16393},{FDI_XOR, 2059, 1034, 16393},{FDI_XOR, 14, 1280, 16393},{FDI_XOR, 14, 1034, 16393},{FDI_XOR, 20656, 1344, 64},{FDI_XOR, 16560, 1184, 64},{FDI_AAA, 0, 1024, 0},{FDI_CMP, 11, 1280, 16393},{FDI_CMP, 11, 1034, 16393},{FDI_CMP, 14, 1280, 16393},{FDI_CMP, 14, 1034, 16393},{FDI_CMP, 20656, 1344, 64},{FDI_CMP, 16560, 1184, 64},{FDI_AAS, 0, 1024, 0},{FDI_INC, 3, 1026, 1},{FDI_DEC, 3, 1026, 1},{FDI_PUSH, 3, 1026, 4097},{FDI_POP, 3, 1026, 4097},{FDI_PUSHA, 0, 34048, 0},{FDI_POPA, 0, 34048, 0},{FDI_BOUND, 14, 1034, 16392},{FDI_ARPL, 11, 2048, 16393},{FDI_MOVSX, 14, 3336, 16393},{FDI_PUSH, 16576, 1152, 4096},{FDI_IMUL, 16462, 1162, 16393},{FDI_PUSH, 20672, 1024, 4096},{FDI_IMUL, 20558, 1034, 16393},{FDI_INS, 0, 1280, 0},{FDI_INS, 0, 34048, 0},{FDI_OUTS, 0, 1280, 0},{FDI_OUTS, 0, 34048, 0},{FDI_JO, 28864, 1024, 6144},{FDI_JNO, 28864, 1024, 6144},{FDI_JC, 28864, 1024, 6144},{FDI_JNC, 28864, 1024, 6144},{FDI_JZ, 28864, 1024, 6144},{FDI_JNZ, 28864, 1024, 6144},{FDI_JBE, 28864, 1024, 6144},{FDI_JA, 28864, 1024, 6144},{FDI_JS, 28864, 1024, 6144},{FDI_JNS, 28864, 1024, 6144},{FDI_JP, 28864, 1024, 6144},{FDI_JNP, 28864, 1024, 6144},{FDI_JL, 28864, 1024, 6144},{FDI_JGE, 28864, 1024, 6144},{FDI_JLE, 28864, 1024, 6144},{FDI_JG, 28864, 1024, 6144},{FDI_ADD, 22659, 1344, 16385},{FDI_OR, 22659, 1344, 16385},{FDI_ADC, 22659, 1344, 16385},{FDI_SBB, 22659, 1344, 16385},{FDI_AND, 22659, 1344, 16385},{FDI_SUB, 22659, 1344, 16385},{FDI_XOR, 22659, 1344, 16385},{FDI_CMP, 20611, 1344, 16385},{FDI_ADD, 18563, 1154, 16385},{FDI_OR, 18563, 1154, 16385},{FDI_ADC, 18563, 1154, 16385},{FDI_SBB, 18563, 1154, 16385},{FDI_AND, 18563, 1154, 16385},{FDI_SUB, 18563, 1154, 16385},{FDI_XOR, 18563, 1154, 16385},{FDI_CMP, 16515, 1154, 16385},{FDI_ADD, 22659, 1026, 16385},{FDI_OR, 22659, 1026, 16385},{FDI_ADC, 22659, 1026, 16385},{FDI_SBB, 22659, 1026, 16385},{FDI_AND, 22659, 1026, 16385},{FDI_SUB, 22659, 1026, 16385},{FDI_XOR, 22659, 1026, 16385},{FDI_CMP, 20611, 1026, 16385},{FDI_TEST, 11, 1280, 16393},{FDI_TEST, 11, 1034, 16393},{FDI_XCHG, 2059, 1280, 16393},{FDI_XCHG, 2059, 1034, 16393},{FDI_MOV, 11, 1280, 16393},{FDI_MOV, 11, 1034, 16393},{FDI_MOV, 14, 1280, 16393},{FDI_MOV, 14, 1034, 16393},{FDI_MOV_S2G, 11, 2048, 16409},{FDI_LEA, 14, 8, 16392},{FDI_MOV_G2S, 14, 2048, 16409},{FDI_POP, 3, 1026, 20481},{FDI_XCHG_NOP, 35, 1314, 65},{FDI_C_EX, 0, 34048, 0},{FDI_C_SEP, 0, 34048, 0},{FDI_CALLF, 16576, 1152, 0},{FDI_FWAIT, 0, 1024, 0},{FDI_PUSHF, 0, 34048, 4096},{FDI_POPF, 0, 34048, 4096},{FDI_SAHF, 0, 1024, 0},{FDI_LAHF, 0, 1024, 0},{FDI_MOV, 8368, 1280, 64},{FDI_MOV, 8368, 1184, 64},{FDI_MOV, 8416, 1280, 64},{FDI_MOV, 8416, 1184, 64},{FDI_MOVS, 0, 1280, 0},{FDI_MOVS, 0, 34048, 0},{FDI_CMPS, 0, 1280, 0},{FDI_CMPS, 0, 34048, 0},{FDI_TEST, 20656, 1344, 64},{FDI_TEST, 16560, 1184, 64},{FDI_STOS, 0, 1280, 0},{FDI_STOS, 0, 34048, 0},{FDI_LODS, 0, 1280, 0},{FDI_LODS, 0, 34048, 0},{FDI_SCAS, 0, 1280, 0},{FDI_SCAS, 0, 34048, 0},{FDI_MOVABS, 20611, 1344, 1},{FDI_MOVABS, 16515, 1154, 1},{FDI_ROL, 20611, 1344, 16385},{FDI_ROR, 20611, 1344, 16385},{FDI_RCL, 20611, 1344, 16385},{FDI_RCR, 20611, 1344, 16385},{FDI_SHL, 20611, 1344, 16385},{FDI_SHR, 20611, 1344, 16385},{FDI_SAR, 20611, 1344, 16385},{FDI_ROL, 20611, 1090, 16385},{FDI_ROR, 20611, 1090, 16385},{FDI_RCL, 20611, 1090, 16385},{FDI_RCR, 20611, 1090, 16385},{FDI_SHL, 20611, 1090, 16385},{FDI_SHR, 20611, 1090, 16385},{FDI_SAR, 20611, 1090, 16385},{FDI_RET, 16576, 35072, 6144},{FDI_RET, 0, 34048, 6144},{FDI_LES, 14, 1034, 16392},{FDI_LDS, 14, 1034, 16392},{FDI_MOV, 20611, 1344, 16385},{FDI_XABORT, 20672, 1088, 16384},{FDI_MOV, 16515, 1154, 16385},{FDI_XBEGIN, 24768, 3072, 16384},{FDI_XBEGIN, 24768, 4096, 16384},{FDI_ENTER, 16576, 36096, 4096},{FDI_LEAVE, 0, 34048, 4096},{FDI_RETF, 16576, 35072, 0},{FDI_RETF, 0, 34048, 0},{FDI_INT3, 0, 1024, 0},{FDI_INT, 20672, 1088, 0},{FDI_INTO, 0, 1024, 0},{FDI_IRET, 0, 34048, 0},{FDI_ROL, 4227, 1280, 16385},{FDI_ROR, 4227, 1280, 16385},{FDI_RCL, 4227, 1280, 16385},{FDI_RCR, 4227, 1280, 16385},{FDI_SHL, 4227, 1280, 16385},{FDI_SHR, 4227, 1280, 16385},{FDI_SAR, 4227, 1280, 16385},{FDI_ROL, 4227, 1026, 16385},{FDI_ROR, 4227, 1026, 16385},{FDI_RCL, 4227, 1026, 16385},{FDI_RCR, 4227, 1026, 16385},{FDI_SHL, 4227, 1026, 16385},{FDI_SHR, 4227, 1026, 16385},{FDI_SAR, 4227, 1026, 16385},{FDI_ROL, 1059, 1280, 16449},{FDI_ROR, 1059, 1280, 16449},{FDI_RCL, 1059, 1280, 16449},{FDI_RCR, 1059, 1280, 16449},{FDI_SHL, 1059, 1280, 16449},{FDI_SHR, 1059, 1280, 16449},{FDI_SAR, 1059, 1280, 16449},{FDI_ROL, 1059, 1026, 16449},{FDI_ROR, 1059, 1026, 16449},{FDI_RCL, 1059, 1026, 16449},{FDI_RCR, 1059, 1026, 16449},{FDI_SHL, 1059, 1026, 16449},{FDI_SHR, 1059, 1026, 16449},{FDI_SAR, 1059, 1026, 16449},{FDI_AAM, 20672, 1344, 0},{FDI_AAD, 20672, 1344, 0},{FDI_XLATB, 0, 1024, 0},{FDI_LOOPNZ, 28864, 1024, 6144},{FDI_LOOPZ, 28864, 1024, 6144},{FDI_LOOP, 28864, 1024, 6144},{FDI_JCXZ, 28864, 1024, 6144},{FDI_IN, 20656, 1344, 64},{FDI_IN, 20656, 1120, 64},{FDI_OUT, 20656, 1344, 64},{FDI_OUT, 20656, 1120, 64},{FDI_CALL, 24768, 1152, 6144},{FDI_JMP, 24768, 1152, 6144},{FDI_JMPF, 16576, 1152, 0},{FDI_JMP, 28864, 1024, 6144},{FDI_IN, 0, 1280, 0},{FDI_IN, 0, 34048, 0},{FDI_OUT, 0, 1280, 0},{FDI_OUT, 0, 34048, 0},{FDI_INT1, 0, 1024, 0},{FDI_HLT, 0, 1024, 0},{FDI_CMC, 0, 1024, 0},{FDI_TEST, 20611, 1344, 16385},{FDI_NOT, 2051, 1280, 16385},{FDI_NEG, 2051, 1280, 16385},{FDI_MUL, 3, 1280, 16385},{FDI_IMUL, 3, 1280, 16385},{FDI_DIV, 3, 1280, 16385},{FDI_IDIV, 3, 1280, 16385},{FDI_TEST, 16515, 1154, 16385},{FDI_NOT, 2051, 1026, 16385},{FDI_NEG, 2051, 1026, 16385},{FDI_MUL, 3, 1026, 16385},{FDI_IMUL, 3, 1026, 16385},{FDI_DIV, 3, 1026, 16385},{FDI_IDIV, 3, 1026, 16385},{FDI_CLC, 0, 1024, 0},{FDI_STC, 0, 1024, 0},{FDI_CLI, 0, 1024, 0},{FDI_STI, 0, 1024, 0},{FDI_CLD, 0, 1024, 0},{FDI_STD, 0, 1024, 0},{FDI_INC, 2051, 1280, 16385},{FDI_DEC, 2051, 1280, 16385},{FDI_INC, 2051, 1026, 16385},{FDI_DEC, 2051, 1026, 16385},{FDI_CALL, 3, 1026, 22529},{FDI_CALLF, 3, 1026, 16384},{FDI_JMP, 3, 1026, 22529},{FDI_JMPF, 3, 1026, 16384},{FDI_PUSH, 3, 1026, 20481},{FDI_SLDT, 3, 2048, 16385},{FDI_STR, 3, 2048, 16385},{FDI_LLDT, 3, 2048, 16385},{FDI_LTR, 3, 2048, 16385},{FDI_VERR, 3, 2048, 16385},{FDI_VERW, 3, 2048, 16385},{FDI_SGDT, 3, 0, 16384},{FDI_SIDT, 3, 0, 16384},{FDI_LGDT, 3, 0, 16384},{FDI_LIDT, 3, 0, 16384},{FDI_SMSW, 3, 2048, 16384},{FDI_SMSW, 3, 1026, 16385},{FDI_LMSW, 3, 2048, 16385},{FDI_INVLPG, 3, 1280, 16384},{FDI_ENCLV, 0, 1024, 49152},{FDI_MONITOR, 0, 1024, 49152},{FDI_MWAIT, 0, 1024, 49152},{FDI_CLAC, 0, 1024, 49152},{FDI_STAC, 0, 1024, 49152},{FDI_ENCLS, 0, 1024, 49152},{FDI_XGETBV, 0, 1024, 49152},{FDI_XSETBV, 0, 1024, 49152},{FDI_XEND, 0, 1024, 49152},{FDI_XTEST, 0, 1024, 49152},{FDI_ENCLU, 0, 1024, 49152},{FDI_SWAPGS, 0, 1024, 16384},{FDI_RDTSCP, 0, 1024, 16384},{FDI_LAR, 14, 2056, 16393},{FDI_LSL, 14, 2056, 16393},{FDI_SYSCALL, 0, 1024, 0},{FDI_CLTS, 0, 1024, 0},{FDI_SYSRET, 0, 1024, 0},{FDI_INVD, 0, 1024, 0},{FDI_WBINVD, 0, 1024, 0},{FDI_UD2, 0, 1024, 0},{FDI_PREFETCH, 3, 1024, 16384},{FDI_PREFETCHW, 3, 1024, 16384},{FDI_PREFETCHWT1, 3, 1024, 16384},{FDI_RESERVED_PREFETCH, 3, 1024, 16384},{FDI_RESERVED_NOP, 11, 1034, 16393},{FDI_FEMMS, 0, 1024, 0},{FDI_3DNOW, 20558, 4416, 16429},{FDI_PREFETCHNTA, 3, 1024, 16384},{FDI_PREFETCHT0, 3, 1024, 16384},{FDI_PREFETCHT1, 3, 1024, 16384},{FDI_PREFETCHT2, 3, 1024, 16384},{FDI_PREFETCHIT1, 3, 1024, 16384},{FDI_PREFETCHIT0, 3, 1024, 16384},{FDI_NOP, 3, 1026, 16385},{FDI_MOV_CR, 11, 1034, 53249},{FDI_MOV_DR, 11, 1034, 53249},{FDI_MOV_CR, 14, 1034, 53249},{FDI_MOV_DR, 14, 1034, 53249},{FDI_WRMSR, 0, 1024, 0},{FDI_RDTSC, 0, 1024, 0},{FDI_RDMSR, 0, 1024, 0},{FDI_RDPMC, 0, 1024, 0},{FDI_SYSENTER, 0, 1024, 0},{FDI_SYSEXIT, 0, 1024, 0},{FDI_GETSEC, 0, 1024, 32768},{FDI_CMOVO, 14, 1034, 16393},{FDI_CMOVNO, 14, 1034, 16393},{FDI_CMOVC, 14, 1034, 16393},{FDI_CMOVNC, 14, 1034, 16393},{FDI_CMOVZ, 14, 1034, 16393},{FDI_CMOVNZ, 14, 1034, 16393},{FDI_CMOVBE, 14, 1034, 16393},{FDI_CMOVA, 14, 1034, 16393},{FDI_CMOVS, 14, 1034, 16393},{FDI_CMOVNS, 14, 1034, 16393},{FDI_CMOVP, 14, 1034, 16393},{FDI_CMOVNP, 14, 1034, 16393},{FDI_CMOVL, 14, 1034, 16393},{FDI_CMOVGE, 14, 1034, 16393},{FDI_CMOVLE, 14, 1034, 16393},{FDI_CMOVG, 14, 1034, 16393},{FDI_JO, 24768, 1152, 6144},{FDI_JNO, 24768, 1152, 6144},{FDI_JC, 24768, 1152, 6144},{FDI_JNC, 24768, 1152, 6144},{FDI_JZ, 24768, 1152, 6144},{FDI_JNZ, 24768, 1152, 6144},{FDI_JBE, 24768, 1152, 6144},{FDI_JA, 24768, 1152, 6144},{FDI_JS, 24768, 1152, 6144},{FDI_JNS, 24768, 1152, 6144},{FDI_JP, 24768, 1152, 6144},{FDI_JNP, 24768, 1152, 6144},{FDI_JL, 24768, 1152, 6144},{FDI_JGE, 24768, 1152, 6144},{FDI_JLE, 24768, 1152, 6144},{FDI_JG, 24768, 1152, 6144},{FDI_SETO, 3, 1280, 16385},{FDI_SETNO, 3, 1280, 16385},{FDI_SETC, 3, 1280, 16385},{FDI_SETNC, 3, 1280, 16385},{FDI_SETZ, 3, 1280, 16385},{FDI_SETNZ, 3, 1280, 16385},{FDI_SETBE, 3, 1280, 16385},{FDI_SETA, 3, 1280, 16385},{FDI_SETS, 3, 1280, 16385},{FDI_SETNS, 3, 1280, 16385},{FDI_SETP, 3, 1280, 16385},{FDI_SETNP, 3, 1280, 16385},{FDI_SETL, 3, 1280, 16385},{FDI_SETGE, 3, 1280, 16385},{FDI_SETLE, 3, 1280, 16385},{FDI_SETG, 3, 1280, 16385},{FDI_PUSH, 12, 1032, 4120},{FDI_POP, 12, 1032, 4120},{FDI_CPUID, 0, 1024, 0},{FDI_BT, 11, 1034, 16393},{FDI_SHLD, 20555, 1098, 16393},{FDI_SHLD, 1051, 1034, 16457},{FDI_RSM, 0, 1024, 0},{FDI_BTS, 2059, 1034, 16393},{FDI_SHRD, 20555, 1098, 16393},{FDI_SHRD, 1051, 1034, 16457},{FDI_IMUL, 14, 1034, 16393},{FDI_CMPXCHG, 2059, 1280, 16393},{FDI_CMPXCHG, 2059, 1034, 16393},{FDI_LSS, 14, 1034, 16392},{FDI_BTR, 2059, 1034, 16393},{FDI_LFS, 14, 1034, 16392},{FDI_LGS, 14, 1034, 16392},{FDI_MOVZX, 14, 1288, 16393},{FDI_MOVZX, 14, 2312, 16393},{FDI_POPCNT, 14, 1034, 16393},{FDI_UD1, 14, 1034, 16393},{FDI_BT, 20611, 1090, 16385},{FDI_BTS, 22659, 1090, 16385},{FDI_BTR, 22659, 1090, 16385},{FDI_BTC, 22659, 1090, 16385},{FDI_BTC, 2059, 1034, 16393},{FDI_BSF, 14, 1034, 16393},{FDI_TZCNT, 14, 1034, 16393},{FDI_BSR, 14, 1034, 16393},{FDI_LZCNT, 14, 1034, 16393},{FDI_MOVSX, 14, 1288, 16393},{FDI_MOVSX, 14, 2312, 16393},{FDI_XADD, 2059, 1280, 16393},{FDI_XADD, 2059, 1034, 16393},{FDI_MOVNTI, 11, 1034, 49160},{FDI_CMPXCHGD, 2051, 33024, 49152},{FDI_BSWAP, 3, 1026, 1},{FDI_UD0, 14, 1034, 16393},{FDI_MOVBE, 14, 1034, 16392},{FDI_CRC32, 14, 17668, 49161},{FDI_MOVBE, 11, 1034, 16392},{FDI_CRC32, 14, 3074, 16393},{FDI_MMX_CVTPI2PS, 14, 4096, 49157},{FDI_MMX_CVTPI2PD, 14, 29697, 49157},{FDI_MMX_CVTTPS2PI, 14, 4096, 49192},{FDI_MMX_CVTTPD2PI, 14, 29700, 49192},{FDI_MMX_CVTPS2PI, 14, 4096, 49192},{FDI_MMX_CVTPD2PI, 14, 29700, 49192},{FDI_MMX_PUNPCKLBW, 14, 27652, 49197},{FDI_MMX_PUNPCKLWD, 14, 27652, 49197},{FDI_MMX_PUNPCKLDQ, 14, 27652, 49197},{FDI_MMX_PACKSSWB, 14, 4096, 49197},{FDI_MMX_PCMPGTB, 14, 4096, 49197},{FDI_MMX_PCMPGTW, 14, 4096, 49197},{FDI_MMX_PCMPGTD, 14, 4096, 49197},{FDI_MMX_PACKUSWB, 14, 4096, 49197},{FDI_MMX_PUNPCKHBW, 14, 4096, 49197},{FDI_MMX_PUNPCKHWD, 14, 4096, 49197},{FDI_MMX_PUNPCKHDQ, 14, 4096, 49197},{FDI_MMX_PACKSSDW, 14, 4096, 49197},{FDI_MMX_MOVD, 14, 4098, 49193},{FDI_MMX_MOVQ, 14, 4098, 49193},{FDI_MMX_MOVQ, 14, 4096, 49197},{FDI_MMX_PSHUFW, 20558, 4160, 49197},{FDI_MMX_PSRLW, 20611, 4160, 49157},{FDI_MMX_PSRAW, 20611, 4160, 49157},{FDI_MMX_PSLLW, 20611, 4160, 49157},{FDI_MMX_PSRLD, 20611, 4160, 49157},{FDI_MMX_PSRAD, 20611, 4160, 49157},{FDI_MMX_PSLLD, 20611, 4160, 49157},{FDI_MMX_PSRLQ, 20611, 4160, 49157},{FDI_MMX_PSLLQ, 20611, 4160, 49157},{FDI_MMX_PCMPEQB, 14, 4096, 49197},{FDI_MMX_PCMPEQW, 14, 4096, 49197},{FDI_MMX_PCMPEQD, 14, 4096, 49197},{FDI_MMX_EMMS, 0, 1024, 32768},{FDI_MMX_MOVD, 11, 1034, 49193},{FDI_MMX_MOVQ, 11, 1034, 49193},{FDI_MMX_MOVQ, 11, 4096, 49197},{FDI_MMX_PINSRW, 20558, 26692, 49193},{FDI_MMX_PEXTRW, 20558, 4168, 53261},{FDI_MMX_PSRLW, 14, 4096, 49197},{FDI_MMX_PSRLD, 14, 4096, 49197},{FDI_MMX_PSRLQ, 14, 4096, 49197},{FDI_MMX_PADDQ, 14, 4096, 49197},{FDI_MMX_PMULLW, 14, 4096, 49197},{FDI_MMX_MOVDQ2Q, 14, 4096, 49192},{FDI_MMX_MOVQ2DQ, 14, 29697, 49157},{FDI_MMX_PMOVMSKB, 14, 4104, 53261},{FDI_MMX_PSUBUSB, 14, 4096, 49197},{FDI_MMX_PSUBUSW, 14, 4096, 49197},{FDI_MMX_PMINUB, 14, 4096, 49197},{FDI_MMX_PAND, 14, 4096, 49197},{FDI_MMX_PADDUSB, 14, 4096, 49197},{FDI_MMX_PADDUSW, 14, 4096, 49197},{FDI_MMX_PMAXUB, 14, 4096, 49197},{FDI_MMX_PANDN, 14, 4096, 49197},{FDI_MMX_PAVGB, 14, 4096, 49197},{FDI_MMX_PSRAW, 14, 4096, 49197},{FDI_MMX_PSRAD, 14, 4096, 49197},{FDI_MMX_PAVGW, 14, 4096, 49197},{FDI_MMX_PMULHUW, 14, 4096, 49197},{FDI_MMX_PMULHW, 14, 4096, 49197},{FDI_MMX_MOVNTQ, 11, 4096, 49192},{FDI_MMX_PSUBSB, 14, 4096, 49197},{FDI_MMX_PSUBSW, 14, 4096, 49197},{FDI_MMX_POR, 14, 4096, 49197},{FDI_MMX_PADDSB, 14, 4096, 49197},{FDI_MMX_PMINSW, 14, 4096, 49197},{FDI_MMX_PMAXSW, 14, 4096, 49197},{FDI_MMX_PADDSW, 14, 4096, 49197},{FDI_MMX_PXOR, 14, 4096, 49197},{FDI_MMX_PSLLW, 14, 4096, 49197},{FDI_MMX_PSLLD, 14, 4096, 49197},{FDI_MMX_PSLLQ, 14, 4096, 49197},{FDI_MMX_PMULUDQ, 14, 4096, 49197},{FDI_MMX_PMADDWD, 14, 4096, 49197},{FDI_MMX_PSADBW, 14, 4096, 49197},{FDI_MMX_MASKMOVQ, 14, 4096, 49197},{FDI_MMX_PSUBB, 14, 4096, 49197},{FDI_MMX_PSUBW, 14, 4096, 49197},{FDI_MMX_PSUBD, 14, 4096, 49197},{FDI_MMX_PSUBQ, 14, 4096, 49197},{FDI_MMX_PADDB, 14, 4096, 49197},{FDI_MMX_PADDW, 14, 4096, 49197},{FDI_MMX_PADDD, 14, 4096, 49197},{FDI_MMX_PSHUFB, 14, 4096, 49197},{FDI_MMX_PHADDW, 14, 4096, 49197},{FDI_MMX_PHADDD, 14, 4096, 49197},{FDI_MMX_PHADDSW, 14, 4096, 49197},{FDI_MMX_PMADDUBSW, 14, 4096, 49197},{FDI_MMX_PHSUBW, 14, 4096, 49197},{FDI_MMX_PHSUBD, 14, 4096, 49197},{FDI_MMX_PHSUBSW, 14, 4096, 49197},{FDI_MMX_PSIGNB, 14, 4096, 49197},{FDI_MMX_PSIGNW, 14, 4096, 49197},{FDI_MMX_PSIGND, 14, 4096, 49197},{FDI_MMX_PMULHRSW, 14, 4096, 49197},{FDI_MMX_PABSB, 14, 4096, 49197},{FDI_MMX_PABSW, 14, 4096, 49197},{FDI_MMX_PABSD, 14, 4096, 49197},{FDI_MMX_PALIGNR, 20558, 4160, 49197},{FDI_SSE_MOVUPS, 14, 1034, 57344},{FDI_SSE_MOVUPD, 14, 1034, 57344},{FDI_SSE_MOVSS, 14, 3080, 57344},{FDI_SSE_MOVSD, 14, 4104, 57344},{FDI_SSE_MOVUPS, 11, 1034, 57344},{FDI_SSE_MOVUPD, 11, 1034, 57344},{FDI_SSE_MOVSS, 11, 3072, 49152},{FDI_SSE_MOVSD, 11, 4096, 49152},{FDI_SSE_MOVLPS, 14, 4104, 57344},{FDI_SSE_MOVHLPS, 14, 1034, 57344},{FDI_SSE_MOVLPD, 14, 4104, 57344},{FDI_SSE_MOVSLDUP, 14, 1034, 57344},{FDI_SSE_MOVDDUP, 14, 4104, 57344},{FDI_SSE_MOVLPS, 11, 4096, 49152},{FDI_SSE_MOVLPD, 11, 4096, 49152},{FDI_SSE_UNPCKLPS, 14, 1034, 57344},{FDI_SSE_UNPCKLPD, 14, 1034, 57344},{FDI_SSE_UNPCKHPS, 14, 1034, 57344},{FDI_SSE_UNPCKHPD, 14, 1034, 57344},{FDI_SSE_MOVHPS, 14, 4104, 57344},{FDI_SSE_MOVLHPS, 14, 4104, 57344},{FDI_SSE_MOVHPD, 14, 29697, 49152},{FDI_SSE_MOVSHDUP, 14, 1034, 57344},{FDI_SSE_MOVHPS, 11, 4104, 57344},{FDI_SSE_MOVHPD, 11, 4104, 57344},{FDI_SSE_MOVAPS, 14, 1034, 57344},{FDI_SSE_MOVAPD, 14, 1034, 57344},{FDI_SSE_MOVAPS, 11, 1034, 57344},{FDI_SSE_MOVAPD, 11, 1034, 57344},{FDI_SSE_CVTSI2SS, 14, 3074, 49153},{FDI_SSE_CVTSI2SD, 14, 4098, 49153},{FDI_SSE_MOVNTPS, 11, 1034, 57344},{FDI_SSE_MOVNTPD, 11, 1034, 57344},{FDI_SSE_MOVNTSS, 11, 3072, 49152},{FDI_SSE_MOVNTSD, 11, 4096, 49152},{FDI_SSE_CVTTSS2SI, 14, 3080, 49160},{FDI_SSE_CVTTSD2SI, 14, 4104, 49160},{FDI_SSE_CVTSS2SI, 14, 3080, 49160},{FDI_SSE_CVTSD2SI, 14, 4104, 49160},{FDI_SSE_UCOMISS, 14, 3072, 49152},{FDI_SSE_UCOMISD, 14, 4096, 49152},{FDI_SSE_COMISS, 14, 3072, 49152},{FDI_SSE_COMISD, 14, 4096, 49152},{FDI_SSE_MOVMSKPS, 14, 5128, 53256},{FDI_SSE_MOVMSKPD, 14, 5128, 53256},{FDI_SSE_SQRTPS, 14, 1034, 57344},{FDI_SSE_SQRTPD, 14, 1034, 57344},{FDI_SSE_SQRTSS, 14, 3072, 49152},{FDI_SSE_SQRTSD, 14, 4096, 49152},{FDI_SSE_RSQRTPS, 14, 1034, 57344},{FDI_SSE_RSQRTSS, 14, 3072, 49152},{FDI_SSE_RCPPS, 14, 1034, 57344},{FDI_SSE_RCPSS, 14, 3072, 49152},{FDI_SSE_ANDPS, 14, 1034, 57344},{FDI_SSE_ANDPD, 14, 1034, 57344},{FDI_SSE_ANDNPS, 14, 1034, 57344},{FDI_SSE_ANDNPD, 14, 1034, 57344},{FDI_SSE_ORPS, 14, 1034, 57344},{FDI_SSE_ORPD, 14, 1034, 57344},{FDI_SSE_XORPS, 14, 1034, 57344},{FDI_SSE_XORPD, 14, 1034, 57344},{FDI_SSE_ADDPS, 14, 1034, 57344},{FDI_SSE_ADDPD, 14, 1034, 57344},{FDI_SSE_ADDSS, 14, 3072, 49152},{FDI_SSE_ADDSD, 14, 4096, 49152},{FDI_SSE_MULPS, 14, 1034, 57344},{FDI_SSE_MULPD, 14, 1034, 57344},{FDI_SSE_MULSS, 14, 3072, 49152},{FDI_SSE_MULSD, 14, 4096, 49152},{FDI_SSE_CVTPS2PD, 14, 4104, 57344},{FDI_SSE_CVTPD2PS, 14, 1034, 57344},{FDI_SSE_CVTSS2SD, 14, 27652, 49152},{FDI_SSE_CVTSD2SS, 14, 27649, 49152},{FDI_SSE_CVTDQ2PS, 14, 5128, 57344},{FDI_SSE_CVTPS2DQ, 14, 5122, 57344},{FDI_SSE_CVTTPS2DQ, 14, 5122, 57344},{FDI_SSE_SUBPS, 14, 1034, 57344},{FDI_SSE_SUBPD, 14, 1034, 57344},{FDI_SSE_SUBSS, 14, 3072, 49152},{FDI_SSE_SUBSD, 14, 4096, 49152},{FDI_SSE_MINPS, 14, 1034, 57344},{FDI_SSE_MINPD, 14, 1034, 57344},{FDI_SSE_MINSS, 14, 3072, 49152},{FDI_SSE_MINSD, 14, 4096, 49152},{FDI_SSE_DIVPS, 14, 1034, 57344},{FDI_SSE_DIVPD, 14, 1034, 57344},{FDI_SSE_DIVSS, 14, 3072, 49152},{FDI_SSE_DIVSD, 14, 4096, 49152},{FDI_SSE_MAXPS, 14, 1034, 57344},{FDI_SSE_MAXPD, 14, 1034, 57344},{FDI_SSE_MAXSS, 14, 3072, 49152},{FDI_SSE_MAXSD, 14, 4096, 49152},{FDI_SSE_PUNPCKLBW, 14, 1034, 57344},{FDI_SSE_PUNPCKLWD, 14, 1034, 57344},{FDI_SSE_PUNPCKLDQ, 14, 1034, 57344},{FDI_SSE_PACKSSWB, 14, 1034, 57344},{FDI_SSE_PCMPGTB, 14, 1034, 57344},{FDI_SSE_PCMPGTW, 14, 1034, 57344},{FDI_SSE_PCMPGTD, 14, 1034, 57344},{FDI_SSE_PACKUSWB, 14, 1034, 57344},{FDI_SSE_PUNPCKHBW, 14, 1034, 57344},{FDI_SSE_PUNPCKHWD, 14, 1034, 57344},{FDI_SSE_PUNPCKHDQ, 14, 1034, 57344},{FDI_SSE_PACKSSDW, 14, 1034, 57344},{FDI_SSE_PUNPCKLQDQ, 14, 1034, 57344},{FDI_SSE_PUNPCKHQDQ, 14, 1034, 57344},{FDI_SSE_MOVD, 14, 3080, 57345},{FDI_SSE_MOVQ, 14, 4104, 57345},{FDI_SSE_MOVDQA, 14, 1034, 57344},{FDI_SSE_MOVDQU, 14, 1034, 57344},{FDI_SSE_PSHUFD, 20558, 1098, 57344},{FDI_SSE_PSHUFHW, 20558, 1098, 57344},{FDI_SSE_PSHUFLW, 20558, 1098, 57344},{FDI_SSE_PSRLW, 20611, 1090, 57344},{FDI_SSE_PSRAW, 20611, 1090, 57344},{FDI_SSE_PSLLW, 20611, 1090, 57344},{FDI_SSE_PSRLD, 20611, 1090, 57344},{FDI_SSE_PSRAD, 20611, 1090, 57344},{FDI_SSE_PSLLD, 20611, 1090, 57344},{FDI_SSE_PSRLQ, 20611, 1090, 57344},{FDI_SSE_PSRLDQ, 20611, 1090, 57344},{FDI_SSE_PSLLQ, 20611, 1090, 57344},{FDI_SSE_PSLLDQ, 20611, 1090, 57344},{FDI_SSE_PCMPEQB, 14, 1034, 57344},{FDI_SSE_PCMPEQW, 14, 1034, 57344},{FDI_SSE_PCMPEQD, 14, 1034, 57344},{FDI_SSE_EXTRQ, 16515, 2050, 57344},{FDI_SSE_INSERTQ, 16462, 2058, 57344},{FDI_SSE_EXTRQ, 14, 1034, 57344},{FDI_SSE_INSERTQ, 14, 1034, 57344},{FDI_SSE_HADDPD, 14, 1034, 57344},{FDI_SSE_HADDPS, 14, 1034, 57344},{FDI_SSE_HSUBPD, 14, 1034, 57344},{FDI_SSE_HSUBPS, 14, 1034, 57344},{FDI_SSE_MOVD, 11, 1034, 49153},{FDI_SSE_MOVQ, 11, 1034, 49153},{FDI_SSE_MOVQ, 14, 4104, 57344},{FDI_SSE_MOVDQA, 11, 1034, 57344},{FDI_SSE_MOVDQU, 11, 1034, 57344},{FDI_FXSAVE, 3, 33024, 49152},{FDI_FXRSTOR, 3, 33024, 49152},{FDI_LDMXCSR, 3, 3072, 49152},{FDI_STMXCSR, 3, 3072, 49152},{FDI_LFENCE, 0, 1024, 49152},{FDI_MFENCE, 0, 1024, 49152},{FDI_SFENCE, 0, 1024, 49152},{FDI_SSE_CMPPS, 20558, 1098, 57344},{FDI_SSE_CMPPD, 20558, 1098, 57344},{FDI_SSE_CMPSS, 20558, 3136, 49152},{FDI_SSE_CMPSD, 20558, 4160, 49152},{FDI_SSE_PINSRW, 20558, 2120, 57345},{FDI_SSE_PEXTRW, 20558, 5192, 53256},{FDI_SSE_SHUFPS, 20558, 1098, 57344},{FDI_SSE_SHUFPD, 20558, 1098, 57344},{FDI_SSE_ADDSUBPD, 14, 1034, 57344},{FDI_SSE_ADDSUBPS, 14, 1034, 57344},{FDI_SSE_PSRLW, 14, 1034, 57344},{FDI_SSE_PSRLD, 14, 1034, 57344},{FDI_SSE_PSRLQ, 14, 1034, 57344},{FDI_SSE_PADDQ, 14, 1034, 57344},{FDI_SSE_PMULLW, 14, 1034, 57344},{FDI_SSE_MOVQ, 11, 4096, 49152},{FDI_SSE_PMOVMSKB, 14, 5128, 53256},{FDI_SSE_PSUBUSB, 14, 1034, 57344},{FDI_SSE_PSUBUSW, 14, 1034, 57344},{FDI_SSE_PMINUB, 14, 1034, 57344},{FDI_SSE_PAND, 14, 1034, 57344},{FDI_SSE_PADDUSB, 14, 1034, 57344},{FDI_SSE_PADDUSW, 14, 1034, 57344},{FDI_SSE_PMAXUB, 14, 1034, 57344},{FDI_SSE_PANDN, 14, 1034, 57344},{FDI_SSE_PAVGB, 14, 1034, 57344},{FDI_SSE_PSRAW, 14, 1034, 57344},{FDI_SSE_PSRAD, 14, 1034, 57344},{FDI_SSE_PAVGW, 14, 1034, 57344},{FDI_SSE_PMULHUW, 14, 1034, 57344},{FDI_SSE_PMULHW, 14, 1034, 57344},{FDI_SSE_CVTTPD2DQ, 14, 1034, 57344},{FDI_SSE_CVTDQ2PD, 14, 4104, 57344},{FDI_SSE_CVTPD2DQ, 14, 1034, 57344},{FDI_SSE_MOVNTDQ, 11, 1034, 57344},{FDI_SSE_PSUBSB, 14, 1034, 57344},{FDI_SSE_PSUBSW, 14, 1034, 57344},{FDI_SSE_POR, 14, 1034, 57344},{FDI_SSE_PADDSB, 14, 1034, 57344},{FDI_SSE_PMINSW, 14, 1034, 57344},{FDI_SSE_PMAXSW, 14, 1034, 57344},{FDI_SSE_PADDSW, 14, 1034, 57344},{FDI_SSE_PXOR, 14, 1034, 57344},{FDI_SSE_LDDQU, 14, 1034, 57344},{FDI_SSE_PSLLW, 14, 1034, 57344},{FDI_SSE_PSLLD, 14, 1034, 57344},{FDI_SSE_PSLLQ, 14, 1034, 57344},{FDI_SSE_PMULUDQ, 14, 1034, 57344},{FDI_SSE_PMADDWD, 14, 1034, 57344},{FDI_SSE_PSADBW, 14, 1034, 57344},{FDI_SSE_MASKMOVDQU, 14, 1034, 57344},{FDI_SSE_PSUBB, 14, 1034, 57344},{FDI_SSE_PSUBW, 14, 1034, 57344},{FDI_SSE_PSUBD, 14, 1034, 57344},{FDI_SSE_PSUBQ, 14, 1034, 57344},{FDI_SSE_PADDB, 14, 1034, 57344},{FDI_SSE_PADDW, 14, 1034, 57344},{FDI_SSE_PADDD, 14, 1034, 57344},{FDI_SSE_PSHUFB, 14, 1034, 57344},{FDI_SSE_PHADDW, 14, 1034, 57344},{FDI_SSE_PHADDD, 14, 1034, 57344},{FDI_SSE_PHADDSW, 14, 1034, 57344},{FDI_SSE_PMADDUBSW, 14, 1034, 57344},{FDI_SSE_PHSUBW, 14, 1034, 57344},{FDI_SSE_PHSUBD, 14, 1034, 57344},{FDI_SSE_PHSUBSW, 14, 1034, 57344},{FDI_SSE_PSIGNB, 14, 1034, 57344},{FDI_SSE_PSIGNW, 14, 1034, 57344},{FDI_SSE_PSIGND, 14, 1034, 57344},{FDI_SSE_PMULHRSW, 14, 1034, 57344},{FDI_SSE_PBLENDVB, 14, 5120, 49152},{FDI_SSE_BLENDVPS, 30, 5120, 49152},{FDI_SSE_BLENDVPD, 30, 5120, 49152},{FDI_SSE_PTEST, 14, 1034, 57344},{FDI_SSE_PABSB, 14, 1034, 57344},{FDI_SSE_PABSW, 14, 1034, 57344},{FDI_SSE_PABSD, 14, 1034, 57344},{FDI_SSE_PMOVSXBW, 14, 1035, 59392},{FDI_SSE_PMOVSXBD, 14, 1035, 61440},{FDI_SSE_PMOVSXBQ, 14, 1035, 63488},{FDI_SSE_PMOVSXWD, 14, 1035, 59392},{FDI_SSE_PMOVSXWQ, 14, 1035, 61440},{FDI_SSE_PMOVSXDQ, 14, 1035, 59392},{FDI_SSE_PMULDQ, 14, 1034, 57344},{FDI_SSE_PCMPEQQ, 14, 1034, 57344},{FDI_SSE_MOVNTDQA, 14, 1034, 57344},{FDI_SSE_PACKUSDW, 14, 1034, 57344},{FDI_SSE_PMOVZXBW, 14, 1035, 59392},{FDI_SSE_PMOVZXBD, 14, 1035, 61440},{FDI_SSE_PMOVZXBQ, 14, 1035, 63488},{FDI_SSE_PMOVZXWD, 14, 1035, 59392},{FDI_SSE_PMOVZXWQ, 14, 1035, 61440},{FDI_SSE_PMOVZXDQ, 14, 1035, 59392},{FDI_SSE_PCMPGTQ, 14, 1034, 57344},{FDI_SSE_PMINSB, 14, 1034, 57344},{FDI_SSE_PMINSD, 14, 1034, 57344},{FDI_SSE_PMINUW, 14, 1034, 57344},{FDI_SSE_PMINUD, 14, 1034, 57344},{FDI_SSE_PMAXSB, 14, 1034, 57344},{FDI_SSE_PMAXSD, 14, 1034, 57344},{FDI_SSE_PMAXUW, 14, 1034, 57344},{FDI_SSE_PMAXUD, 14, 1034, 57344},{FDI_SSE_PMULLD, 14, 1034, 57344},{FDI_SSE_PHMINPOSUW, 14, 1034, 57344},{FDI_MOVDIR64B, 14, 7176, 53256},{FDI_MOVDIRI, 11, 1034, 49160},{FDI_SSE_ROUNDPS, 20558, 1098, 57344},{FDI_SSE_ROUNDPD, 20558, 1098, 57344},{FDI_SSE_ROUNDSS, 20558, 3136, 49152},{FDI_SSE_ROUNDSD, 20558, 4160, 49152},{FDI_SSE_BLENDPS, 20558, 1098, 57344},{FDI_SSE_BLENDPD, 20558, 1098, 57344},{FDI_SSE_PBLENDW, 20558, 1098, 57344},{FDI_SSE_PALIGNR, 20558, 1098, 57344},{FDI_SSE_PEXTRB, 20555, 1096, 57344},{FDI_SSE_PEXTRB, 20555, 3144, 57345},{FDI_SSE_PEXTRW, 20555, 2120, 57344},{FDI_SSE_PEXTRW, 20555, 3144, 57345},{FDI_SSE_PEXTRD, 20555, 3144, 57345},{FDI_SSE_PEXTRQ, 20555, 4168, 57345},{FDI_SSE_EXTRACTPS, 20555, 3144, 57345},{FDI_SSE_PINSRB, 20558, 1096, 57345},{FDI_SSE_INSERTPS, 20558, 3144, 57344},{FDI_SSE_PINSRD, 20558, 3144, 57345},{FDI_SSE_PINSRQ, 20558, 4168, 57345},{FDI_SSE_DPPS, 20558, 1098, 57344},{FDI_SSE_DPPD, 20558, 1098, 57344},{FDI_SSE_MPSADBW, 20558, 1098, 57344},{FDI_SSE_PCLMULQDQ, 20558, 5184, 49152},{FDI_SSE_PCMPESTRM, 20558, 5184, 49152},{FDI_SSE_PCMPESTRI, 20558, 5184, 49152},{FDI_SSE_PCMPISTRM, 20558, 5184, 49152},{FDI_SSE_PCMPISTRI, 20558, 5184, 49152},{FDI_AESIMC, 14, 5120, 49152},{FDI_AESENC, 14, 5120, 49152},{FDI_AESENCLAST, 14, 5120, 49152},{FDI_AESDEC, 14, 5120, 49152},{FDI_AESDECLAST, 14, 5120, 49152},{FDI_AESKEYGENASSIST, 20558, 5184, 49152},{FDI_VAESIMC, 14, 5120, 49152},{FDI_VAESENC, 45, 1066, 57344},{FDI_VAESENCLAST, 45, 1066, 57344},{FDI_VAESDEC, 45, 1066, 57344},{FDI_VAESDECLAST, 45, 1066, 57344},{FDI_VAESKEYGENASSIST, 20558, 5184, 49152},{FDI_VMOVUPS, 14, 1034, 57344},{FDI_VMOVUPD, 14, 1034, 57344},{FDI_VMOVSS, 14, 21505, 49152},{FDI_VMOVSS, 45, 21505, 49152},{FDI_VMOVSD, 14, 29697, 49152},{FDI_VMOVSD, 45, 29697, 49152},{FDI_VMOVUPS, 11, 1034, 57344},{FDI_VMOVUPD, 11, 1034, 57344},{FDI_VMOVSS, 11, 3072, 49152},{FDI_VMOVSS, 39, 21508, 49152},{FDI_VMOVSD, 11, 4096, 49152},{FDI_VMOVSD, 39, 29700, 49152},{FDI_VMOVLPS, 45, 29697, 49152},{FDI_VMOVHLPS, 45, 5120, 49152},{FDI_VMOVLPD, 45, 29697, 49152},{FDI_VMOVDDUP, 14, 4104, 57344},{FDI_VMOVDDUP, 14, 1034, 57344},{FDI_VMOVSLDUP, 14, 1034, 57344},{FDI_VMOVLPS, 11, 4096, 49152},{FDI_VMOVLPD, 11, 4096, 49152},{FDI_VUNPCKLPS, 45, 1066, 57344},{FDI_VUNPCKLPD, 45, 1066, 57344},{FDI_VUNPCKHPS, 45, 1066, 57344},{FDI_VUNPCKHPD, 45, 1066, 57344},{FDI_VMOVHPS, 45, 29713, 49152},{FDI_VMOVLHPS, 45, 29713, 49152},{FDI_VMOVHPD, 45, 29713, 49152},{FDI_VMOVSHDUP, 14, 1034, 57344},{FDI_VMOVHPS, 11, 4096, 49152},{FDI_VMOVHPD, 11, 4096, 49152},{FDI_VMOVAPS, 14, 1034, 57344},{FDI_VMOVAPD, 14, 1034, 57344},{FDI_VMOVAPS, 11, 1034, 57344},{FDI_VMOVAPD, 11, 1034, 57344},{FDI_VCVTSI2SS, 45, 5122, 49153},{FDI_VCVTSI2SD, 45, 5122, 49153},{FDI_VMOVNTPS, 11, 1034, 57344},{FDI_VMOVNTPD, 11, 1034, 57344},{FDI_VCVTTSS2SI, 14, 3080, 49160},{FDI_VCVTTSD2SI, 14, 4104, 49160},{FDI_VCVTSS2SI, 14, 3080, 49160},{FDI_VCVTSD2SI, 14, 4104, 49160},{FDI_VUCOMISS, 14, 3072, 49152},{FDI_VUCOMISD, 14, 4096, 49152},{FDI_VCOMISS, 14, 3072, 49152},{FDI_VCOMISD, 14, 4096, 49152},{FDI_VMOVMSKPS, 14, 3074, 57352},{FDI_VMOVMSKPD, 14, 3074, 57352},{FDI_VSQRTPS, 14, 1034, 57344},{FDI_VSQRTPD, 14, 1034, 57344},{FDI_VSQRTSS, 45, 21505, 49152},{FDI_VSQRTSD, 45, 29697, 49152},{FDI_VRSQRTPS, 14, 1034, 57344},{FDI_VRSQRTSS, 45, 21505, 49152},{FDI_VRCPPS, 14, 1034, 57344},{FDI_VRCPSS, 45, 21505, 49152},{FDI_VANDPS, 45, 1066, 57344},{FDI_VANDPD, 45, 1066, 57344},{FDI_VANDNPS, 45, 1066, 57344},{FDI_VANDNPD, 45, 1066, 57344},{FDI_VORPS, 45, 1066, 57344},{FDI_VORPD, 45, 1066, 57344},{FDI_VXORPS, 45, 1066, 57344},{FDI_VXORPD, 45, 1066, 57344},{FDI_VADDPS, 45, 1066, 57344},{FDI_VADDPD, 45, 1066, 57344},{FDI_VADDSS, 45, 21505, 49152},{FDI_VADDSD, 45, 29697, 49152},{FDI_VMULPS, 45, 1066, 57344},{FDI_VMULPD, 45, 1066, 57344},{FDI_VMULSS, 45, 21505, 49152},{FDI_VMULSD, 45, 29697, 49152},{FDI_VCVTPS2PD, 14, 1035, 59392},{FDI_VCVTPD2PS, 14, 1038, 59392},{FDI_VCVTSS2SD, 45, 21505, 49152},{FDI_VCVTSD2SS, 45, 29697, 49152},{FDI_VCVTDQ2PS, 14, 1034, 57344},{FDI_VCVTPS2DQ, 14, 1034, 57344},{FDI_VCVTTPS2DQ, 14, 1034, 57344},{FDI_VSUBPS, 45, 1066, 57344},{FDI_VSUBPD, 45, 1066, 57344},{FDI_VSUBSS, 45, 21505, 49152},{FDI_VSUBSD, 45, 29697, 49152},{FDI_VMINPS, 45, 1066, 57344},{FDI_VMINPD, 45, 1066, 57344},{FDI_VMINSS, 45, 21505, 49152},{FDI_VMINSD, 45, 29697, 49152},{FDI_VDIVPS, 45, 1066, 57344},{FDI_VDIVPD, 45, 1066, 57344},{FDI_VDIVSS, 45, 21505, 49152},{FDI_VDIVSD, 45, 29697, 49152},{FDI_VMAXPS, 45, 1066, 57344},{FDI_VMAXPD, 45, 1066, 57344},{FDI_VMAXSS, 45, 21505, 49152},{FDI_VMAXSD, 45, 29697, 49152},{FDI_VPUNPCKLBW, 45, 1066, 57344},{FDI_VPUNPCKLWD, 45, 1066, 57344},{FDI_VPUNPCKLDQ, 45, 1066, 57344},{FDI_VPACKSSWB, 45, 1066, 57344},{FDI_VPCMPGTB, 45, 1066, 57344},{FDI_VPCMPGTW, 45, 1066, 57344},{FDI_VPCMPGTD, 45, 1066, 57344},{FDI_VPACKUSWB, 45, 1066, 57344},{FDI_VPUNPCKHBW, 45, 1066, 57344},{FDI_VPUNPCKHWD, 45, 1066, 57344},{FDI_VPUNPCKHDQ, 45, 1066, 57344},{FDI_VPACKSSDW, 45, 1066, 57344},{FDI_VPUNPCKLQDQ, 45, 1066, 57344},{FDI_VPUNPCKHQDQ, 45, 1066, 57344},{FDI_VMOVD, 14, 1034, 49153},{FDI_VMOVQ, 14, 1034, 49153},{FDI_VMOVDQA, 14, 1034, 57344},{FDI_VMOVDQU, 14, 1034, 57344},{FDI_VPSHUFD, 20558, 1098, 57344},{FDI_VPSHUFHW, 20558, 1098, 57344},{FDI_VPSHUFLW, 20558, 1098, 57344},{FDI_VPSRLW, 20594, 1122, 57344},{FDI_VPSRAW, 20594, 1122, 57344},{FDI_VPSLLW, 20594, 1122, 57344},{FDI_VPSRLD, 20594, 1122, 57344},{FDI_VPSRAD, 20594, 1122, 57344},{FDI_VPSLLD, 20594, 1122, 57344},{FDI_VPSRLQ, 20594, 1122, 57344},{FDI_VPSRLDQ, 20594, 1122, 57344},{FDI_VPSLLQ, 20594, 1122, 57344},{FDI_VPSLLDQ, 20594, 1122, 57344},{FDI_VPCMPEQB, 45, 1066, 57344},{FDI_VPCMPEQW, 45, 1066, 57344},{FDI_VPCMPEQD, 45, 1066, 57344},{FDI_VZEROUPPER, 0, 1024, 32768},{FDI_VZEROALL, 0, 1024, 32768},{FDI_VHADDPD, 45, 1066, 57344},{FDI_VHADDPS, 45, 1066, 57344},{FDI_VHSUBPD, 45, 1066, 57344},{FDI_VHSUBPS, 45, 1066, 57344},{FDI_VMOVD, 11, 1034, 49153},{FDI_VMOVQ, 11, 1034, 49153},{FDI_VMOVQ, 14, 4096, 49152},{FDI_VMOVDQA, 11, 1034, 57344},{FDI_VMOVDQU, 11, 1034, 57344},{FDI_VLDMXCSR, 3, 3072, 49152},{FDI_VSTMXCSR, 3, 3072, 49152},{FDI_VCMPPS, 20525, 1130, 57344},{FDI_VCMPPD, 20525, 1130, 57344},{FDI_VCMPSS, 20525, 21569, 49152},{FDI_VCMPSD, 20525, 29761, 49152},{FDI_VPINSRW, 20525, 13377, 49153},{FDI_VPEXTRW, 20558, 21572, 49160},{FDI_VSHUFPS, 20525, 1130, 57344},{FDI_VSHUFPD, 20525, 1130, 57344},{FDI_VADDSUBPD, 45, 1066, 57344},{FDI_VADDSUBPS, 45, 1066, 57344},{FDI_VPSRLW, 45, 5160, 57344},{FDI_VPSRLD, 45, 5160, 57344},{FDI_VPSRLQ, 45, 5160, 57344},{FDI_VPADDQ, 45, 1066, 57344},{FDI_VPMULLW, 45, 1066, 57344},{FDI_VMOVQ, 11, 4096, 49152},{FDI_VPMOVMSKB, 14, 3074, 57352},{FDI_VPSUBUSB, 45, 1066, 57344},{FDI_VPSUBUSW, 45, 1066, 57344},{FDI_VPMINUB, 45, 1066, 57344},{FDI_VPAND, 45, 1066, 57344},{FDI_VPADDUSB, 45, 1066, 57344},{FDI_VPADDUSW, 45, 1066, 57344},{FDI_VPMAXUB, 45, 1066, 57344},{FDI_VPANDN, 45, 1066, 57344},{FDI_VPAVGB, 45, 1066, 57344},{FDI_VPSRAW, 45, 5160, 57344},{FDI_VPSRAD, 45, 5160, 57344},{FDI_VPAVGW, 45, 1066, 57344},{FDI_VPMULHUW, 45, 1066, 57344},{FDI_VPMULHW, 45, 1066, 57344},{FDI_VCVTTPD2DQ, 14, 1038, 59392},{FDI_VCVTDQ2PD, 14, 1035, 59392},{FDI_VCVTPD2DQ, 14, 1038, 59392},{FDI_VMOVNTDQ, 11, 1034, 57344},{FDI_VPSUBSB, 45, 1066, 57344},{FDI_VPSUBSW, 45, 1066, 57344},{FDI_VPOR, 45, 1066, 57344},{FDI_VPADDSB, 45, 1066, 57344},{FDI_VPMINSW, 45, 1066, 57344},{FDI_VPADDSW, 45, 1066, 57344},{FDI_VPMAXSW, 45, 1066, 57344},{FDI_VPXOR, 45, 1066, 57344},{FDI_VLDDQU, 14, 1034, 57344},{FDI_VPSLLW, 45, 5160, 57344},{FDI_VPSLLD, 45, 5160, 57344},{FDI_VPSLLQ, 45, 5160, 57344},{FDI_VPMULUDQ, 45, 1066, 57344},{FDI_VPMADDWD, 45, 1066, 57344},{FDI_VPSADBW, 45, 1066, 57344},{FDI_VMASKMOVDQU, 14, 1034, 57344},{FDI_VPSUBB, 45, 1066, 57344},{FDI_VPSUBW, 45, 1066, 57344},{FDI_VPSUBD, 45, 1066, 57344},{FDI_VPSUBQ, 45, 1066, 57344},{FDI_VPADDB, 45, 1066, 57344},{FDI_VPADDW, 45, 1066, 57344},{FDI_VPADDD, 45, 1066, 57344},{FDI_VPSHUFB, 45, 1066, 57344},{FDI_VPHADDW, 45, 1066, 57344},{FDI_VPHADDD, 45, 1066, 57344},{FDI_VPHADDSW, 45, 1066, 57344},{FDI_VPMADDUBSW, 45, 1066, 57344},{FDI_VPHSUBW, 45, 1066, 57344},{FDI_VPHSUBD, 45, 1066, 57344},{FDI_VPHSUBSW, 45, 1066, 57344},{FDI_VPSIGNB, 45, 1066, 57344},{FDI_VPSIGNW, 45, 1066, 57344},{FDI_VPSIGND, 45, 1066, 57344},{FDI_VPMULHRSW, 45, 1066, 57344},{FDI_VPERMILPS, 45, 1066, 57344},{FDI_VPERMILPD, 45, 1066, 57344},{FDI_VTESTPS, 14, 1034, 57344},{FDI_VTESTPD, 14, 1034, 57344},{FDI_VCVTPH2PS, 14, 1035, 59392},{FDI_VPERMPS, 45, 1066, 57344},{FDI_VPTEST, 14, 1034, 57344},{FDI_VBROADCASTSS, 14, 3080, 57344},{FDI_VBROADCASTSD, 14, 4104, 57344},{FDI_VBROADCASTF128, 14, 5128, 57344},{FDI_VPABSB, 14, 1034, 57344},{FDI_VPABSW, 14, 1034, 57344},{FDI_VPABSD, 14, 1034, 57344},{FDI_VPMOVSXBW, 14, 1035, 59392},{FDI_VPMOVSXBD, 14, 1035, 61440},{FDI_VPMOVSXBQ, 14, 1035, 63488},{FDI_VPMOVSXWD, 14, 1035, 59392},{FDI_VPMOVSXWQ, 14, 1035, 61440},{FDI_VPMOVSXDQ, 14, 1035, 59392},{FDI_VPMULDQ, 45, 1066, 57344},{FDI_VPCMPEQQ, 45, 1066, 57344},{FDI_VMOVNTDQA, 14, 1034, 57344},{FDI_VPACKUSDW, 45, 1066, 57344},{FDI_VMASKMOVPS, 45, 1066, 57344},{FDI_VMASKMOVPD, 45, 1066, 57344},{FDI_VMASKMOVPS, 39, 1066, 57344},{FDI_VMASKMOVPD, 39, 1066, 57344},{FDI_VPMOVZXBW, 14, 1035, 59392},{FDI_VPMOVZXBD, 14, 1035, 61440},{FDI_VPMOVZXBQ, 14, 1035, 63488},{FDI_VPMOVZXWD, 14, 1035, 59392},{FDI_VPMOVZXWQ, 14, 1035, 61440},{FDI_VPMOVZXDQ, 14, 1035, 59392},{FDI_VPERMD, 45, 1066, 57344},{FDI_VPCMPGTQ, 45, 1066, 57344},{FDI_VPMINSB, 45, 1066, 57344},{FDI_VPMINSD, 45, 1066, 57344},{FDI_VPMINUW, 45, 1066, 57344},{FDI_VPMINUD, 45, 1066, 57344},{FDI_VPMAXSB, 45, 1066, 57344},{FDI_VPMAXSD, 45, 1066, 57344},{FDI_VPMAXUW, 45, 1066, 57344},{FDI_VPMAXUD, 45, 1066, 57344},{FDI_VPMULLD, 45, 1066, 57344},{FDI_VPHMINPOSUW, 14, 1034, 57344},{FDI_VPSRLVD, 45, 1066, 57344},{FDI_VPSRLVQ, 45, 1066, 57344},{FDI_VPSRAVD, 45, 1066, 57344},{FDI_VPSLLVD, 45, 1066, 57344},{FDI_VPSLLVQ, 45, 1066, 57344},{FDI_VPBROADCASTD, 14, 3080, 57344},{FDI_VPBROADCASTQ, 14, 4104, 57344},{FDI_VBROADCASTI128, 14, 5128, 57344},{FDI_VPBROADCASTB, 14, 1032, 57344},{FDI_VPBROADCASTW, 14, 2056, 57344},{FDI_VPMASKMOVD, 45, 1066, 57344},{FDI_VPMASKMOVQ, 45, 1066, 57344},{FDI_VPMASKMOVD, 39, 1066, 57344},{FDI_VPMASKMOVQ, 39, 1066, 57344},{FDI_VPGATHERDD, 32798, 3112, 57344},{FDI_VPGATHERDQ, 32798, 4136, 57344},{FDI_VPGATHERQD, 32798, 3132, 59392},{FDI_VPGATHERQQ, 32798, 4136, 57344},{FDI_VGATHERDPS, 32798, 3112, 57344},{FDI_VGATHERDPD, 32798, 4136, 57344},{FDI_VGATHERQPS, 32798, 3132, 59392},{FDI_VGATHERQPD, 32798, 4136, 57344},{FDI_VFMADDSUB132PS, 45, 1066, 57344},{FDI_VFMADDSUB132PD, 45, 1066, 57344},{FDI_VFMSUBADD132PS, 45, 1066, 57344},{FDI_VFMSUBADD132PD, 45, 1066, 57344},{FDI_VFMADD132PS, 45, 1066, 57344},{FDI_VFMADD132PD, 45, 1066, 57344},{FDI_VFMADD132SS, 45, 21505, 49152},{FDI_VFMADD132SD, 45, 29697, 49152},{FDI_VFMSUB132PS, 45, 1066, 57344},{FDI_VFMSUB132PD, 45, 1066, 57344},{FDI_VFMSUB132SS, 45, 21505, 49152},{FDI_VFMSUB132SD, 45, 29697, 49152},{FDI_VFNMADD132PS, 45, 1066, 57344},{FDI_VFNMADD132PD, 45, 1066, 57344},{FDI_VFNMADD132SS, 45, 21505, 49152},{FDI_VFNMADD132SD, 45, 29697, 49152},{FDI_VFNMSUB132PS, 45, 1066, 57344},{FDI_VFNMSUB132PD, 45, 1066, 57344},{FDI_VFNMSUB132SS, 45, 21505, 49152},{FDI_VFNMSUB132SD, 45, 29697, 49152},{FDI_VFMADDSUB213PS, 45, 1066, 57344},{FDI_VFMADDSUB213PD, 45, 1066, 57344},{FDI_VFMSUBADD213PS, 45, 1066, 57344},{FDI_VFMSUBADD213PD, 45, 1066, 57344},{FDI_VFMADD213PS, 45, 1066, 57344},{FDI_VFMADD213PD, 45, 1066, 57344},{FDI_VFMADD213SS, 45, 21505, 49152},{FDI_VFMADD213SD, 45, 29697, 49152},{FDI_VFMSUB213PS, 45, 1066, 57344},{FDI_VFMSUB213PD, 45, 1066, 57344},{FDI_VFMSUB213SS, 45, 21505, 49152},{FDI_VFMSUB213SD, 45, 29697, 49152},{FDI_VFNMADD213PS, 45, 1066, 57344},{FDI_VFNMADD213PD, 45, 1066, 57344},{FDI_VFNMADD213SS, 45, 21505, 49152},{FDI_VFNMADD213SD, 45, 29697, 49152},{FDI_VFNMSUB213PS, 45, 1066, 57344},{FDI_VFNMSUB213PD, 45, 1066, 57344},{FDI_VFNMSUB213SS, 45, 21505, 49152},{FDI_VFNMSUB213SD, 45, 29697, 49152},{FDI_VFMADDSUB231PS, 45, 1066, 57344},{FDI_VFMADDSUB231PD, 45, 1066, 57344},{FDI_VFMSUBADD231PS, 45, 1066, 57344},{FDI_VFMSUBADD231PD, 45, 1066, 57344},{FDI_VFMADD231PS, 45, 1066, 57344},{FDI_VFMADD231PD, 45, 1066, 57344},{FDI_VFMADD231SS, 45, 21505, 49152},{FDI_VFMADD231SD, 45, 29697, 49152},{FDI_VFMSUB231PS, 45, 1066, 57344},{FDI_VFMSUB231PD, 45, 1066, 57344},{FDI_VFMSUB231SS, 45, 21505, 49152},{FDI_VFMSUB231SD, 45, 29697, 49152},{FDI_VFNMADD231PS, 45, 1066, 57344},{FDI_VFNMADD231PD, 45, 1066, 57344},{FDI_VFNMADD231SS, 45, 21505, 49152},{FDI_VFNMADD231SD, 45, 29697, 49152},{FDI_VFNMSUB231PS, 45, 1066, 57344},{FDI_VFNMSUB231PD, 45, 1066, 57344},{FDI_VFNMSUB231SS, 45, 21505, 49152},{FDI_VFNMSUB231SD, 45, 29697, 49152},{FDI_VPERMQ, 20558, 1098, 57344},{FDI_VPERMPD, 20558, 1098, 57344},{FDI_VPBLENDD, 20525, 1130, 57344},{FDI_VPERMILPS, 20558, 1098, 57344},{FDI_VPERMILPD, 20558, 1098, 57344},{FDI_VPERM2F128, 20525, 1130, 57344},{FDI_VROUNDPS, 20558, 1098, 57344},{FDI_VROUNDPD, 20558, 1098, 57344},{FDI_VROUNDSS, 20525, 21569, 49152},{FDI_VROUNDSD, 20525, 29761, 49152},{FDI_VBLENDPS, 20525, 1130, 57344},{FDI_VBLENDPD, 20525, 1130, 57344},{FDI_VPBLENDW, 20525, 1130, 57344},{FDI_VPALIGNR, 20525, 1130, 57344},{FDI_VPEXTRB, 20555, 5185, 49152},{FDI_VPEXTRB, 20555, 21569, 49153},{FDI_VPEXTRW, 20555, 13377, 49152},{FDI_VPEXTRW, 20555, 21569, 49153},{FDI_VPEXTRD, 20555, 5186, 49153},{FDI_VPEXTRQ, 20555, 5186, 49153},{FDI_VEXTRACTPS, 20555, 21569, 49153},{FDI_VINSERTF128, 20525, 5224, 57344},{FDI_VEXTRACTF128, 20555, 5192, 57344},{FDI_VCVTPS2PH, 20555, 1099, 59392},{FDI_VPINSRB, 20525, 5185, 49153},{FDI_VINSERTPS, 20525, 21569, 49152},{FDI_VPINSRD, 20525, 5186, 49153},{FDI_VPINSRQ, 20525, 5186, 49153},{FDI_VINSERTI128, 20525, 5224, 57344},{FDI_VEXTRACTI128, 20555, 5192, 57344},{FDI_VDPPS, 20525, 1130, 57344},{FDI_VDPPD, 20525, 1130, 57344},{FDI_VMPSADBW, 20525, 1130, 57344},{FDI_VPCLMULQDQ, 20525, 1130, 57344},{FDI_VPERM2I128, 20525, 1130, 57344},{FDI_VBLENDVPS, 12333, 1194, 57344},{FDI_VBLENDVPD, 12333, 1194, 57344},{FDI_VPBLENDVB, 12333, 1194, 57344},{FDI_VPCMPESTRM, 20558, 1098, 57344},{FDI_VPCMPESTRI, 20558, 1098, 57344},{FDI_VPCMPISTRM, 20558, 1098, 57344},{FDI_VPCMPISTRI, 20558, 1098, 57344},{FDI_ANDN, 45, 1066, 49225},{FDI_BLSR, 50, 1058, 49217},{FDI_BLSMSK, 50, 1058, 49217},{FDI_BLSI, 50, 1058, 49217},{FDI_BEXTR, 30, 1066, 49225},{FDI_RORX, 20558, 1098, 49161},{FDI_BZHI, 30, 1066, 49225},{FDI_PDEP, 45, 1066, 49225},{FDI_PEXT, 45, 1066, 49225},{FDI_MULX, 45, 1066, 49225},{FDI_SHLX, 30, 1066, 49225},{FDI_SHRX, 30, 1066, 49225},{FDI_SARX, 30, 1066, 49225},{FDI_ADCX, 14, 1034, 49161},{FDI_ADOX, 14, 1034, 49161},{FDI_FADD, 3, 3072, 16384},{FDI_FMUL, 3, 3072, 16384},{FDI_FCOM, 3, 3072, 16384},{FDI_FCOMP, 3, 3072, 16384},{FDI_FSUB, 3, 3072, 16384},{FDI_FSUBR, 3, 3072, 16384},{FDI_FDIV, 3, 3072, 16384},{FDI_FDIVR, 3, 3072, 16384},{FDI_FADD, 50, 0, 16580},{FDI_FMUL, 50, 0, 16580},{FDI_FCOM, 50, 0, 16580},{FDI_FCOMP, 50, 0, 16580},{FDI_FSUB, 50, 0, 16580},{FDI_FSUBR, 50, 0, 16580},{FDI_FDIV, 50, 0, 16580},{FDI_FDIVR, 50, 0, 16580},{FDI_FLD, 3, 3072, 16384},{FDI_FST, 3, 3072, 16384},{FDI_FSTP, 3, 3072, 16384},{FDI_FLDENV, 3, 0, 16384},{FDI_FLDCW, 3, 2048, 16384},{FDI_FSTENV, 3, 0, 16384},{FDI_FSTCW, 3, 2048, 16384},{FDI_FLD, 3, 0, 16388},{FDI_FXCH, 3, 0, 16388},{FDI_FNOP, 0, 1024, 16384},{FDI_FCHS, 0, 1024, 16384},{FDI_FABS, 0, 1024, 16384},{FDI_FTST, 0, 1024, 16384},{FDI_FXAM, 0, 1024, 16384},{FDI_FLD1, 0, 1024, 16384},{FDI_FLDL2T, 0, 1024, 16384},{FDI_FLDL2E, 0, 1024, 16384},{FDI_FLDPI, 0, 1024, 16384},{FDI_FLDLG2, 0, 1024, 16384},{FDI_FLDLN2, 0, 1024, 16384},{FDI_FLDZ, 0, 1024, 16384},{FDI_F2XM1, 0, 1024, 16384},{FDI_FYL2X, 0, 1024, 16384},{FDI_FPTAN, 0, 1024, 16384},{FDI_FPATAN, 0, 1024, 16384},{FDI_FXTRACT, 0, 1024, 16384},{FDI_FPREM1, 0, 1024, 16384},{FDI_FDECSTP, 0, 1024, 16384},{FDI_FINCSTP, 0, 1024, 16384},{FDI_FPREM, 0, 1024, 16384},{FDI_FYL2XP1, 0, 1024, 16384},{FDI_FSQRT, 0, 1024, 16384},{FDI_FSINCOS, 0, 1024, 16384},{FDI_FRNDINT, 0, 1024, 16384},{FDI_FSCALE, 0, 1024, 16384},{FDI_FSIN, 0, 1024, 16384},{FDI_FCOS, 0, 1024, 16384},{FDI_FIADD, 3, 3072, 16384},{FDI_FIMUL, 3, 3072, 16384},{FDI_FICOM, 3, 3072, 16384},{FDI_FICOMP, 3, 3072, 16384},{FDI_FISUB, 3, 3072, 16384},{FDI_FISUBR, 3, 3072, 16384},{FDI_FIDIV, 3, 3072, 16384},{FDI_FIDIVR, 3, 3072, 16384},{FDI_FCMOVB, 3, 0, 16388},{FDI_FCMOVE, 3, 0, 16388},{FDI_FCMOVBE, 3, 0, 16388},{FDI_FCMOVU, 3, 0, 16388},{FDI_FUCOMPP, 0, 1024, 16384},{FDI_FILD, 3, 3072, 16384},{FDI_FISTTP, 3, 3072, 16384},{FDI_FIST, 3, 3072, 16384},{FDI_FISTP, 3, 3072, 16384},{FDI_FLD, 3, 0, 16384},{FDI_FSTP, 3, 0, 16384},{FDI_FCMOVNB, 3, 0, 16388},{FDI_FCMOVNE, 3, 0, 16388},{FDI_FCMOVNBE, 3, 0, 16388},{FDI_FCMOVNU, 3, 0, 16388},{FDI_FCLEX, 0, 1024, 16384},{FDI_FINIT, 0, 1024, 16384},{FDI_FUCOMI, 3, 0, 16388},{FDI_FCOMI, 3, 0, 16388},{FDI_FADD, 3, 4096, 16384},{FDI_FMUL, 3, 4096, 16384},{FDI_FCOM, 3, 4096, 16384},{FDI_FCOMP, 3, 4096, 16384},{FDI_FSUB, 3, 4096, 16384},{FDI_FSUBR, 3, 4096, 16384},{FDI_FDIV, 3, 4096, 16384},{FDI_FDIVR, 3, 4096, 16384},{FDI_FADD, 35, 0, 16580},{FDI_FMUL, 35, 0, 16580},{FDI_FSUBR, 35, 0, 16580},{FDI_FSUB, 35, 0, 16580},{FDI_FDIVR, 35, 0, 16580},{FDI_FDIV, 35, 0, 16580},{FDI_FLD, 3, 4096, 16384},{FDI_FISTTP, 3, 4096, 16384},{FDI_FST, 3, 4096, 16384},{FDI_FSTP, 3, 4096, 16384},{FDI_FRSTOR, 3, 0, 16384},{FDI_FSAVE, 3, 0, 16384},{FDI_FSTSW, 3, 2048, 16384},{FDI_FFREE, 3, 0, 16388},{FDI_FST, 3, 0, 16388},{FDI_FSTP, 3, 0, 16388},{FDI_FUCOM, 3, 0, 16388},{FDI_FUCOMP, 3, 0, 16388},{FDI_FIADD, 3, 2048, 16384},{FDI_FIMUL, 3, 2048, 16384},{FDI_FICOM, 3, 2048, 16384},{FDI_FICOMP, 3, 2048, 16384},{FDI_FISUB, 3, 2048, 16384},{FDI_FISUBR, 3, 2048, 16384},{FDI_FIDIV, 3, 2048, 16384},{FDI_FIDIVR, 3, 2048, 16384},{FDI_FADDP, 35, 0, 16580},{FDI_FMULP, 35, 0, 16580},{FDI_FCOMPP, 0, 1024, 16384},{FDI_FSUBRP, 35, 0, 16580},{FDI_FSUBP, 35, 0, 16580},{FDI_FDIVRP, 35, 0, 16580},{FDI_FDIVP, 35, 0, 16580},{FDI_FILD, 3, 2048, 16384},{FDI_FISTTP, 3, 2048, 16384},{FDI_FIST, 3, 2048, 16384},{FDI_FISTP, 3, 2048, 16384},{FDI_FBLD, 3, 0, 16384},{FDI_FILD, 3, 4096, 16384},{FDI_FBSTP, 3, 0, 16384},{FDI_FISTP, 3, 4096, 16384},{FDI_FSTSW, 48, 2048, 16448},{FDI_FUCOMIP, 50, 0, 16580},{FDI_FCOMIP, 50, 0, 16580},{FDI_RSTORSSP, 3, 4096, 49152},{FDI_SETSSBSY, 0, 1024, 49152},{FDI_SAVEPREVSSP, 0, 1024, 49152},{FDI_RDSSP, 3, 1026, 49153},{FDI_ENDBR64, 0, 1024, 49152},{FDI_ENDBR32, 0, 1024, 49152},{FDI_WRUSS, 11, 1034, 49160},{FDI_WRSS, 11, 1034, 49160},{FDI_CLRSSBSY, 3, 4096, 49152},{FDI_INCSSP, 3, 1026, 49153},{FDI_CLDEMOTE, 3, 1024, 49152},{FDI_REP_MONTMUL, 0, 1024, 49152},{FDI_REP_XSHA1, 0, 1024, 49152},{FDI_REP_XSHA256, 0, 1024, 49152},{FDI_XSTORE, 0, 1024, 16384},{FDI_REP_XSTORE, 0, 1024, 49152},{FDI_REP_XCRYPTECB, 0, 1024, 49152},{FDI_REP_XCRYPTCBC, 0, 1024, 49152},{FDI_REP_XCRYPTCTR, 0, 1024, 49152},{FDI_REP_XCRYPTCFB, 0, 1024, 49152},{FDI_REP_XCRYPTOFB, 0, 1024, 49152},{FDI_INVEPT, 14, 5128, 53256},{FDI_INVVPID, 14, 5128, 53256},{FDI_VMCALL, 0, 1024, 49152},{FDI_VMCLEAR, 3, 4096, 49152},{FDI_VMFUNC, 0, 1024, 49152},{FDI_VMLAUNCH, 0, 1024, 49152},{FDI_VMRESUME, 0, 1024, 49152},{FDI_VMPTRLD, 3, 4096, 49152},{FDI_VMPTRST, 3, 4096, 49152},{FDI_VMREAD, 11, 1034, 53257},{FDI_VMWRITE, 14, 1034, 53257},{FDI_VMXOFF, 0, 1024, 49152},{FDI_VMXON, 3, 4096, 49152},{FDI_TDCALL, 0, 1024, 49152},{FDI_SEAMRET, 0, 1024, 49152},{FDI_SEAMOPS, 0, 1024, 49152},{FDI_SEAMCALL, 0, 1024, 49152},{FDI_CLZERO, 48, 1056, 16448},{FDI_RDPRU, 0, 1024, 16384},{FDI_VMRUN, 0, 1024, 16384},{FDI_VMMCALL, 0, 1024, 16384},{FDI_VMGEXIT, 0, 1024, 49152},{FDI_VMLOAD, 0, 1024, 16384},{FDI_VMSAVE, 0, 1024, 16384},{FDI_STGI, 0, 1024, 16384},{FDI_CLGI, 0, 1024, 16384},{FDI_SKINIT, 0, 1024, 16384},{FDI_INVLPGA, 0, 1024, 16384},{FDI_MONITORX, 0, 1024, 49152},{FDI_MCOMMIT, 0, 1024, 49152},{FDI_MWAITX, 0, 1024, 49152},{FDI_INVLPGB, 0, 1024, 49152},{FDI_TLBSYNC, 0, 1024, 49152},{FDI_RMPQUERY, 0, 1024, 49152},{FDI_RMPREAD, 0, 1024, 49152},{FDI_RMPADJUST, 0, 1024, 49152},{FDI_RMPUPDATE, 0, 1024, 49152},{FDI_PSMASH, 0, 1024, 49152},{FDI_PVALIDATE, 0, 1024, 49152},{FDI_TPAUSE, 3, 3072, 49153},{FDI_UMONITOR, 3, 1026, 49153},{FDI_UMWAIT, 3, 3072, 49153},{FDI_PTWRITE, 3, 1026, 49153},{FDI_GF2P8MULB, 14, 1034, 57344},{FDI_GF2P8AFFINEQB, 20558, 1098, 57344},{FDI_GF2P8AFFINEINVQB, 20558, 1098, 57344},{FDI_VGF2P8MULB, 45, 1066, 57344},{FDI_VGF2P8AFFINEQB, 20525, 1130, 57344},{FDI_VGF2P8AFFINEINVQB, 20525, 1130, 57344},{FDI_EVX_GF2P8MULB, 557, 1066, 57344},{FDI_EVX_GF2P8AFFINEQB, 21293, 1130, 57344},{FDI_EVX_GF2P8AFFINEINVQB, 21293, 1130, 57344},{FDI_ENQCMD, 14, 7176, 49160},{FDI_ENQCMDS, 14, 7176, 49160},{FDI_PCONFIG, 0, 1024, 49152},{FDI_WBNOINVD, 0, 1024, 32768},{FDI_RDPKRU, 0, 1024, 49152},{FDI_WRPKRU, 0, 1024, 49152},{FDI_RDFSBASE, 3, 1026, 49153},{FDI_RDGSBASE, 3, 1026, 49153},{FDI_WRFSBASE, 3, 1026, 49153},{FDI_WRGSBASE, 3, 1026, 49153},{FDI_XSAVE, 3, 33024, 49152},{FDI_XRSTOR, 3, 33024, 49152},{FDI_XSAVEOPT, 3, 33024, 49152},{FDI_CLWB, 3, 1024, 49152},{FDI_CLFLUSH, 3, 1024, 49152},{FDI_CLFLUSHOPT, 3, 1024, 49152},{FDI_XRSTORS, 3, 33024, 49152},{FDI_XSAVEC, 3, 33024, 49152},{FDI_XSAVES, 3, 33024, 49152},{FDI_RDRAND, 3, 1026, 16385},{FDI_RDSEED, 3, 1026, 16385},{FDI_RDPID, 3, 1026, 53249},{FDI_INVPCID, 14, 5128, 53256},{FDI_SHA1NEXTE, 14, 5120, 49152},{FDI_SHA1MSG1, 14, 5120, 49152},{FDI_SHA1MSG2, 14, 5120, 49152},{FDI_SHA256RNDS2, 30, 5120, 49152},{FDI_SHA256MSG1, 14, 5120, 49152},{FDI_SHA256MSG2, 14, 5120, 49152},{FDI_SHA1RNDS4, 20558, 5184, 49152},{FDI_XSUSLDTRK, 0, 1024, 49152},{FDI_XRESLDTRK, 0, 1024, 49152},{FDI_VPDPBUUD, 45, 1066, 57344},{FDI_VPDPBUSD, 45, 1066, 57344},{FDI_VPDPBSUD, 45, 1066, 57344},{FDI_VPDPBSSD, 45, 1066, 57344},{FDI_VPDPBUUDS, 45, 1066, 57344},{FDI_VPDPBUSDS, 45, 1066, 57344},{FDI_VPDPBSUDS, 45, 1066, 57344},{FDI_VPDPBSSDS, 45, 1066, 57344},{FDI_VPDPWSSD, 45, 1066, 57344},{FDI_VPDPWSSDS, 45, 1066, 57344},{FDI_VCVTNEOPH2PS, 14, 1034, 57344},{FDI_VCVTNEEPH2PS, 14, 1034, 57344},{FDI_VCVTNEEBF162PS, 14, 1034, 57344},{FDI_VCVTNEOBF162PS, 14, 1034, 57344},{FDI_VBCSTNESH2PS, 14, 2056, 57344},{FDI_VBCSTNEBF162PS, 14, 2056, 57344},{FDI_VCVTNEPS2BF16, 14, 1038, 59392},{FDI_VPMADD52LUQ, 45, 1066, 57344},{FDI_VPMADD52HUQ, 45, 1066, 57344},{FDI_HRESET, 20672, 1088, 49152},{FDI_SERIALIZE, 0, 1024, 49152},{FDI_UIRET, 0, 1024, 49152},{FDI_TESTUI, 0, 1024, 49152},{FDI_CLUI, 0, 1024, 49152},{FDI_STUI, 0, 1024, 49152},{FDI_SENDUIPI, 3, 1026, 53249},{FDI_WRMSRNS, 0, 1024, 49152},{FDI_RDMSRLIST, 0, 1024, 49152},{FDI_WRMSRLIST, 0, 1024, 49152},{FDI_AADD, 11, 1034, 49160},{FDI_AAND, 11, 1034, 49160},{FDI_AXOR, 11, 1034, 49160},{FDI_AOR, 11, 1034, 49160},{FDI_CMPOXADD, 27, 1066, 49224},{FDI_CMPNOXADD, 27, 1066, 49224},{FDI_CMPBXADD, 27, 1066, 49224},{FDI_CMPNBXADD, 27, 1066, 49224},{FDI_CMPZXADD, 27, 1066, 49224},{FDI_CMPNZXADD, 27, 1066, 49224},{FDI_CMPBEXADD, 27, 1066, 49224},{FDI_CMPNBEXADD, 27, 1066, 49224},{FDI_CMPSXADD, 27, 1066, 49224},{FDI_CMPNSXADD, 27, 1066, 49224},{FDI_CMPPXADD, 27, 1066, 49224},{FDI_CMPNPXADD, 27, 1066, 49224},{FDI_CMPLXADD, 27, 1066, 49224},{FDI_CMPNLXADD, 27, 1066, 49224},{FDI_CMPLEXADD, 27, 1066, 49224},{FDI_CMPNLEXADD, 27, 1066, 49224},{FDI_AESENCWIDE128KL, 3, 0, 49152},{FDI_AESDECWIDE128KL, 3, 0, 49152},{FDI_AESENCWIDE256KL, 3, 0, 49152},{FDI_AESDECWIDE256KL, 3, 0, 49152},{FDI_AESENC128KL, 14, 8, 57344},{FDI_LOADIWKEY, 14, 1034, 57344},{FDI_AESDEC128KL, 14, 8, 57344},{FDI_AESENC256KL, 14, 8, 57344},{FDI_AESDEC256KL, 14, 8, 57344},{FDI_ENCODEKEY128, 14, 3072, 49161},{FDI_ENCODEKEY256, 14, 3072, 49161},{FDI_LKGS, 3, 2048, 49153},{FDI_ERETU, 0, 1024, 49152},{FDI_ERETS, 0, 1024, 49152},{FDI_LDTILECFG, 3, 0, 49152},{FDI_STTILECFG, 3, 0, 49152},{FDI_TILERELEASE, 0, 1024, 49152},{FDI_TILEZERO, 12, 0, 49200},{FDI_TILELOADDT1, 14, 0, 49200},{FDI_TILESTORED, 11, 0, 49200},{FDI_TILELOADD, 14, 0, 49200},{FDI_TDPBF16PS, 30, 0, 49398},{FDI_TDPFP16PS, 30, 0, 49398},{FDI_TDPBUUD, 30, 0, 49398},{FDI_TDPBUSD, 30, 0, 49398},{FDI_TDPBSUD, 30, 0, 49398},{FDI_TDPBSSD, 30, 0, 49398},{FDI_TCMMRLFP16PS, 30, 0, 49398},{FDI_TCMMIMFP16PS, 30, 0, 49398},{FDI_PBNDKB, 0, 1024, 49152},{FDI_RDMSR, 16515, 27649, 49153},{FDI_WRMSRNS, 16578, 27649, 49153},{FDI_URDMSR, 11, 4096, 49161},{FDI_UWRMSR, 11, 4096, 49161},{FDI_URDMSR, 16515, 27649, 49153},{FDI_UWRMSR, 16578, 27649, 49153},{FDI_VSM4KEY4, 45, 1066, 57344},{FDI_VSM4RNDS4, 45, 1066, 57344},{FDI_EVX_ADDPS, 813, 1066, 58112},{FDI_EVX_ADDPD, 813, 1066, 58112},{FDI_EVX_ADDSS, 557, 21505, 49920},{FDI_EVX_ADDSD, 557, 29697, 49920},{FDI_EVX_AESENC, 45, 1066, 57344},{FDI_EVX_AESENCLAST, 45, 1066, 57344},{FDI_EVX_AESDEC, 45, 1066, 57344},{FDI_EVX_AESDECLAST, 45, 1066, 57344},{FDI_EVX_ANDPS, 813, 1066, 57344},{FDI_EVX_ANDPD, 813, 1066, 57344},{FDI_EVX_ANDNPS, 813, 1066, 57344},{FDI_EVX_ANDNPD, 813, 1066, 57344},{FDI_EVX_CMPPS, 21293, 1122, 57656},{FDI_EVX_CMPPD, 21293, 1122, 57656},{FDI_EVX_CMPSS, 21037, 17489, 49464},{FDI_EVX_CMPSD, 21037, 25681, 49464},{FDI_EVX_COMISS, 14, 3072, 49408},{FDI_EVX_COMISD, 14, 4096, 49408},{FDI_EVX_CVTDQ2PD, 782, 1035, 59648},{FDI_EVX_CVTPD2DQ, 782, 1038, 60160},{FDI_EVX_CVTDQ2PS, 782, 1034, 58112},{FDI_EVX_CVTPS2DQ, 782, 1034, 58112},{FDI_EVX_CVTPS2PD, 782, 1035, 59648},{FDI_EVX_CVTPD2PS, 782, 1038, 60160},{FDI_EVX_CVTSS2SI, 14, 3080, 49928},{FDI_EVX_CVTSD2SI, 14, 4104, 49928},{FDI_EVX_CVTSS2SD, 557, 21505, 49408},{FDI_EVX_CVTSD2SS, 557, 29697, 49920},{FDI_EVX_CVTSI2SS, 45, 5122, 49921},{FDI_EVX_CVTSI2SD, 45, 5122, 49921},{FDI_EVX_CVTTPD2DQ, 782, 1038, 59648},{FDI_EVX_CVTTPS2DQ, 782, 1034, 57600},{FDI_EVX_CVTTSD2SI, 14, 4104, 49416},{FDI_EVX_CVTTSS2SI, 14, 3080, 49416},{FDI_EVX_DIVPS, 813, 1066, 58112},{FDI_EVX_DIVPD, 813, 1066, 58112},{FDI_EVX_DIVSS, 557, 21505, 49920},{FDI_EVX_DIVSD, 557, 29697, 49920},{FDI_EVX_EXTRACTPS, 20555, 21569, 49153},{FDI_EVX_INSERTPS, 20525, 21569, 49152},{FDI_EVX_MAXPS, 813, 1066, 57600},{FDI_EVX_MAXPD, 813, 1066, 57600},{FDI_EVX_MAXSS, 557, 21505, 49408},{FDI_EVX_MAXSD, 557, 29697, 49408},{FDI_EVX_MINPS, 813, 1066, 57600},{FDI_EVX_MINPD, 813, 1066, 57600},{FDI_EVX_MINSS, 557, 21505, 49408},{FDI_EVX_MINSD, 557, 29697, 49408},{FDI_EVX_MOVAPS, 526, 1034, 57344},{FDI_EVX_MOVAPD, 526, 1034, 57344},{FDI_EVX_MOVAPS, 523, 1034, 57344},{FDI_EVX_MOVAPD, 523, 1034, 57344},{FDI_EVX_MOV_X2G, 11, 1034, 49153},{FDI_EVX_MOV_G2X, 14, 1034, 49153},{FDI_EVX_MOVDDUP, 526, 4104, 57344},{FDI_EVX_MOVDDUP, 526, 1034, 57344},{FDI_EVX_MOVDQA32, 526, 1034, 57344},{FDI_EVX_MOVDQA64, 526, 1034, 57344},{FDI_EVX_MOVDQA32, 523, 1034, 57344},{FDI_EVX_MOVDQA64, 523, 1034, 57344},{FDI_EVX_MOVDQU32, 526, 1034, 57344},{FDI_EVX_MOVDQU64, 526, 1034, 57344},{FDI_EVX_MOVDQU32, 523, 1034, 57344},{FDI_EVX_MOVDQU64, 523, 1034, 57344},{FDI_EVX_MOVDQU8, 526, 1034, 57344},{FDI_EVX_MOVDQU16, 526, 1034, 57344},{FDI_EVX_MOVDQU8, 523, 1034, 57344},{FDI_EVX_MOVDQU16, 523, 1034, 57344},{FDI_EVX_MOVLPS, 45, 29697, 49152},{FDI_EVX_MOVHLPS, 45, 5120, 49152},{FDI_EVX_MOVLPD, 45, 29697, 49152},{FDI_EVX_MOVLPS, 11, 4096, 49152},{FDI_EVX_MOVLPD, 11, 4096, 49152},{FDI_EVX_MOVHPS, 45, 29713, 49152},{FDI_EVX_MOVLHPS, 45, 29713, 49152},{FDI_EVX_MOVHPD, 45, 29713, 49152},{FDI_EVX_MOVHPS, 11, 4096, 49152},{FDI_EVX_MOVHPD, 11, 4096, 49152},{FDI_EVX_MOVNTDQA, 14, 1034, 57344},{FDI_EVX_MOVNTDQ, 11, 1034, 57344},{FDI_EVX_MOVNTPS, 11, 1034, 57344},{FDI_EVX_MOVNTPD, 11, 1034, 57344},{FDI_EVX_MOVQ, 14, 4096, 49152},{FDI_EVX_MOVQ, 11, 4096, 49152},{FDI_EVX_MOVSS, 526, 21505, 49152},{FDI_EVX_MOVSS, 557, 21505, 49152},{FDI_EVX_MOVSD, 526, 29697, 49152},{FDI_EVX_MOVSD, 557, 29697, 49152},{FDI_EVX_MOVSS, 523, 3072, 49152},{FDI_EVX_MOVSS, 551, 21508, 49152},{FDI_EVX_MOVSD, 523, 4096, 49152},{FDI_EVX_MOVSD, 551, 29700, 49152},{FDI_EVX_MOVSLDUP, 526, 1034, 57344},{FDI_EVX_MOVSHDUP, 526, 1034, 57344},{FDI_EVX_MOVUPS, 526, 1034, 57344},{FDI_EVX_MOVUPD, 526, 1034, 57344},{FDI_EVX_MOVUPS, 523, 1034, 57344},{FDI_EVX_MOVUPD, 523, 1034, 57344},{FDI_EVX_MULPS, 813, 1066, 58112},{FDI_EVX_MULPD, 813, 1066, 58112},{FDI_EVX_MULSS, 557, 21505, 49920},{FDI_EVX_MULSD, 557, 29697, 49920},{FDI_EVX_ORPS, 813, 1066, 57344},{FDI_EVX_ORPD, 813, 1066, 57344},{FDI_EVX_PABSB, 526, 1034, 57344},{FDI_EVX_PABSW, 526, 1034, 57344},{FDI_EVX_PABSD, 782, 1034, 57344},{FDI_EVX_PABSQ, 782, 1034, 57344},{FDI_EVX_PACKSSWB, 557, 1066, 57344},{FDI_EVX_PACKUSWB, 557, 1066, 57344},{FDI_EVX_PACKSSDW, 813, 1066, 57344},{FDI_EVX_PACKUSDW, 813, 1066, 57344},{FDI_EVX_PADDB, 557, 1066, 57344},{FDI_EVX_PADDW, 557, 1066, 57344},{FDI_EVX_PADDD, 813, 1066, 57344},{FDI_EVX_PADDQ, 813, 1066, 57344},{FDI_EVX_PADDSB, 557, 1066, 57344},{FDI_EVX_PADDSW, 557, 1066, 57344},{FDI_EVX_PADDUSB, 557, 1066, 57344},{FDI_EVX_PADDUSW, 557, 1066, 57344},{FDI_EVX_PALIGNR, 21037, 1130, 57344},{FDI_EVX_PANDD, 813, 1066, 57344},{FDI_EVX_PANDQ, 813, 1066, 57344},{FDI_EVX_PANDND, 813, 1066, 57344},{FDI_EVX_PANDNQ, 813, 1066, 57344},{FDI_EVX_PAVGB, 557, 1066, 57344},{FDI_EVX_PAVGW, 557, 1066, 57344},{FDI_EVX_PCLMULQDQ, 20525, 1130, 57344},{FDI_EVX_PCMPEQB, 557, 34, 57400},{FDI_EVX_PCMPEQW, 557, 34, 57400},{FDI_EVX_PCMPEQD, 813, 34, 57400},{FDI_EVX_PCMPEQQ, 813, 34, 57400},{FDI_EVX_PCMPGTB, 557, 34, 57400},{FDI_EVX_PCMPGTW, 557, 34, 57400},{FDI_EVX_PCMPGTD, 813, 34, 57400},{FDI_EVX_PCMPGTQ, 813, 34, 57400},{FDI_EVX_PEXTRB, 20555, 5185, 49152},{FDI_EVX_PEXTRB, 20555, 21569, 49153},{FDI_EVX_PEXTRW, 20558, 21572, 49160},{FDI_EVX_PEXTRW, 20555, 13377, 49152},{FDI_EVX_PEXTRW, 20555, 21569, 49153},{FDI_EVX_PEXTR, 20555, 5186, 49153},{FDI_EVX_PINSR, 20525, 5185, 49153},{FDI_EVX_PINSR, 20525, 13377, 49153},{FDI_EVX_PINSR, 20525, 5186, 49153},{FDI_EVX_PMADDUBSW, 557, 1066, 57344},{FDI_EVX_PMADDWD, 557, 1066, 57344},{FDI_EVX_PMINUB, 557, 1066, 57344},{FDI_EVX_PMAXUB, 557, 1066, 57344},{FDI_EVX_PMINSW, 557, 1066, 57344},{FDI_EVX_PMAXSW, 557, 1066, 57344},{FDI_EVX_PMINSB, 557, 1066, 57344},{FDI_EVX_PMINSD, 813, 1066, 57344},{FDI_EVX_PMINSQ, 813, 1066, 57344},{FDI_EVX_PMINUW, 557, 1066, 57344},{FDI_EVX_PMINUD, 813, 1066, 57344},{FDI_EVX_PMINUQ, 813, 1066, 57344},{FDI_EVX_PMAXSB, 557, 1066, 57344},{FDI_EVX_PMAXSD, 813, 1066, 57344},{FDI_EVX_PMAXSQ, 813, 1066, 57344},{FDI_EVX_PMAXUW, 557, 1066, 57344},{FDI_EVX_PMAXUD, 813, 1066, 57344},{FDI_EVX_PMAXUQ, 813, 1066, 57344},{FDI_EVX_PMOVSXBW, 526, 1035, 59392},{FDI_EVX_PMOVSXBD, 526, 1035, 61440},{FDI_EVX_PMOVSXBQ, 526, 1035, 63488},{FDI_EVX_PMOVSXWD, 526, 1035, 59392},{FDI_EVX_PMOVSXWQ, 526, 1035, 61440},{FDI_EVX_PMOVSXDQ, 526, 1035, 59392},{FDI_EVX_PMOVZXBW, 526, 1035, 59392},{FDI_EVX_PMOVZXBD, 526, 1035, 61440},{FDI_EVX_PMOVZXBQ, 526, 1035, 63488},{FDI_EVX_PMOVZXWD, 526, 1035, 59392},{FDI_EVX_PMOVZXWQ, 526, 1035, 61440},{FDI_EVX_PMOVZXDQ, 526, 1035, 59392},{FDI_EVX_PMULDQ, 813, 1066, 57344},{FDI_EVX_PMULHRSW, 557, 1066, 57344},{FDI_EVX_PMULHUW, 557, 1066, 57344},{FDI_EVX_PMULHW, 557, 1066, 57344},{FDI_EVX_PMULLW, 557, 1066, 57344},{FDI_EVX_PMULLD, 813, 1066, 57344},{FDI_EVX_PMULLQ, 813, 1066, 57344},{FDI_EVX_PMULUDQ, 813, 1066, 57344},{FDI_EVX_PORD, 813, 1066, 57344},{FDI_EVX_PORQ, 813, 1066, 57344},{FDI_EVX_PSADBW, 45, 1066, 57344},{FDI_EVX_PSHUFB, 557, 1066, 57344},{FDI_EVX_PSHUFD, 21326, 1098, 57344},{FDI_EVX_PSHUFHW, 21070, 1098, 57344},{FDI_EVX_PSHUFLW, 21070, 1098, 57344},{FDI_EVX_PSRLW, 21106, 1122, 57344},{FDI_EVX_PSRAW, 21106, 1122, 57344},{FDI_EVX_PSLLW, 21106, 1122, 57344},{FDI_EVX_PSRLD, 21362, 1122, 57344},{FDI_EVX_PSRAD, 21362, 1122, 57344},{FDI_EVX_PSLLD, 21362, 1122, 57344},{FDI_EVX_PSRLQ, 21362, 1122, 57344},{FDI_EVX_PSRAQ, 21362, 1122, 57344},{FDI_EVX_PSLLQ, 21362, 1122, 57344},{FDI_EVX_PSRLW, 557, 5160, 57344},{FDI_EVX_PSRLD, 557, 5160, 57344},{FDI_EVX_PSRLQ, 557, 5160, 57344},{FDI_EVX_PSRAW, 557, 5160, 57344},{FDI_EVX_PSRAD, 557, 5160, 57344},{FDI_EVX_PSRAQ, 557, 5160, 57344},{FDI_EVX_PSLLW, 557, 5160, 57344},{FDI_EVX_PSLLD, 557, 5160, 57344},{FDI_EVX_PSLLQ, 557, 5160, 57344},{FDI_EVX_PSRLDQ, 20594, 1122, 57344},{FDI_EVX_PSLLDQ, 20594, 1122, 57344},{FDI_EVX_PSUBB, 557, 1066, 57344},{FDI_EVX_PSUBW, 557, 1066, 57344},{FDI_EVX_PSUBD, 813, 1066, 57344},{FDI_EVX_PSUBQ, 813, 1066, 57344},{FDI_EVX_PSUBSB, 557, 1066, 57344},{FDI_EVX_PSUBSW, 557, 1066, 57344},{FDI_EVX_PSUBUSB, 557, 1066, 57344},{FDI_EVX_PSUBUSW, 557, 1066, 57344},{FDI_EVX_PUNPCKLBW, 557, 1066, 57344},{FDI_EVX_PUNPCKLWD, 557, 1066, 57344},{FDI_EVX_PUNPCKLDQ, 813, 1066, 57344},{FDI_EVX_PUNPCKLQDQ, 813, 1066, 57344},{FDI_EVX_PUNPCKHBW, 557, 1066, 57344},{FDI_EVX_PUNPCKHWD, 557, 1066, 57344},{FDI_EVX_PUNPCKHDQ, 813, 1066, 57344},{FDI_EVX_PUNPCKHQDQ, 813, 1066, 57344},{FDI_EVX_PXORD, 813, 1066, 57344},{FDI_EVX_PXORQ, 813, 1066, 57344},{FDI_EVX_SHUFPS, 21293, 1130, 57344},{FDI_EVX_SHUFPD, 21293, 1130, 57344},{FDI_EVX_SQRTPS, 782, 1034, 58112},{FDI_EVX_SQRTPD, 782, 1034, 58112},{FDI_EVX_SQRTSS, 557, 21505, 49920},{FDI_EVX_SQRTSD, 557, 29697, 49920},{FDI_EVX_SUBPS, 813, 1066, 58112},{FDI_EVX_SUBPD, 813, 1066, 58112},{FDI_EVX_SUBSS, 557, 21505, 49920},{FDI_EVX_SUBSD, 557, 29697, 49920},{FDI_EVX_UCOMISS, 14, 3072, 49408},{FDI_EVX_UCOMISD, 14, 4096, 49408},{FDI_EVX_UNPCKLPS, 813, 1066, 57344},{FDI_EVX_UNPCKLPD, 813, 1066, 57344},{FDI_EVX_UNPCKHPS, 813, 1066, 57344},{FDI_EVX_UNPCKHPD, 813, 1066, 57344},{FDI_EVX_ALIGND, 21293, 1130, 57344},{FDI_EVX_ALIGNQ, 21293, 1130, 57344},{FDI_EVX_BLENDMPS, 813, 1066, 57344},{FDI_EVX_BLENDMPD, 813, 1066, 57344},{FDI_EVX_BROADCASTSS, 526, 3080, 57344},{FDI_EVX_BROADCASTF32X2, 526, 4104, 57344},{FDI_EVX_BROADCASTSD, 526, 4104, 57344},{FDI_EVX_BROADCASTF32X4, 526, 5128, 57344},{FDI_EVX_BROADCASTF64X2, 526, 5128, 57344},{FDI_EVX_BROADCASTF32X8, 526, 6152, 57344},{FDI_EVX_BROADCASTF64X4, 526, 6152, 57344},{FDI_EVX_COMPRESSPS, 523, 3080, 57344},{FDI_EVX_COMPRESSPS, 523, 1034, 57344},{FDI_EVX_COMPRESSPD, 523, 4104, 57344},{FDI_EVX_COMPRESSPD, 523, 1034, 57344},{FDI_EVX_CVTNE2PS2BF16, 813, 1066, 57344},{FDI_EVX_CVTNEPS2BF16, 782, 1038, 59392},{FDI_EVX_CVTPS2QQ, 782, 1035, 60160},{FDI_EVX_CVTPD2QQ, 782, 1034, 58112},{FDI_EVX_CVTPS2UDQ, 782, 1034, 58112},{FDI_EVX_CVTPD2UDQ, 782, 1038, 60160},{FDI_EVX_CVTPS2UQQ, 782, 1035, 60160},{FDI_EVX_CVTPD2UQQ, 782, 1034, 58112},{FDI_EVX_CVTPH2PS, 526, 1035, 59648},{FDI_EVX_CVTPS2PH, 21067, 1099, 59648},{FDI_EVX_CVTQQ2PD, 782, 1034, 58112},{FDI_EVX_CVTQQ2PS, 782, 1038, 60160},{FDI_EVX_CVTSD2USI, 14, 4104, 49928},{FDI_EVX_CVTSS2USI, 14, 3080, 49928},{FDI_EVX_CVTUSI2SD, 45, 5122, 49921},{FDI_EVX_CVTUSI2SS, 45, 5122, 49921},{FDI_EVX_CVTTPS2QQ, 782, 1035, 59648},{FDI_EVX_CVTTPD2QQ, 782, 1034, 57600},{FDI_EVX_CVTTPS2UDQ, 782, 1034, 57600},{FDI_EVX_CVTTPD2UDQ, 782, 1038, 59648},{FDI_EVX_CVTTPS2UQQ, 782, 1035, 59648},{FDI_EVX_CVTTPD2UQQ, 782, 1034, 57600},{FDI_EVX_CVTTSD2USI, 14, 4104, 49416},{FDI_EVX_CVTTSS2USI, 14, 3080, 49416},{FDI_EVX_CVTUDQ2PD, 782, 1035, 59648},{FDI_EVX_CVTUDQ2PS, 782, 1034, 58112},{FDI_EVX_CVTUQQ2PD, 782, 1034, 58112},{FDI_EVX_CVTUQQ2PS, 782, 1038, 60160},{FDI_EVX_DBPSADBW, 21037, 1130, 57344},{FDI_EVX_DPBF16PS, 813, 1066, 57344},{FDI_EVX_EXPANDPS, 526, 3080, 57344},{FDI_EVX_EXPANDPS, 526, 1034, 57344},{FDI_EVX_EXPANDPD, 526, 4104, 57344},{FDI_EVX_EXPANDPD, 526, 1034, 57344},{FDI_EVX_EXTRACTF32X4, 21067, 5192, 57344},{FDI_EVX_EXTRACTF64X2, 21067, 5192, 57344},{FDI_EVX_EXTRACTF32X8, 21067, 6216, 57344},{FDI_EVX_EXTRACTF64X4, 21067, 6216, 57344},{FDI_EVX_EXTRACTI32X4, 21067, 5192, 57344},{FDI_EVX_EXTRACTI64X2, 21067, 5192, 57344},{FDI_EVX_EXTRACTI32X8, 21067, 6216, 57344},{FDI_EVX_EXTRACTI64X4, 21067, 6216, 57344},{FDI_EVX_FIXUPIMMPS, 21293, 1130, 57600},{FDI_EVX_FIXUPIMMPD, 21293, 1130, 57600},{FDI_EVX_FIXUPIMMSS, 21037, 21569, 49408},{FDI_EVX_FIXUPIMMSD, 21037, 29761, 49408},{FDI_EVX_FMADDSUB132PS, 813, 1066, 58112},{FDI_EVX_FMADDSUB132PD, 813, 1066, 58112},{FDI_EVX_FMSUBADD132PS, 813, 1066, 58112},{FDI_EVX_FMSUBADD132PD, 813, 1066, 58112},{FDI_EVX_FMADD132PS, 813, 1066, 58112},{FDI_EVX_FMADD132PD, 813, 1066, 58112},{FDI_EVX_FMADD132SS, 557, 21505, 49920},{FDI_EVX_FMADD132SD, 557, 29697, 49920},{FDI_EVX_FMSUB132PS, 813, 1066, 58112},{FDI_EVX_FMSUB132PD, 813, 1066, 58112},{FDI_EVX_FMSUB132SS, 557, 21505, 49920},{FDI_EVX_FMSUB132SD, 557, 29697, 49920},{FDI_EVX_FNMADD132PS, 813, 1066, 58112},{FDI_EVX_FNMADD132PD, 813, 1066, 58112},{FDI_EVX_FNMADD132SS, 557, 21505, 49920},{FDI_EVX_FNMADD132SD, 557, 29697, 49920},{FDI_EVX_FNMSUB132PS, 813, 1066, 58112},{FDI_EVX_FNMSUB132PD, 813, 1066, 58112},{FDI_EVX_FNMSUB132SS, 557, 21505, 49920},{FDI_EVX_FNMSUB132SD, 557, 29697, 49920},{FDI_EVX_FMADDSUB213PS, 813, 1066, 58112},{FDI_EVX_FMADDSUB213PD, 813, 1066, 58112},{FDI_EVX_FMSUBADD213PS, 813, 1066, 58112},{FDI_EVX_FMSUBADD213PD, 813, 1066, 58112},{FDI_EVX_FMADD213PS, 813, 1066, 58112},{FDI_EVX_FMADD213PD, 813, 1066, 58112},{FDI_EVX_FMADD213SS, 557, 21505, 49920},{FDI_EVX_FMADD213SD, 557, 29697, 49920},{FDI_EVX_FMSUB213PS, 813, 1066, 58112},{FDI_EVX_FMSUB213PD, 813, 1066, 58112},{FDI_EVX_FMSUB213SS, 557, 21505, 49920},{FDI_EVX_FMSUB213SD, 557, 29697, 49920},{FDI_EVX_FNMADD213PS, 813, 1066, 58112},{FDI_EVX_FNMADD213PD, 813, 1066, 58112},{FDI_EVX_FNMADD213SS, 557, 21505, 49920},{FDI_EVX_FNMADD213SD, 557, 29697, 49920},{FDI_EVX_FNMSUB213PS, 813, 1066, 58112},{FDI_EVX_FNMSUB213PD, 813, 1066, 58112},{FDI_EVX_FNMSUB213SS, 557, 21505, 49920},{FDI_EVX_FNMSUB213SD, 557, 29697, 49920},{FDI_EVX_FMADDSUB231PS, 813, 1066, 58112},{FDI_EVX_FMADDSUB231PD, 813, 1066, 58112},{FDI_EVX_FMSUBADD231PS, 813, 1066, 58112},{FDI_EVX_FMSUBADD231PD, 813, 1066, 58112},{FDI_EVX_FMADD231PS, 813, 1066, 58112},{FDI_EVX_FMADD231PD, 813, 1066, 58112},{FDI_EVX_FMADD231SS, 557, 21505, 49920},{FDI_EVX_FMADD231SD, 557, 29697, 49920},{FDI_EVX_FMSUB231PS, 813, 1066, 58112},{FDI_EVX_FMSUB231PD, 813, 1066, 58112},{FDI_EVX_FMSUB231SS, 557, 21505, 49920},{FDI_EVX_FMSUB231SD, 557, 29697, 49920},{FDI_EVX_FNMADD231PS, 813, 1066, 58112},{FDI_EVX_FNMADD231PD, 813, 1066, 58112},{FDI_EVX_FNMADD231SS, 557, 21505, 49920},{FDI_EVX_FNMADD231SD, 557, 29697, 49920},{FDI_EVX_FNMSUB231PS, 813, 1066, 58112},{FDI_EVX_FNMSUB231PD, 813, 1066, 58112},{FDI_EVX_FNMSUB231SS, 557, 21505, 49920},{FDI_EVX_FNMSUB231SD, 557, 29697, 49920},{FDI_EVX_FPCLASSPS, 21326, 1090, 57400},{FDI_EVX_FPCLASSPD, 21326, 1090, 57400},{FDI_EVX_FPCLASSSS, 21070, 17473, 49208},{FDI_EVX_FPCLASSSD, 21070, 25665, 49208},{FDI_EVX_GATHERDPS, 33294, 3080, 57344},{FDI_EVX_GATHERDPD, 33294, 4104, 57344},{FDI_EVX_GATHERQPS, 33294, 3084, 59392},{FDI_EVX_GATHERQPD, 33294, 4104, 57344},{FDI_EVX_GETEXPPS, 782, 1034, 57600},{FDI_EVX_GETEXPPD, 782, 1034, 57600},{FDI_EVX_GETEXPSS, 557, 21505, 49408},{FDI_EVX_GETEXPSD, 557, 29697, 49408},{FDI_EVX_GETMANTPS, 21326, 1098, 57600},{FDI_EVX_GETMANTPD, 21326, 1098, 57600},{FDI_EVX_GETMANTSS, 21037, 21569, 49408},{FDI_EVX_GETMANTSD, 21037, 29761, 49408},{FDI_EVX_INSERTF32X4, 21037, 5224, 57344},{FDI_EVX_INSERTF64X2, 21037, 5224, 57344},{FDI_EVX_INSERTF32X8, 21037, 6248, 57344},{FDI_EVX_INSERTF64X4, 21037, 6248, 57344},{FDI_EVX_INSERTI32X4, 21037, 5224, 57344},{FDI_EVX_INSERTI64X2, 21037, 5224, 57344},{FDI_EVX_INSERTI32X8, 21037, 6248, 57344},{FDI_EVX_INSERTI64X4, 21037, 6248, 57344},{FDI_EVX_P2INTERSECTD, 301, 34, 57400},{FDI_EVX_P2INTERSECTQ, 301, 34, 57400},{FDI_EVX_PBLENDMB, 557, 1066, 57344},{FDI_EVX_PBLENDMW, 557, 1066, 57344},{FDI_EVX_PBLENDMD, 813, 1066, 57344},{FDI_EVX_PBLENDMQ, 813, 1066, 57344},{FDI_EVX_PBROADCAST, 526, 1032, 57345},{FDI_EVX_PBROADCAST, 526, 2056, 57345},{FDI_EVX_PBROADCAST, 526, 3080, 57345},{FDI_EVX_PBROADCAST, 526, 4104, 57345},{FDI_EVX_PBROADCASTB, 526, 1032, 57344},{FDI_EVX_PBROADCASTW, 526, 2056, 57344},{FDI_EVX_PBROADCASTD, 526, 3080, 57344},{FDI_EVX_PBROADCASTQ, 526, 4104, 57344},{FDI_EVX_BROADCASTI32X2, 526, 4104, 57344},{FDI_EVX_BROADCASTI32X4, 526, 5128, 57344},{FDI_EVX_BROADCASTI64X2, 526, 5128, 57344},{FDI_EVX_BROADCASTI32X8, 526, 6152, 57344},{FDI_EVX_BROADCASTI64X4, 526, 6152, 57344},{FDI_EVX_PBROADCASTMB2Q, 14, 8, 57351},{FDI_EVX_PBROADCASTMW2D, 14, 8, 57351},{FDI_EVX_PCMPUD, 21293, 98, 57400},{FDI_EVX_PCMPD, 21293, 98, 57400},{FDI_EVX_PCMPUQ, 21293, 98, 57400},{FDI_EVX_PCMPQ, 21293, 98, 57400},{FDI_EVX_PCMPUB, 21037, 98, 57400},{FDI_EVX_PCMPB, 21037, 98, 57400},{FDI_EVX_PCMPUW, 21037, 98, 57400},{FDI_EVX_PCMPW, 21037, 98, 57400},{FDI_EVX_PCOMPRESSB, 523, 1032, 57344},{FDI_EVX_PCOMPRESSB, 523, 1034, 57344},{FDI_EVX_PCOMPRESSW, 523, 2056, 57344},{FDI_EVX_PCOMPRESSW, 523, 1034, 57344},{FDI_EVX_PCOMPRESSD, 523, 3080, 57344},{FDI_EVX_PCOMPRESSD, 523, 1034, 57344},{FDI_EVX_PCOMPRESSQ, 523, 4104, 57344},{FDI_EVX_PCOMPRESSQ, 523, 1034, 57344},{FDI_EVX_PCONFLICTD, 782, 1034, 57344},{FDI_EVX_PCONFLICTQ, 782, 1034, 57344},{FDI_EVX_PDPBUSD, 813, 1066, 57344},{FDI_EVX_PDPBUSDS, 813, 1066, 57344},{FDI_EVX_PDPWSSD, 813, 1066, 57344},{FDI_EVX_PDPWSSDS, 813, 1066, 57344},{FDI_EVX_PERMB, 557, 1066, 57344},{FDI_EVX_PERMW, 557, 1066, 57344},{FDI_EVX_PERMD, 813, 1066, 57344},{FDI_EVX_PERMI2B, 557, 1066, 57344},{FDI_EVX_PERMI2W, 557, 1066, 57344},{FDI_EVX_PERMI2D, 813, 1066, 57344},{FDI_EVX_PERMI2Q, 813, 1066, 57344},{FDI_EVX_PERMI2PS, 813, 1066, 57344},{FDI_EVX_PERMI2PD, 813, 1066, 57344},{FDI_EVX_PERMILPS, 813, 1066, 57344},{FDI_EVX_PERMILPD, 813, 1066, 57344},{FDI_EVX_PERMILPS, 21326, 1098, 57344},{FDI_EVX_PERMILPD, 21326, 1098, 57344},{FDI_EVX_PERMPS, 813, 1066, 57344},{FDI_EVX_PERMPD, 813, 1066, 57344},{FDI_EVX_PERMQ, 813, 1066, 57344},{FDI_EVX_PERMQ, 21326, 1098, 57344},{FDI_EVX_PERMPD, 21326, 1098, 57344},{FDI_EVX_PERMT2B, 557, 1066, 57344},{FDI_EVX_PERMT2W, 557, 1066, 57344},{FDI_EVX_PERMT2D, 813, 1066, 57344},{FDI_EVX_PERMT2Q, 813, 1066, 57344},{FDI_EVX_PERMT2PS, 813, 1066, 57344},{FDI_EVX_PERMT2PD, 813, 1066, 57344},{FDI_EVX_PEXPANDB, 526, 1032, 57344},{FDI_EVX_PEXPANDB, 526, 1034, 57344},{FDI_EVX_PEXPANDW, 526, 2056, 57344},{FDI_EVX_PEXPANDW, 526, 1034, 57344},{FDI_EVX_PEXPANDD, 526, 3080, 57344},{FDI_EVX_PEXPANDD, 526, 1034, 57344},{FDI_EVX_PEXPANDQ, 526, 4104, 57344},{FDI_EVX_PEXPANDQ, 526, 1034, 57344},{FDI_EVX_PGATHERDD, 33294, 3080, 57344},{FDI_EVX_PGATHERDQ, 33294, 4104, 57344},{FDI_EVX_PGATHERQD, 33294, 3084, 59392},{FDI_EVX_PGATHERQQ, 33294, 4104, 57344},{FDI_EVX_PLZCNTD, 782, 1034, 57344},{FDI_EVX_PLZCNTQ, 782, 1034, 57344},{FDI_EVX_PMADD52LUQ, 813, 1066, 57344},{FDI_EVX_PMADD52HUQ, 813, 1066, 57344},{FDI_EVX_PMOVB2M, 14, 2, 57400},{FDI_EVX_PMOVW2M, 14, 2, 57400},{FDI_EVX_PMOVD2M, 14, 2, 57400},{FDI_EVX_PMOVQ2M, 14, 2, 57400},{FDI_EVX_PMOVM2B, 14, 8, 57351},{FDI_EVX_PMOVM2W, 14, 8, 57351},{FDI_EVX_PMOVM2D, 14, 8, 57351},{FDI_EVX_PMOVM2Q, 14, 8, 57351},{FDI_EVX_PMOVWB, 523, 1035, 59392},{FDI_EVX_PMOVSWB, 523, 1035, 59392},{FDI_EVX_PMOVUSWB, 523, 1035, 59392},{FDI_EVX_PMOVDB, 523, 1035, 61440},{FDI_EVX_PMOVSDB, 523, 1035, 61440},{FDI_EVX_PMOVUSDB, 523, 1035, 61440},{FDI_EVX_PMOVQB, 523, 1035, 63488},{FDI_EVX_PMOVSQB, 523, 1035, 63488},{FDI_EVX_PMOVUSQB, 523, 1035, 63488},{FDI_EVX_PMOVDW, 523, 1035, 59392},{FDI_EVX_PMOVSDW, 523, 1035, 59392},{FDI_EVX_PMOVUSDW, 523, 1035, 59392},{FDI_EVX_PMOVQW, 523, 1035, 61440},{FDI_EVX_PMOVSQW, 523, 1035, 61440},{FDI_EVX_PMOVUSQW, 523, 1035, 61440},{FDI_EVX_PMOVQD, 523, 1035, 59392},{FDI_EVX_PMOVSQD, 523, 1035, 59392},{FDI_EVX_PMOVUSQD, 523, 1035, 59392},{FDI_EVX_PMULTISHIFTQB, 813, 1066, 57344},{FDI_EVX_POPCNTB, 526, 1034, 57344},{FDI_EVX_POPCNTW, 526, 1034, 57344},{FDI_EVX_POPCNTD, 782, 1034, 57344},{FDI_EVX_POPCNTQ, 782, 1034, 57344},{FDI_EVX_PRORVD, 813, 1066, 57344},{FDI_EVX_PRORVQ, 813, 1066, 57344},{FDI_EVX_PRORD, 21362, 1122, 57344},{FDI_EVX_PRORQ, 21362, 1122, 57344},{FDI_EVX_PROLVD, 813, 1066, 57344},{FDI_EVX_PROLVQ, 813, 1066, 57344},{FDI_EVX_PROLD, 21362, 1122, 57344},{FDI_EVX_PROLQ, 21362, 1122, 57344},{FDI_EVX_PSCATTERDD, 33291, 3080, 57344},{FDI_EVX_PSCATTERDQ, 33291, 4104, 57344},{FDI_EVX_PSCATTERQD, 33291, 3084, 59392},{FDI_EVX_PSCATTERQQ, 33291, 4104, 57344},{FDI_EVX_PSHLDW, 21037, 1130, 57344},{FDI_EVX_PSHLDD, 21293, 1130, 57344},{FDI_EVX_PSHLDQ, 21293, 1130, 57344},{FDI_EVX_PSHLDVW, 557, 1066, 57344},{FDI_EVX_PSHLDVD, 813, 1066, 57344},{FDI_EVX_PSHLDVQ, 813, 1066, 57344},{FDI_EVX_PSHRDW, 21037, 1130, 57344},{FDI_EVX_PSHRDD, 21293, 1130, 57344},{FDI_EVX_PSHRDQ, 21293, 1130, 57344},{FDI_EVX_PSHRDVW, 557, 1066, 57344},{FDI_EVX_PSHRDVD, 813, 1066, 57344},{FDI_EVX_PSHRDVQ, 813, 1066, 57344},{FDI_EVX_PSHUFBITQMB, 557, 34, 57400},{FDI_EVX_PSLLVW, 557, 1066, 57344},{FDI_EVX_PSLLVD, 813, 1066, 57344},{FDI_EVX_PSLLVQ, 813, 1066, 57344},{FDI_EVX_PSRAVW, 557, 1066, 57344},{FDI_EVX_PSRAVD, 813, 1066, 57344},{FDI_EVX_PSRAVQ, 813, 1066, 57344},{FDI_EVX_PSRLVW, 557, 1066, 57344},{FDI_EVX_PSRLVD, 813, 1066, 57344},{FDI_EVX_PSRLVQ, 813, 1066, 57344},{FDI_EVX_PTERNLOGD, 21293, 1130, 57344},{FDI_EVX_PTERNLOGQ, 21293, 1130, 57344},{FDI_EVX_PTESTMB, 557, 34, 57400},{FDI_EVX_PTESTMW, 557, 34, 57400},{FDI_EVX_PTESTMD, 813, 34, 57400},{FDI_EVX_PTESTMQ, 813, 34, 57400},{FDI_EVX_PTESTNMB, 557, 34, 57400},{FDI_EVX_PTESTNMW, 557, 34, 57400},{FDI_EVX_PTESTNMD, 813, 34, 57400},{FDI_EVX_PTESTNMQ, 813, 34, 57400},{FDI_EVX_RANGEPS, 21293, 1130, 57600},{FDI_EVX_RANGEPD, 21293, 1130, 57600},{FDI_EVX_RANGESS, 21037, 21569, 49408},{FDI_EVX_RANGESD, 21037, 29761, 49408},{FDI_EVX_RCP14PS, 782, 1034, 57344},{FDI_EVX_RCP14PD, 782, 1034, 57344},{FDI_EVX_RCP14SS, 557, 21505, 49152},{FDI_EVX_RCP14SD, 557, 29697, 49152},{FDI_EVX_REDUCEPS, 21326, 1098, 57600},{FDI_EVX_REDUCEPD, 21326, 1098, 57600},{FDI_EVX_REDUCESS, 21037, 21569, 49408},{FDI_EVX_REDUCESD, 21037, 29761, 49408},{FDI_EVX_RNDSCALEPS, 21326, 1098, 57600},{FDI_EVX_RNDSCALEPD, 21326, 1098, 57600},{FDI_EVX_RNDSCALESS, 21037, 21569, 49408},{FDI_EVX_RNDSCALESD, 21037, 29761, 49408},{FDI_EVX_RSQRT14PS, 782, 1034, 57344},{FDI_EVX_RSQRT14PD, 782, 1034, 57344},{FDI_EVX_RSQRT14SS, 557, 21505, 49152},{FDI_EVX_RSQRT14SD, 557, 29697, 49152},{FDI_EVX_SCALEFPS, 813, 1066, 58112},{FDI_EVX_SCALEFPD, 813, 1066, 58112},{FDI_EVX_SCALEFSS, 557, 21505, 49920},{FDI_EVX_SCALEFSD, 557, 29697, 49920},{FDI_EVX_SCATTERDPS, 33291, 3080, 57344},{FDI_EVX_SCATTERDPD, 33291, 4104, 57344},{FDI_EVX_SCATTERQPS, 33291, 3084, 59392},{FDI_EVX_SCATTERQPD, 33291, 4104, 57344},{FDI_EVX_SHUFF32X4, 21293, 1130, 57344},{FDI_EVX_SHUFF64X2, 21293, 1130, 57344},{FDI_EVX_SHUFI32X4, 21293, 1130, 57344},{FDI_EVX_SHUFI64X2, 21293, 1130, 57344},{FDI_EVX_XORPS, 813, 1066, 57344},{FDI_EVX_XORPD, 813, 1066, 57344},{FDI_KANDB, 45, 1024, 49343},{FDI_KANDW, 45, 2048, 49343},{FDI_KANDD, 45, 3072, 49343},{FDI_KANDQ, 45, 4096, 49343},{FDI_KANDNB, 45, 1024, 49343},{FDI_KANDNW, 45, 2048, 49343},{FDI_KANDND, 45, 3072, 49343},{FDI_KANDNQ, 45, 4096, 49343},{FDI_KNOTB, 14, 1024, 49215},{FDI_KNOTW, 14, 2048, 49215},{FDI_KNOTD, 14, 3072, 49215},{FDI_KNOTQ, 14, 4096, 49215},{FDI_KORB, 45, 1024, 49343},{FDI_KORW, 45, 2048, 49343},{FDI_KORD, 45, 3072, 49343},{FDI_KORQ, 45, 4096, 49343},{FDI_KXNORB, 45, 1024, 49343},{FDI_KXNORW, 45, 2048, 49343},{FDI_KXNORD, 45, 3072, 49343},{FDI_KXNORQ, 45, 4096, 49343},{FDI_KXORB, 45, 1024, 49343},{FDI_KXORW, 45, 2048, 49343},{FDI_KXORD, 45, 3072, 49343},{FDI_KXORQ, 45, 4096, 49343},{FDI_KADDB, 45, 1024, 49343},{FDI_KADDW, 45, 2048, 49343},{FDI_KADDD, 45, 3072, 49343},{FDI_KADDQ, 45, 4096, 49343},{FDI_KUNPCKBW, 45, 9220, 49343},{FDI_KUNPCKWD, 45, 18436, 49343},{FDI_KUNPCKDQ, 45, 27652, 49343},{FDI_KORTESTB, 14, 1024, 49215},{FDI_KORTESTW, 14, 2048, 49215},{FDI_KORTESTD, 14, 3072, 49215},{FDI_KORTESTQ, 14, 4096, 49215},{FDI_KMOVB, 14, 1024, 49215},{FDI_KMOVW, 14, 2048, 49215},{FDI_KMOVD, 14, 3072, 49215},{FDI_KMOVQ, 14, 4096, 49215},{FDI_KMOVB, 11, 1024, 49208},{FDI_KMOVW, 11, 2048, 49208},{FDI_KMOVD, 11, 3072, 49208},{FDI_KMOVQ, 11, 4096, 49208},{FDI_KMOVB, 14, 17409, 49209},{FDI_KMOVW, 14, 18433, 49209},{FDI_KMOVD, 14, 3072, 49209},{FDI_KMOVQ, 14, 4096, 49209},{FDI_KMOVB, 14, 17412, 49167},{FDI_KMOVW, 14, 18436, 49167},{FDI_KMOVD, 14, 3072, 49167},{FDI_KMOVQ, 14, 4096, 49167},{FDI_KTESTB, 14, 1024, 49215},{FDI_KTESTW, 14, 2048, 49215},{FDI_KTESTD, 14, 3072, 49215},{FDI_KTESTQ, 14, 4096, 49215},{FDI_KSHIFTRB, 20558, 1088, 49215},{FDI_KSHIFTRW, 20558, 2112, 49215},{FDI_KSHIFTRD, 20558, 3136, 49215},{FDI_KSHIFTRQ, 20558, 4160, 49215},{FDI_KSHIFTLB, 20558, 1088, 49215},{FDI_KSHIFTLW, 20558, 2112, 49215},{FDI_KSHIFTLD, 20558, 3136, 49215},{FDI_KSHIFTLQ, 20558, 4160, 49215},{FDI_EVX_RNDSCALEPH, 21326, 1098, 58624},{FDI_EVX_RNDSCALESH, 21037, 13377, 49408},{FDI_EVX_GETMANTPH, 21326, 1098, 58624},{FDI_EVX_GETMANTSH, 21037, 13377, 49408},{FDI_EVX_REDUCEPH, 21326, 1098, 58624},{FDI_EVX_REDUCESH, 21037, 13377, 49408},{FDI_EVX_FPCLASSPH, 21326, 66, 58424},{FDI_EVX_FPCLASSSH, 21070, 9281, 49208},{FDI_EVX_CMPPH, 21293, 98, 58680},{FDI_EVX_CMPSH, 21037, 9297, 49464},{FDI_EVX_MOVSH, 526, 13313, 49152},{FDI_EVX_MOVSH, 557, 13313, 49152},{FDI_EVX_MOVSH, 523, 2048, 49152},{FDI_EVX_MOVSH, 551, 13316, 49152},{FDI_EVX_CVTSS2SH, 557, 21505, 49920},{FDI_EVX_CVTPS2PHX, 782, 1038, 60160},{FDI_EVX_CVTSI2SH, 45, 5122, 49921},{FDI_EVX_CVTTSH2SI, 14, 2056, 49416},{FDI_EVX_CVTSH2SI, 14, 2056, 49928},{FDI_EVX_UCOMISH, 14, 2048, 49408},{FDI_EVX_COMISH, 14, 2048, 49408},{FDI_EVX_SQRTPH, 782, 1034, 59136},{FDI_EVX_SQRTSH, 557, 13313, 49920},{FDI_EVX_ADDPH, 813, 1066, 59136},{FDI_EVX_ADDSH, 557, 13313, 49920},{FDI_EVX_MULPH, 813, 1066, 59136},{FDI_EVX_MULSH, 557, 13313, 49920},{FDI_EVX_CVTPH2PD, 782, 1035, 62720},{FDI_EVX_CVTPD2PH, 782, 1038, 62208},{FDI_EVX_CVTSH2SD, 557, 13313, 49408},{FDI_EVX_CVTSD2SH, 557, 29697, 49920},{FDI_EVX_CVTDQ2PH, 782, 1038, 60160},{FDI_EVX_CVTQQ2PH, 782, 1038, 62208},{FDI_EVX_CVTPH2DQ, 782, 1035, 61184},{FDI_EVX_CVTTPH2DQ, 782, 1035, 60672},{FDI_EVX_SUBPH, 813, 1066, 59136},{FDI_EVX_SUBSH, 557, 13313, 49920},{FDI_EVX_MINPH, 813, 1066, 58624},{FDI_EVX_MINSH, 557, 13313, 49408},{FDI_EVX_DIVPH, 813, 1066, 59136},{FDI_EVX_DIVSH, 557, 13313, 49920},{FDI_EVX_MAXPH, 813, 1066, 58624},{FDI_EVX_MAXSH, 557, 13313, 49408},{FDI_EVX_MOVW_G2X, 14, 13313, 49153},{FDI_EVX_CVTTPH2UDQ, 782, 1035, 60672},{FDI_EVX_CVTTPH2UQQ, 782, 1035, 62720},{FDI_EVX_CVTTSH2USI, 14, 2056, 49416},{FDI_EVX_CVTPH2UDQ, 782, 1035, 61184},{FDI_EVX_CVTPH2UQQ, 782, 1035, 63232},{FDI_EVX_CVTSH2USI, 14, 2056, 49928},{FDI_EVX_CVTTPH2QQ, 782, 1035, 62720},{FDI_EVX_CVTUDQ2PH, 782, 1038, 60160},{FDI_EVX_CVTUQQ2PH, 782, 1038, 62208},{FDI_EVX_CVTPH2QQ, 782, 1035, 63232},{FDI_EVX_CVTUSI2SH, 45, 5122, 49921},{FDI_EVX_CVTTPH2UW, 782, 1034, 58624},{FDI_EVX_CVTTPH2W, 782, 1034, 58624},{FDI_EVX_CVTPH2UW, 782, 1034, 59136},{FDI_EVX_CVTPH2W, 782, 1034, 59136},{FDI_EVX_CVTW2PH, 782, 1034, 59136},{FDI_EVX_CVTUW2PH, 782, 1034, 59136},{FDI_EVX_MOVW_X2G, 11, 2048, 49153},{FDI_EVX_CVTPH2PSX, 782, 1035, 60672},{FDI_EVX_CVTSH2SS, 557, 13313, 49408},{FDI_EVX_SCALEFPH, 813, 1066, 59136},{FDI_EVX_SCALEFSH, 557, 13313, 49920},{FDI_EVX_GETEXPPH, 782, 1034, 58624},{FDI_EVX_GETEXPSH, 557, 13313, 49408},{FDI_EVX_RCPPH, 782, 1034, 58368},{FDI_EVX_RCPSH, 557, 13313, 49152},{FDI_EVX_RSQRTPH, 782, 1034, 58368},{FDI_EVX_RSQRTSH, 557, 13313, 49152},{FDI_EVX_FMADDCPH, 813, 1066, 58112},{FDI_EVX_FCMADDCPH, 813, 1066, 58112},{FDI_EVX_FMADDCSH, 557, 21505, 49920},{FDI_EVX_FCMADDCSH, 557, 21505, 49920},{FDI_EVX_FMULCPH, 813, 1066, 58112},{FDI_EVX_FCMULCPH, 813, 1066, 58112},{FDI_EVX_FMULCSH, 557, 21505, 49920},{FDI_EVX_FCMULCSH, 557, 21505, 49920},{FDI_EVX_FMADDSUB132PH, 813, 1066, 59136},{FDI_EVX_FMADDSUB213PH, 813, 1066, 59136},{FDI_EVX_FMADDSUB231PH, 813, 1066, 59136},{FDI_EVX_FMSUBADD132PH, 813, 1066, 59136},{FDI_EVX_FMSUBADD213PH, 813, 1066, 59136},{FDI_EVX_FMSUBADD231PH, 813, 1066, 59136},{FDI_EVX_FMADD132PH, 813, 1066, 59136},{FDI_EVX_FMADD213PH, 813, 1066, 59136},{FDI_EVX_FMADD231PH, 813, 1066, 59136},{FDI_EVX_FMADD132SH, 557, 13313, 49920},{FDI_EVX_FMADD213SH, 557, 13313, 49920},{FDI_EVX_FMADD231SH, 557, 13313, 49920},{FDI_EVX_FMSUB132PH, 813, 1066, 59136},{FDI_EVX_FMSUB213PH, 813, 1066, 59136},{FDI_EVX_FMSUB231PH, 813, 1066, 59136},{FDI_EVX_FMSUB132SH, 557, 13313, 49920},{FDI_EVX_FMSUB213SH, 557, 13313, 49920},{FDI_EVX_FMSUB231SH, 557, 13313, 49920},{FDI_EVX_FNMADD132PH, 813, 1066, 59136},{FDI_EVX_FNMADD213PH, 813, 1066, 59136},{FDI_EVX_FNMADD231PH, 813, 1066, 59136},{FDI_EVX_FNMADD132SH, 557, 13313, 49920},{FDI_EVX_FNMADD213SH, 557, 13313, 49920},{FDI_EVX_FNMADD231SH, 557, 13313, 49920},{FDI_EVX_FNMSUB132PH, 813, 1066, 59136},{FDI_EVX_FNMSUB213PH, 813, 1066, 59136},{FDI_EVX_FNMSUB231PH, 813, 1066, 59136},{FDI_EVX_FNMSUB132SH, 557, 13313, 49920},{FDI_EVX_FNMSUB213SH, 557, 13313, 49920},{FDI_EVX_FNMSUB231SH, 557, 13313, 49920} +#elif defined(FD_DECODE_TABLE_STRTAB1) +"xtestuiretf2xm1xsusldtrkaddbextrclacall farplahfabsfencenclslarcrc32xsetbvaddpdepbndkblsidtcmmimfp16pshufwaitcmmrlfp16psmasha1msg1xsavesahfaddpconfigetsecbw cwdecdqencluincsspopaaaddaamcommitdcalldtilecfgxsaveoptwritenclvaddphltrdfsbaseamcalldsarxabortdpbf16psaveprevsspopfbldasbblsmskinitdpbssdxsaveclcldemotencodekey128xrstorssprefetchit0xresldtrkadddxlatblsrdgsbaseamopscaseamretdpbsud0xgetbvaddpsenduipinsertqxendbr32xbegint1wrusserializencodekey256wrssetaandwrpkrud1wrmsrnsetbendbr64wrmsrlistaclflushoptdpbusdwrgsbasetclgint3dnowbinvdbpsadbwbnoinvdivpdpbssdsetgenqcmdsetleaverrdmsrlistgintoutsetnclidtdpbuud2wrfsbasetnovzeroupperetsetnprefetchit1vzeroallfenceretumonitorxvxorpsetnsetnzvxorpdvunpcklpsetovunpcklpdvunpckhpsetpausetssbsyscallfsaverwvunpckhpdvucomissetzcntdpfp16psgdtileloaddt1vucomisha1msg2vucomisdvtestpsha1nextevtestpdvsubssha1rnds4vsubsha256msg1vsubsdvsubpsha256msg2vsubphresetilereleasevsubpdvstmxcsrdpidvsqrtssha256rnds2vsqrtshlxvsqrtsdvsqrtpshrxvsqrtphvsqrtpdvsm4rnds4vsm4key4vshufpsmswapgstosttilecfgvshufpdvshufi64x2vshufi32x4vshuff64x2vshuff32x4vscatterqpsysenterdpkrumwaitxvscatterqpdvscatterdpsysexitilestoredvscatterdpdvscalefssysretilezerorxvscalefshvscalefsdvscalefpsvscalefphvscalefpdvrsqrtssvrsqrtshvrsqrtpsvrsqrtphvrsqrt14ssvrsqrt14sdvrsqrt14psvrsqrt14pdvroundssvroundsdvroundpsvroundpdvrndscalessvrndscaleshvrndscalesdvrndscalepsvrndscalephvrndscalepdvreducessvreduceshvreducesdvreducepsvreducephvreducepdvrcpssvrcpshvrcppsvrcpphvrcp14ssvrcp14sdvrcp14psvrcp14pdvrangessvrangesdvrangepsvrangepdvpxorqvpxordpmclrssbsyvpunpcklwdvpunpcklqdqvpunpckldqvpunpcklbwvpunpckhwdvpunpckhqdqvpunpckhdqvpunpckhbwvptestnmwvptestnmqvptestnmdvptestnmboundvptestmwvptestmqvptestmdvptestmbsrdprurdmsrdrandvpternlogqvpternlogdvpsubwvpsubuswvpsubusbswaprefetchntaasvpsubswvpsubsbtcltsvpsubqvpsubdvpsubbtrdseedvpsrlwvpsrlvwvpsrlvqvpsrlvdivphadddvpsrlqvpsrldqvpsrawvpsravwvpsravqvpsravdivpsadbwvpsraqvpsradcxvpsllwvpsllvwvpsllvqvpsllvdivsdvpsllqvpslldqvpsignwvpsigndvpsignbtsvpshuflwvpshufhwvpshufdecstprefetcht0vpshufbitqmbzhinveptlbsynclwbvpshrdwvpshrdvwvpshrdvqvpshrdvdivshvpshrdqvpshrddvpshldwvpshldvwvpshldvqvpshldvdivssvpshldqvpshlddvpscatterqqvpscatterqdvpscatterdqvpscatterddvprorvqvprorvdpbf16psvprorqvprordssprefetcht1vprolvqvprolvdppdvprolqvproldvporqvpordtscpuidvpopcntwvpopcntqvpopcntdvpopcntbvpmuludqvpmultishiftqbvpmullwvpmullqvpmulldvpmulhwvpmulhuwrmsrep montmulxvpmulhrswvpmuldqvpmovzxwqvpmovzxwdvpmovzxdqvpmovzxbwvpmovzxbqvpmovzxbdvpmovwbvpmovw2mfencevpmovuswbvpmovusqwvpmovusqdvpmovusqbvpmovusdwvpmovusdbvpmovsxwqvpmovsxwdvpmovsxdqvpmovsxbwvpmovsxbqvpmovsxbdvpmovswbvpmovsqwvpmovsqdvpmovsqbvpmovsdwvpmovsdbvpmovqwvpmovqdvpmovqbvpmovq2movdir64bvpmovmskbvpmovm2wvpmovm2qvpmovm2dvpmovm2bvpmovdwvpmovdbvpmovd2movdirinvlpgadoxvpmovb2movdq2qvpminuwvpminuqvpminudvpminubvpminswvpminsqvpminsdvpminsbvpmaxuwvpmaxuqvpmaxudvpmaxubvpmaxswvpmaxsqvpmaxsdvpmaxsbvpmaskmovq2dqvpmaskmovdppsvpmaddwdvpmaddubswvpmadd52luqvpmadd52huqvplzcntqvplzcntdvpinsrwvpinsrqvpinsrdvpinsrbvphsubwvphsubswvphsubdvphminposuwvphaddwvphaddswvpgatherqqvpgatherqdvpgatherdqvpgatherddvpextrwvpextrqvpextrdvpextrbvpexpandwvpexpandqvpexpanddvpexpandbvpermwvpermt2wvpermt2qvpermt2psvpermt2pdvpermt2dvpermt2bvpermqvpermpsvpermpdvpermilpsvpermilpdvpermi2wvpermi2qvpermi2psvpermi2pdvpermi2dvpermi2bvpermdvpermbvperm2i128vperm2f128vpdpwssdsvpdpbuudsvpdpbusdsvpdpbsudsvpconflictqvpconflictdvpcompresswvpcompressqvpcompressdvpcompressbvpcmpwvpcmpuwvpcmpuqvpcmpudvpcmpubvpcmpqvpcmpistrmpadjustvpcmpistrinvlpgbvpcmpgtwvpcmpgtqvpcmpgtdvpcmpgtbvpcmpestrmpqueryvpcmpestrinvpcidvpcmpeqwvpcmpeqqvpcmpeqdvpcmpeqbvpcmpdvpcmpbexaddvpclmulqdqvpbroadcastwvpbroadcastqvpbroadcastmw2dvpbroadcastmb2qvpbroadcastdvpbroadcastbvpblendwvpblendvbcstnebf162psvpblendmwvpblendmqvpblendmdvpblendmbvpblenddvpavgwvpavgbvpandqvpandnqvpandndvpanddvpalignrep xcryptcbclzerovpaddwvpadduswvpaddusbvpaddswvpaddsbvpaddqvpadddvpaddbvpackuswbvpackusdwvpacksswbvpackssdwvpabswvpabsqvpabsdvpabsbvp2intersectqvp2intersectdvorpsvorpdvmxonegvmxoffreevmwritevmulssvmulshvmulsdvmulpsvmulphvmulpdvmsavexpandpdvmrunvmresumevmreadvmptrstvmptrldvmpsadbwvmovwvmovupsvmovupdvmovssvmovslduprefetcht2vmovshduprefetchwt1vmovsdvmovqvmovntpsvmovntpdvmovntdqaesdec128klgdtvmovmskpsvmovmskpdvmovlpsvmovlpdvmovlhpsvmovhpsvmovhpdvmovhlpsvmovdqu8vmovdqu64vmovdqu32vmovdqu16vmovdqa64vmovdqa32vmovddupushaesdec256klgsvmovapsvmovapdvmmcallkgsvmloadiwkeyvmlaunchvminssvminshvminsdvminpsvminphvminpdvmgexitvmfuncmcmovaddsdvmclearep xcryptcfbstpushfchsvmcallmswvmaxssvmaxshvmaxsdvmaxpsvmaxphvmaxpdvmaskmovpsvmaskmovpdvmaskmovdquvldmxcsrep xcryptctrep xcryptecbvlddquvinsertpsvinserti64x4vinserti64x2vinserti32x8vinserti32x4vinserti128vinsertf64x4vinsertf64x2vinsertf32x8vinsertf32x4vinsertf128vhsubpsvhsubpdvhaddpsvhaddpdvgf2p8mulbvgf2p8affineqbvgf2p8affineinvqbvgetmantssvgetmantshvgetmantsdvgetmantpsvgetmantphvgetmantpdvgetexpssvgetexpshvgetexpsdvgetexppsvgetexpphvgetexppdvgatherqpsvgatherqpdvgatherdpsvgatherdpdvfpclassssvfpclassshvfpclasssdvfpclasspsvfpclassphvfpclasspdvfnmsub231ssvfnmsub231shvfnmsub231sdvfnmsub231psvfnmsub231phvfnmsub231pdvfnmsub213ssvfnmsub213shvfnmsub213sdvfnmsub213psvfnmsub213phvfnmsub213pdvfnmsub132ssvfnmsub132shvfnmsub132sdvfnmsub132psvfnmsub132phvfnmsub132pdvfnmadd231ssvfnmadd231shvfnmadd231sdvfnmadd231psvfnmadd231phvfnmadd231pdvfnmadd213ssvfnmadd213shvfnmadd213sdvfnmadd213psvfnmadd213phvfnmadd213pdvfnmadd132ssvfnmadd132shvfnmadd132sdvfnmadd132psvfnmadd132phvfnmadd132pdvfmulcshvfmulcphvfmsubadd231psvfmsubadd231phvfmsubadd231pdvfmsubadd213psvfmsubadd213phvfmsubadd213pdvfmsubadd132psvfmsubadd132phvfmsubadd132pdvfmsub231ssvfmsub231shvfmsub231sdvfmsub231psvfmsub231phvfmsub231pdvfmsub213ssvfmsub213shvfmsub213sdvfmsub213psvfmsub213phvfmsub213pdvfmsub132ssvfmsub132shvfmsub132sdvfmsub132psvfmsub132phvfmsub132pdvfmaddsub231psvfmaddsub231phvfmaddsub231pdvfmaddsub213psvfmaddsub213phvfmaddsub213pdvfmaddsub132psvfmaddsub132phvfmaddsub132pdvfmaddcshvfmaddcphvfmadd231ssvfmadd231shvfmadd231sdvfmadd231psvfmadd231phvfmadd231pdvfmadd213ssvfmadd213shvfmadd213sdvfmadd213psvfmadd213phvfmadd213pdvfmadd132ssvfmadd132shvfmadd132sdvfmadd132psvfmadd132phvfmadd132pdvfixupimmssvfixupimmsdvfixupimmpsvfixupimmpdvfcmulcshvfcmulcphvfcmaddcshvfcmaddcphvextractpsvextracti64x4vextracti64x2vextracti32x8vextracti32x4vextracti128vextractf64x4vextractf64x2vextractf32x8vextractf32x4vextractf128vexpandpsvcvtw2phvcvtuw2phvcvtusi2ssvcvtusi2shvcvtusi2sdvcvtuqq2psvcvtuqq2phvcvtuqq2pdvcvtudq2psvcvtudq2phvcvtudq2pdvcvttss2usinvvpidvcvttss2sivcvttsh2usivcvttsh2sivcvttsd2usivcvttsd2sivcvttps2uqqvcvttps2udqvcvttps2qqvcvttps2dqvcvttph2wvcvttph2uwvcvttph2uqqvcvttph2udqvcvttph2qqvcvttph2dqvcvttpd2uqqvcvttpd2udqvcvttpd2qqvcvttpd2dqvcvtss2usivcvtss2sivcvtss2shvcvtss2sdvcvtsi2ssvcvtsi2shvcvtsi2sdvcvtsh2usivcvtsh2ssvcvtsh2sivcvtsh2sdvcvtsd2usivcvtsd2ssvcvtsd2sivcvtsd2shvcvtqq2psvcvtqq2phvcvtqq2pdvcvtps2uqqvcvtps2udqvcvtps2qqvcvtps2phxvcvtps2pdvcvtps2dqvcvtph2wvcvtph2uwvcvtph2uqqvcvtph2udqvcvtph2qqvcvtph2psxvcvtph2pdvcvtph2dqvcvtpd2uqqvcvtpd2udqvcvtpd2qqvcvtpd2psvcvtpd2phvcvtpd2dqvcvtneps2bf16vcvtneoph2psvcvtneobf162psvcvtneeph2psvcvtneebf162psvcvtne2ps2bf16vcvtdq2psvcvtdq2phvcvtdq2pdvcompresspsvcompresspdvcomissvcomishvcomisdvcmpssvcmpshvcmpsdvcmppsvcmpphvcmppdvbroadcastssvbroadcastsdvbroadcasti64x4vbroadcasti64x2vbroadcasti32x8vbroadcasti32x4vbroadcasti32x2vbroadcasti128vbroadcastf64x4vbroadcastf64x2vbroadcastf32x8vbroadcastf32x4vbroadcastf32x2vbroadcastf128vblendvpsvblendvpdvblendpsvblendpdvblendmpsvblendmpdvbcstnesh2psvandpsvandpdvandnpsvandnpdvalignqvaligndvaeskeygenassistvaesimcmovcmovgevaesenclastvaesdeclastvaddsubpsvaddsubpdvaddssvaddshrsmovntirmpupdatermpreadrep xstorep xcryptofbrep xsha256rep xsha1pvalidatemovntssmovntsdmovntqloopzloopnzlodskxorwkxorqkxordkxorbkxnorwkxnorqkxnordkxnorbkunpckwdkunpckdqkunpckbwktestwktestqktestdktestbkshiftrwkshiftrqkshiftrdkshiftrbkshiftlwkshiftlqkshiftldkshiftlbkorwkortestwkortestqkortestdkortestbkorqkordkorbknotwknotqknotdknotbkmovwkmovbkandwkandqkandnwkandnqkandndkandnbkanddkandbkaddwkaddqjzjsjpjojnzjnsjnpjnojncmovlejmp farjlejgejcxz jecxzjrcxzjbejaesdecwide128klfyl2xp1fxtractfxsavefxrstorfxchfxamfucomppfucomipftstfsubrpfsubpfstswfstpfstenvfstcwd cdq cqofsqrtfsincosfscalefrstorfrndintfptanfprem1fpatanfnopfmulpfldzfldpifldln2fldlg2fldl2tfldl2efldenvfldcwfld1fisubrfisttpfistpfinitfincstpfimulfildfidivrficompfiaddfemmsfdivrpfdivpfcosfcomppfcomipfcmovufcmovnufcmovnefcmovnbefcmovefcmovbefclexcvttps2picvttpd2picvtps2picvtpi2pscvtpi2pdcvtpd2picmpzxaddcmpxchgcmpsxaddcmppxaddcmpoxaddcmpnzxaddcmpnsxaddcmpnpxaddcmpnoxaddcmpnlxaddcmpnlexaddcmpnbxaddcmpnbexaddcmplxaddcmplexaddcmpbxaddcmovzcmovscmovpcmovocmovnzcmovnscmovnpcmovnocmovncaxoraoraesencwide256klaesencwide128klaesenc256klaesenc128klaesdecwide256kl" +#elif defined(FD_DECODE_TABLE_STRTAB2) +529,177,178,178,182,459,1777,1917,1917,24,2749,4189,4189,4329,7548,8045,8688,7537,8677,8666,7537,8651,8636,7521,7505,460,3786,8633,41,8629,27,85,279,357,1669,49,1705,1763,1793,1793,1816,1985,2036,35,35,32,300,302,302,498,498,523,601,1544,1795,166,2050,3823,4433,4435,8380,7526,7530,7530,8007,8007,8623,8617,8611,8605,8599,8594,8589,8584,8579,3421,3596,8571,8562,8554,8544,8535,8525,8516,8507,8498,8489,8480,8472,8464,7163,8456,8449,8449,8441,2282,63,153,8142,181,275,159,552,55,164,216,309,441,414,481,566,566,1086,632,663,73,220,394,4438,7582,7576,7547,7547,7536,7536,7497,7490,7483,7476,7470,7464,7443,7434,7371,7356,7341,7326,7311,7282,7267,7252,7237,7222,7210,7198,7192,7186,7180,7174,7168,7162,7155,7148,7141,7130,7119,7110,7101,7092,7078,7013,7004,6995,6986,6977,6967,6957,6948,6939,6929,6929,6920,6910,6900,6891,6883,6874,6865,6855,6855,6846,6836,6826,6817,6808,6799,6790,6781,6772,6762,6753,6744,6735,6725,6716,6707,6698,6689,6680,6671,6661,6651,6641,6630,6619,6609,6599,6588,6577,6567,6558,6548,6538,6527,6516,6506,6495,6485,6474,6464,6447,6437,6427,6417,6407,6397,6387,6377,6367,6357,6348,6340,537,551,1849,1897,1946,2083,2132,2208,4042,6331,6306,6293,6280,6267,6242,6229,6216,6203,6193,6183,6173,6164,6155,6144,6133,6122,6111,6100,6089,6078,6067,6056,6045,6034,6023,6012,6001,5990,5979,5968,5957,5946,5935,5924,5913,5904,5895,5881,5867,5853,5839,5825,5811,5797,5783,5769,5758,5747,5736,5725,5714,5703,5692,5681,5670,5659,5648,5637,5626,5615,5604,5593,5582,5571,5557,5543,5529,5515,5501,5487,5473,5459,5445,5437,5429,5417,5405,5393,5381,5369,5357,5345,5333,5321,5309,5297,5285,5273,5261,5249,5237,5225,5213,5201,5189,5177,5165,5153,5141,5129,5117,5105,5093,5081,5069,5057,5045,5033,5021,5009,4997,4987,4977,4967,4957,4947,4937,4927,4917,4907,4897,4888,4879,4870,4861,4852,4843,4833,4823,4813,4803,4793,4783,4766,4752,4742,4691,4679,4667,4655,4632,4620,4608,4596,4587,4512,4506,4500,4494,4488,4482,4415,4409,4403,4397,4391,4385,4349,4342,4318,4309,4300,4291,4282,4273,4265,4257,4250,4243,4235,4228,4221,4181,4181,4173,4165,4160,4154,4135,4135,4117,4111,4104,4097,4092,4092,4092,4092,4032,4026,4020,4014,4008,4002,3974,3969,3956,3943,3937,3931,3925,3919,3910,3901,3892,3883,3877,3871,3865,3858,3851,3843,3835,3829,3804,3798,3791,3784,3778,3772,3766,3749,3740,3731,3722,3615,3681,3669,3654,3639,3627,3615,3605,3594,3588,3580,3572,3564,3556,3516,3508,3500,3492,3453,3446,3439,3432,3425,3419,3408,3397,3386,3375,3364,3353,3335,3335,3317,3317,3291,3285,3277,3269,3260,3251,3243,3235,3226,3217,3210,3203,3197,3189,3181,3172,3163,3155,3147,3141,3132,3123,3114,3105,3077,3098,3077,3067,3057,3047,3037,2961,2953,2945,2934,2923,2913,2905,2872,2865,2858,2851,2844,2837,2830,2823,2816,2809,2802,2795,2788,2781,2774,2767,2753,2730,2723,2716,2708,2700,2692,2684,2659,2652,2645,2638,2630,2622,2614,2606,2598,2590,2581,2572,2563,2554,2545,2536,2527,2518,2509,2500,2491,2482,2469,2462,2453,2444,2435,2426,2417,2408,2401,2392,2369,2362,2355,2348,2341,2327,2319,2311,2303,2295,2287,2275,2270,2264,2258,2248,2241,2223,2217,2203,2196,1900,2185,2174,2163,2152,2145,2138,2126,2118,2110,2103,2096,2089,2077,2069,2061,2054,2025,2025,2004,1996,1988,1958,1958,1952,1941,1934,1927,1921,1913,1907,1892,1885,1878,1872,1865,1865,1859,1844,1837,1830,1824,1811,1805,1799,1787,1780,1756,1748,1742,1732,1722,1698,1690,1682,1674,1661,1652,1643,1634,1624,1614,1603,1593,1583,1573,1562,1552,1536,1530,1522,1514,1506,1498,1490,1482,1474,1466,1460,1448,1433,1424,1415,1406,1397,1388,1377,1366,1355,1344,1333,1322,1280,1270,1260,1250,1242,1226,1209,1200,1191,1182,1173,1150,1139,1113,1102,1073,1063,1053,1043,1033,1026,1001,977,970,960,953,944,927,909,888,873,867,853,839,809,795,760,751,717,708,696,690,676,10,47,138,138,272,4461,4469,8386,8379,8379,8373,8365,8365,8358,8351,8345,8333,8339,8339,8333,8333,8329,2009,8318,8324,8318,8318,8313,3990,8308,8302,8302,8296,8296,8292,8287,8280,8275,8264,8270,8264,8258,8258,8210,8254,8249,8243,8237,8231,8225,8219,8214,8210,5430,8205,8201,8195,8189,8189,8184,8177,8171,744,8165,8158,8158,8153,8124,8139,8133,8129,8124,8113,8119,8113,8113,8109,8095,8102,8102,8095,8095,104,8091,8087,8080,8074,8067,8060,8060,148,4767,4753,4743,225,893,8297,8288,169,169,169,406,425,425,526,591,535,2039,2743,2743,3485,3549,6457,6,8044,8041,8026,8026,8023,8023,8020,8020,8013,8013,8005,8002,7999,7996,7993,7991,7989,7987,7985,23,348,7980,7975,7970,7965,7959,7953,7947,7941,7936,7931,7926,2897,2884,7921,7916,7911,7906,7901,7897,7893,7889,7881,7873,7865,7857,7853,7845,7837,7829,7821,7813,7805,7797,7789,7783,7777,7771,7765,7757,7749,7741,7735,7729,7723,7717,7712,7707,7702,7697,44,60,4550,241,195,575,575,1131,658,743,4199,4339,602,4362,194,4478,4368,7693,7682,7687,7682,58,4005,226,2947,184,2476,8433,8425,8417,8409,8400,8391,8314,2881,2666,2760,7676,2640,2885,3938,3932,3920,3911,3902,3884,3878,3872,3866,3859,3852,3844,3836,3830,3805,3109,3785,3773,3767,3581,3573,3557,3517,3509,3493,3078,1853,3030,3023,3005,2997,2990,2962,2914,2906,2852,2845,2796,2789,2676,2393,2370,2363,2342,2320,2271,540,2026,100,1980,1973,1966,1959,1953,1922,1914,1873,1866,1860,1825,1812,1806,1800,1788,1781,1757,1749,1743,1625,1615,1594,1584,1574,1553,1531,668,668,2410,2410,8381,2666,2737,7590,2538,2538,2410,2410,2410,2410,2410,2321,2388,1096,1096,3983,8202,7902,249,594,594,728,80,142,77,3078,174,174,2288,269,329,329,640,1767,2015,2231,4125,4143,4143,118,210,4325,4325,4465,7653,31,62,228,360,581,581,922,1090,1540,1707,1716,1818,2227,2278,2278,2380,3811,4450,4556,4568,7620,7644,7633,7612,8202,329,7,7,3467,3532,7605,7596,2243,1169,1169,7588,322,135,243,243,259,277,372,234,366,375,399,433,456,477,520,562,562,572,572,597,619,636,681,685,704,725,731,731,767,50,781,122,801,823,844,857,878,933,949,2105,949,966,2056,966,87,283,18,1007,74,395,4439,7577,7568,7559,7484,7477,4046,6335,7427,7419,7410,7401,7193,7181,7175,7163,811,762,7111,7093,7005,6987,6875,6866,6782,6773,6717,6699,6690,6672,6652,6549,6507,6465,552,1898,1947,2133,2254,2901,6194,3086,4736,4729,4722,4715,4588,406,4582,4539,4513,4501,2867,4483,4416,4404,2811,4386,4350,4343,2666,4319,4301,4266,4258,4251,4244,4236,4229,4222,4213,4204,4182,4182,4174,4166,7669,7662,2640,2624,4136,4118,4112,4105,4098,4085,4033,4021,4015,4003,692,678,3938,3932,3920,3911,3902,3893,3884,3878,3872,3866,3859,3852,3844,3836,3830,3805,3109,3785,3773,3767,3702,3694,3606,3581,3573,3565,3557,3541,3525,3517,3509,3501,3493,3477,3460,3099,3092,3085,3078,1853,3030,3023,3012,3005,2997,2990,2983,2976,2969,2962,2914,2906,2873,2866,2852,2845,2838,2824,2817,2810,2796,2789,2782,2768,2676,2582,2573,2564,2555,2546,2537,2454,2445,2436,2427,2418,2409,2402,2393,2370,2363,2356,2342,2320,2271,540,2026,2005,1997,1989,1980,1973,1966,1959,1959,1953,1922,1914,1873,1866,1866,1860,1825,1812,1806,1800,1788,1781,1757,1749,1743,1635,1625,1615,1604,1594,1584,1574,1563,1553,1531,1455,1443,1315,1307,1299,1291,1235,1219,1027,1002,978,961,954,928,910,874,868,840,810,761,752,718,709,697,691,677,495,8140,3678,588,7230,916,1014,3465,1017,3,840,1009,737,1083,1123,1158,90,108,190,251,288,381,507,605,773,1,1,784,784,898,1129,1163,2044,727,769,386,468,610,5,667,1095,1711,2375,73,394,4438,7576,7567,7558,7547,7547,7536,7536,7520,7504,7483,7476,7470,7464,3708,7452,7426,7418,7409,7400,7386,7297,7210,7198,7192,7180,7174,7162,7155,7141,7110,7092,7064,7052,7038,7026,7013,7004,6986,6929,6874,6865,6855,6781,6772,6716,6698,6689,6671,6651,6548,6506,6464,551,1897,1946,2132,2253,2900,578,747,6319,6255,6193,6100,6078,6067,6045,6034,6012,6001,5979,5968,5946,5935,5913,5881,5853,5839,5811,5797,5769,5758,5736,5725,5703,5692,5670,5659,5637,5626,5604,5593,5571,5557,5529,5515,5487,5473,5445,5417,5393,5381,5357,5345,5321,5309,5285,5273,5249,5237,5213,5201,5177,5165,5141,5129,5105,5093,5069,5057,5033,5021,4997,4927,4917,4907,4897,4766,4752,4742,4735,4728,4721,4714,4703,4644,4587,4581,4549,4538,4528,4518,4512,4500,4494,4482,4473,4444,4428,4421,4415,4403,4397,4385,4377,4366,4356,4349,4342,4265,4318,4300,4265,4257,4250,4243,4235,4228,4221,4212,4203,4181,4181,4173,4165,4160,4154,4135,4117,4111,4104,4097,4084,4077,4070,4064,4056,4051,4038,4032,4020,4014,4002,3995,3986,3979,3974,3969,3937,3931,3919,3910,3901,3892,3883,3877,3871,3865,3858,3851,3843,3835,3829,3804,3778,3784,3772,3766,3758,3701,3693,3681,3669,3627,3615,3605,3580,3572,3564,3556,3540,3524,3516,3508,3500,3492,3476,3459,554,554,3344,3344,3335,3335,3326,3326,3317,3317,3307,3297,3285,3226,3217,3210,3203,3197,3098,3091,3084,3077,3067,3057,3047,3037,1852,3029,3022,3011,3004,2996,2989,2982,2975,2968,2961,2934,2923,2913,2905,2892,2879,2872,2865,2851,2844,2837,2823,2816,2809,2795,2788,2781,2767,2675,2581,2572,2563,2554,2545,2536,2453,2444,2435,2426,2417,2408,2401,2392,2369,2362,2355,2341,2319,2270,1900,2025,2004,1996,1988,1979,1972,1965,1958,1958,1952,1941,1934,1921,1913,1892,1872,1865,1865,1859,1844,1837,1824,1811,1805,1799,1787,1780,1756,1748,1742,1634,1624,1614,1603,1593,1583,1573,1562,1552,1530,1454,1442,1314,1306,1298,1290,1234,1218,1026,1001,993,984,977,960,953,927,915,909,873,867,839,832,817,809,760,751,717,708,696,690,676,651,624,533,545,613,514,471,488,471,463,453,429,246,3601,421,8452,0,413,389,353,677,340,321,321,130,295,204,130,68,7616,15,0 +#elif defined(FD_DECODE_TABLE_STRTAB3) +5,3,3,4,3,4,3,3,4,3,4,6,11,11,10,15,15,6,11,11,10,15,15,6,15,3,4,3,4,4,5,4,6,4,5,3,3,5,2,3,3,3,4,4,8,4,3,3,8,7,10,4,3,8,4,4,4,6,3,5,6,5,5,6,5,6,6,6,6,6,6,5,5,5,5,3,9,8,9,8,10,9,10,9,9,9,9,9,8,8,4,8,7,7,8,5,5,12,11,3,3,3,3,5,5,5,12,12,7,7,6,7,5,5,5,6,6,6,6,6,6,7,11,7,11,7,7,7,7,6,6,9,9,15,15,15,15,15,15,15,15,15,15,12,12,6,6,6,6,6,6,7,7,7,11,11,9,9,9,14,13,9,9,9,9,10,10,9,9,9,10,9,10,10,9,8,9,9,9,10,9,10,10,9,9,9,9,9,9,10,9,9,9,10,9,9,9,9,9,9,10,10,10,11,11,10,10,11,11,10,9,10,10,11,11,10,11,10,11,10,11,10,10,10,10,10,10,10,10,10,9,8,9,6,6,6,6,6,6,9,9,9,13,13,13,13,13,13,13,13,10,10,10,9,9,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,9,9,14,14,14,14,14,14,14,14,14,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,14,14,14,14,14,14,14,14,14,8,8,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,9,9,9,9,9,9,10,10,10,10,10,10,17,14,10,12,12,12,12,12,12,12,12,9,6,6,6,6,6,6,6,6,6,6,6,6,7,7,8,9,9,9,9,9,8,8,7,7,8,7,7,8,9,8,8,5,6,6,9,9,6,7,7,5,5,4,4,6,6,6,6,6,6,5,5,13,13,6,6,6,6,9,9,9,9,6,6,6,7,7,8,8,6,8,6,7,7,6,6,6,9,9,9,9,11,12,12,15,15,12,12,10,6,6,8,8,8,8,8,8,8,8,6,7,7,7,7,6,11,11,11,11,11,11,8,9,8,9,6,6,8,8,9,9,8,8,9,9,7,7,6,8,8,9,9,8,8,6,9,9,9,9,6,7,7,10,10,10,10,6,8,8,11,11,10,8,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,8,8,7,7,8,8,8,8,8,7,7,7,8,8,8,8,8,8,9,9,9,9,9,9,9,9,9,9,9,9,8,7,9,9,9,9,9,9,7,9,8,7,7,7,7,14,8,8,8,8,8,5,5,6,6,7,7,6,6,7,7,7,11,11,11,11,7,7,8,8,8,7,7,7,8,8,8,7,7,12,7,8,8,6,7,6,7,7,7,6,6,6,7,7,7,6,6,7,6,7,7,7,6,6,6,6,7,7,8,8,6,10,10,8,8,8,8,9,9,9,9,10,10,11,10,10,10,11,10,6,6,8,8,8,8,8,8,8,8,6,6,9,9,9,9,9,9,11,11,11,11,11,11,10,10,10,10,8,8,9,9,9,9,9,9,11,11,11,11,10,10,10,10,7,7,7,7,7,7,7,7,6,6,6,6,6,6,8,8,8,9,9,9,9,6,6,5,4,4,5,4,5,4,5,6,7,6,7,8,7,7,6,4,5,6,5,6,4,7,4,5,5,6,5,5,5,5,6,5,6,4,5,7,5,4,5,6,5,6,3,4,5,6,6,6,6,6,5,4,4,5,4,6,5,6,5,7,6,5,6,4,7,5,3,5,6,4,5,4,5,5,6,4,5,6,7,6,7,5,4,4,7,6,7,5,7,6,16,13,9,3,6,4,4,2,3,6,3,3,4,4,4,4,6,6,7,7,7,7,4,2,3,2,15,2,3,2,3,3,7,3,3,3,3,3,2,2,2,2,5,5,5,5,5,5,6,6,6,6,5,5,5,5,5,5,5,5,5,5,4,4,4,8,8,8,8,4,8,8,8,8,8,8,8,8,6,6,6,6,8,8,8,6,6,6,6,5,5,5,5,4,3,7,3,9,3,5,3,6,3,4,3,4,4,4,4,9,4,4,6,5,3,3,3,5,7,6,8,8,8,8,9,9,4,8,4,7,6,4,7,5,5,5,8,8,8,5,5,5,6,6,7,7,5,7,4,5,5,5,7,7,7,7,7,7,6,6,7,6,6,7,6,6,9,7,6,6,6,6,8,8,7,6,6,7,3,6,6,6,6,6,6,5,5,5,5,5,5,5,5,5,5,5,6,6,7,7,5,9,9,9,9,9,9,4,7,8,3,3,5,9,7,6,4,5,5,3,3,3,3,3,4,5,6,3,3,3,2,3,4,5,6,7,4,4,3,4,6,4,8,11,11,11,10,10,10,9,11,6,7,4,5,5,9,3,3,8,8,5,9,5,6,5,5,6,6,5,5,6,11,13,13,13,13,13,9,11,10,3,8,3,4,9,8,7,9,3,3,4,3,8,4,3,4,11,3,4,8,7,7,8,9,4,5,4,4,5,4,5,5,5,5,5,5,4,4,4,8,4,6,4,8,8,9,9,10,10,11,3,4,4,3,4,4,4,6,4,4,5,5,5,5,8,8,6,6,5,5,7,7,8,8,5,5,5,5,6,6,8,8,8,8,8,8,8,8,8,8,8,8,9,9,9,9,5,5,5,5,4,4,9,5,6,6,6,6,8,7,5,10,5,5,5,5,5,5,5,5,6,6,4,7,6,6,7,6,6,7,6,6,8,8,7,8,7,7,7,7,4,5,8,8,5,6,6,7,5,5,5,5,4,4,5,5,5,8,8,8,8,5,5,5,6,6,7,7,5,7,4,5,5,5,8,7,9,7,7,7,7,9,9,7,7,7,7,9,9,6,6,6,6,6,7,6,10,6,7,6,6,6,6,6,9,7,6,6,6,6,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,8,8,8,8,8,6,8,7,6,6,6,7,3,6,6,6,7,7,6,6,6,5,6,5,5,5,5,5,6,5,5,5,5,5,6,6,7,7,5,5,9,9,10,9,9,9,10,9,4,5,5,7,7,7,7,7,7,6,6,6,6,6,6,5,5,5,5,7,7,8,8,8,8,5,5,4,3,3,4,3,7,4,3,9,4,3,6,7,8,7,6,12,12,6,9,7,7,7,7,9,4,6,9,11,11,10,8,7,6,5,3,3,3,5,8,6,6,6,6,6,6,6,9,9,7,11,7,11,7,16,7,7,6,6,14,12,8,8,9,9,14,14,12,12,6,6,6,6,7,7,9,9,14,12,14,12,13,9,9,9,9,9,9,9,9,9,9,9,9,10,10,10,10,6,6,6,6,5,5,4,4,12,12,10,11,11,11,11,11,11,11,11,11,11,11,11,14,14,14,14,14,14,11,11,11,11,11,11,11,11,11,11,11,11,14,14,14,14,14,14,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,17,14,10,7,7,7,7,11,11,9,6,8,11,10,10,6,6,6,6,6,7,6,7,6,6,6,6,8,6,7,7,7,5,8,7,7,8,7,7,8,7,7,9,9,8,9,8,8,5,6,9,9,6,7,7,8,7,7,6,8,5,6,6,6,6,6,7,6,5,5,5,6,6,6,9,9,9,9,6,6,6,7,7,8,8,6,8,5,6,6,6,8,9,8,12,12,12,12,10,8,8,8,8,10,10,8,8,8,8,10,10,8,9,8,9,8,9,8,9,8,9,10,10,6,9,9,7,7,6,7,7,7,7,10,10,10,10,7,8,7,11,7,8,7,7,7,7,7,11,11,10,8,10,10,7,7,7,7,7,7,7,7,7,7,7,7,9,9,9,9,9,9,9,9,9,9,9,9,9,7,9,8,7,7,7,8,4,7,7,7,8,8,7,7,7,6,7,6,7,7,6,6,7,6,6,7,6,7,7,6,6,6,6,7,7,8,8,6,6,10,10,11,10,10,10,11,10,5,6,6,8,8,8,8,8,8,7,7,8,9,7,7,7,7,8,6,6,6,6,7,7,8,8,9,9,9,9,6,6,8,10,6,8,8,8,5,9,7,6,4,5,6,4,6,4,0,4,6,5,3,9,6,7,5,6,8,6,6,6,9,5 +#elif defined(FD_DECODE_TABLE_DEFINES) +#define FD_TABLE_OFFSET_32 0 +#define FD_TABLE_OFFSET_64 256 + +#else +#error "unspecified decode table" +#endif diff --git a/third_party/fadec/fadec-decode-public.inc b/third_party/fadec/fadec-decode-public.inc new file mode 100644 index 0000000..7b994ff --- /dev/null +++ b/third_party/fadec/fadec-decode-public.inc @@ -0,0 +1,1888 @@ +FD_MNEMONIC(3DNOW,0) +FD_MNEMONIC(AAA,1) +FD_MNEMONIC(AAD,2) +FD_MNEMONIC(AADD,3) +FD_MNEMONIC(AAM,4) +FD_MNEMONIC(AAND,5) +FD_MNEMONIC(AAS,6) +FD_MNEMONIC(ADC,7) +FD_MNEMONIC(ADCX,8) +FD_MNEMONIC(ADD,9) +FD_MNEMONIC(ADOX,10) +FD_MNEMONIC(AESDEC,11) +FD_MNEMONIC(AESDEC128KL,12) +FD_MNEMONIC(AESDEC256KL,13) +FD_MNEMONIC(AESDECLAST,14) +FD_MNEMONIC(AESDECWIDE128KL,15) +FD_MNEMONIC(AESDECWIDE256KL,16) +FD_MNEMONIC(AESENC,17) +FD_MNEMONIC(AESENC128KL,18) +FD_MNEMONIC(AESENC256KL,19) +FD_MNEMONIC(AESENCLAST,20) +FD_MNEMONIC(AESENCWIDE128KL,21) +FD_MNEMONIC(AESENCWIDE256KL,22) +FD_MNEMONIC(AESIMC,23) +FD_MNEMONIC(AESKEYGENASSIST,24) +FD_MNEMONIC(AND,25) +FD_MNEMONIC(ANDN,26) +FD_MNEMONIC(AOR,27) +FD_MNEMONIC(ARPL,28) +FD_MNEMONIC(AXOR,29) +FD_MNEMONIC(BEXTR,30) +FD_MNEMONIC(BLSI,31) +FD_MNEMONIC(BLSMSK,32) +FD_MNEMONIC(BLSR,33) +FD_MNEMONIC(BOUND,34) +FD_MNEMONIC(BSF,35) +FD_MNEMONIC(BSR,36) +FD_MNEMONIC(BSWAP,37) +FD_MNEMONIC(BT,38) +FD_MNEMONIC(BTC,39) +FD_MNEMONIC(BTR,40) +FD_MNEMONIC(BTS,41) +FD_MNEMONIC(BZHI,42) +FD_MNEMONIC(CALL,43) +FD_MNEMONIC(CALLF,44) +FD_MNEMONIC(CLAC,45) +FD_MNEMONIC(CLC,46) +FD_MNEMONIC(CLD,47) +FD_MNEMONIC(CLDEMOTE,48) +FD_MNEMONIC(CLFLUSH,49) +FD_MNEMONIC(CLFLUSHOPT,50) +FD_MNEMONIC(CLGI,51) +FD_MNEMONIC(CLI,52) +FD_MNEMONIC(CLRSSBSY,53) +FD_MNEMONIC(CLTS,54) +FD_MNEMONIC(CLUI,55) +FD_MNEMONIC(CLWB,56) +FD_MNEMONIC(CLZERO,57) +FD_MNEMONIC(CMC,58) +FD_MNEMONIC(CMOVA,59) +FD_MNEMONIC(CMOVBE,60) +FD_MNEMONIC(CMOVC,61) +FD_MNEMONIC(CMOVG,62) +FD_MNEMONIC(CMOVGE,63) +FD_MNEMONIC(CMOVL,64) +FD_MNEMONIC(CMOVLE,65) +FD_MNEMONIC(CMOVNC,66) +FD_MNEMONIC(CMOVNO,67) +FD_MNEMONIC(CMOVNP,68) +FD_MNEMONIC(CMOVNS,69) +FD_MNEMONIC(CMOVNZ,70) +FD_MNEMONIC(CMOVO,71) +FD_MNEMONIC(CMOVP,72) +FD_MNEMONIC(CMOVS,73) +FD_MNEMONIC(CMOVZ,74) +FD_MNEMONIC(CMP,75) +FD_MNEMONIC(CMPBEXADD,76) +FD_MNEMONIC(CMPBXADD,77) +FD_MNEMONIC(CMPLEXADD,78) +FD_MNEMONIC(CMPLXADD,79) +FD_MNEMONIC(CMPNBEXADD,80) +FD_MNEMONIC(CMPNBXADD,81) +FD_MNEMONIC(CMPNLEXADD,82) +FD_MNEMONIC(CMPNLXADD,83) +FD_MNEMONIC(CMPNOXADD,84) +FD_MNEMONIC(CMPNPXADD,85) +FD_MNEMONIC(CMPNSXADD,86) +FD_MNEMONIC(CMPNZXADD,87) +FD_MNEMONIC(CMPOXADD,88) +FD_MNEMONIC(CMPPXADD,89) +FD_MNEMONIC(CMPS,90) +FD_MNEMONIC(CMPSXADD,91) +FD_MNEMONIC(CMPXCHG,92) +FD_MNEMONIC(CMPXCHGD,93) +FD_MNEMONIC(CMPZXADD,94) +FD_MNEMONIC(CPUID,95) +FD_MNEMONIC(CRC32,96) +FD_MNEMONIC(C_EX,97) +FD_MNEMONIC(C_SEP,98) +FD_MNEMONIC(DAA,99) +FD_MNEMONIC(DAS,100) +FD_MNEMONIC(DEC,101) +FD_MNEMONIC(DIV,102) +FD_MNEMONIC(ENCLS,103) +FD_MNEMONIC(ENCLU,104) +FD_MNEMONIC(ENCLV,105) +FD_MNEMONIC(ENCODEKEY128,106) +FD_MNEMONIC(ENCODEKEY256,107) +FD_MNEMONIC(ENDBR32,108) +FD_MNEMONIC(ENDBR64,109) +FD_MNEMONIC(ENQCMD,110) +FD_MNEMONIC(ENQCMDS,111) +FD_MNEMONIC(ENTER,112) +FD_MNEMONIC(ERETS,113) +FD_MNEMONIC(ERETU,114) +FD_MNEMONIC(EVX_ADDPD,115) +FD_MNEMONIC(EVX_ADDPH,116) +FD_MNEMONIC(EVX_ADDPS,117) +FD_MNEMONIC(EVX_ADDSD,118) +FD_MNEMONIC(EVX_ADDSH,119) +FD_MNEMONIC(EVX_ADDSS,120) +FD_MNEMONIC(EVX_AESDEC,121) +FD_MNEMONIC(EVX_AESDECLAST,122) +FD_MNEMONIC(EVX_AESENC,123) +FD_MNEMONIC(EVX_AESENCLAST,124) +FD_MNEMONIC(EVX_ALIGND,125) +FD_MNEMONIC(EVX_ALIGNQ,126) +FD_MNEMONIC(EVX_ANDNPD,127) +FD_MNEMONIC(EVX_ANDNPS,128) +FD_MNEMONIC(EVX_ANDPD,129) +FD_MNEMONIC(EVX_ANDPS,130) +FD_MNEMONIC(EVX_BLENDMPD,131) +FD_MNEMONIC(EVX_BLENDMPS,132) +FD_MNEMONIC(EVX_BROADCASTF32X2,133) +FD_MNEMONIC(EVX_BROADCASTF32X4,134) +FD_MNEMONIC(EVX_BROADCASTF32X8,135) +FD_MNEMONIC(EVX_BROADCASTF64X2,136) +FD_MNEMONIC(EVX_BROADCASTF64X4,137) +FD_MNEMONIC(EVX_BROADCASTI32X2,138) +FD_MNEMONIC(EVX_BROADCASTI32X4,139) +FD_MNEMONIC(EVX_BROADCASTI32X8,140) +FD_MNEMONIC(EVX_BROADCASTI64X2,141) +FD_MNEMONIC(EVX_BROADCASTI64X4,142) +FD_MNEMONIC(EVX_BROADCASTSD,143) +FD_MNEMONIC(EVX_BROADCASTSS,144) +FD_MNEMONIC(EVX_CMPPD,145) +FD_MNEMONIC(EVX_CMPPH,146) +FD_MNEMONIC(EVX_CMPPS,147) +FD_MNEMONIC(EVX_CMPSD,148) +FD_MNEMONIC(EVX_CMPSH,149) +FD_MNEMONIC(EVX_CMPSS,150) +FD_MNEMONIC(EVX_COMISD,151) +FD_MNEMONIC(EVX_COMISH,152) +FD_MNEMONIC(EVX_COMISS,153) +FD_MNEMONIC(EVX_COMPRESSPD,154) +FD_MNEMONIC(EVX_COMPRESSPS,155) +FD_MNEMONIC(EVX_CVTDQ2PD,156) +FD_MNEMONIC(EVX_CVTDQ2PH,157) +FD_MNEMONIC(EVX_CVTDQ2PS,158) +FD_MNEMONIC(EVX_CVTNE2PS2BF16,159) +FD_MNEMONIC(EVX_CVTNEPS2BF16,160) +FD_MNEMONIC(EVX_CVTPD2DQ,161) +FD_MNEMONIC(EVX_CVTPD2PH,162) +FD_MNEMONIC(EVX_CVTPD2PS,163) +FD_MNEMONIC(EVX_CVTPD2QQ,164) +FD_MNEMONIC(EVX_CVTPD2UDQ,165) +FD_MNEMONIC(EVX_CVTPD2UQQ,166) +FD_MNEMONIC(EVX_CVTPH2DQ,167) +FD_MNEMONIC(EVX_CVTPH2PD,168) +FD_MNEMONIC(EVX_CVTPH2PS,169) +FD_MNEMONIC(EVX_CVTPH2PSX,170) +FD_MNEMONIC(EVX_CVTPH2QQ,171) +FD_MNEMONIC(EVX_CVTPH2UDQ,172) +FD_MNEMONIC(EVX_CVTPH2UQQ,173) +FD_MNEMONIC(EVX_CVTPH2UW,174) +FD_MNEMONIC(EVX_CVTPH2W,175) +FD_MNEMONIC(EVX_CVTPS2DQ,176) +FD_MNEMONIC(EVX_CVTPS2PD,177) +FD_MNEMONIC(EVX_CVTPS2PH,178) +FD_MNEMONIC(EVX_CVTPS2PHX,179) +FD_MNEMONIC(EVX_CVTPS2QQ,180) +FD_MNEMONIC(EVX_CVTPS2UDQ,181) +FD_MNEMONIC(EVX_CVTPS2UQQ,182) +FD_MNEMONIC(EVX_CVTQQ2PD,183) +FD_MNEMONIC(EVX_CVTQQ2PH,184) +FD_MNEMONIC(EVX_CVTQQ2PS,185) +FD_MNEMONIC(EVX_CVTSD2SH,186) +FD_MNEMONIC(EVX_CVTSD2SI,187) +FD_MNEMONIC(EVX_CVTSD2SS,188) +FD_MNEMONIC(EVX_CVTSD2USI,189) +FD_MNEMONIC(EVX_CVTSH2SD,190) +FD_MNEMONIC(EVX_CVTSH2SI,191) +FD_MNEMONIC(EVX_CVTSH2SS,192) +FD_MNEMONIC(EVX_CVTSH2USI,193) +FD_MNEMONIC(EVX_CVTSI2SD,194) +FD_MNEMONIC(EVX_CVTSI2SH,195) +FD_MNEMONIC(EVX_CVTSI2SS,196) +FD_MNEMONIC(EVX_CVTSS2SD,197) +FD_MNEMONIC(EVX_CVTSS2SH,198) +FD_MNEMONIC(EVX_CVTSS2SI,199) +FD_MNEMONIC(EVX_CVTSS2USI,200) +FD_MNEMONIC(EVX_CVTTPD2DQ,201) +FD_MNEMONIC(EVX_CVTTPD2QQ,202) +FD_MNEMONIC(EVX_CVTTPD2UDQ,203) +FD_MNEMONIC(EVX_CVTTPD2UQQ,204) +FD_MNEMONIC(EVX_CVTTPH2DQ,205) +FD_MNEMONIC(EVX_CVTTPH2QQ,206) +FD_MNEMONIC(EVX_CVTTPH2UDQ,207) +FD_MNEMONIC(EVX_CVTTPH2UQQ,208) +FD_MNEMONIC(EVX_CVTTPH2UW,209) +FD_MNEMONIC(EVX_CVTTPH2W,210) +FD_MNEMONIC(EVX_CVTTPS2DQ,211) +FD_MNEMONIC(EVX_CVTTPS2QQ,212) +FD_MNEMONIC(EVX_CVTTPS2UDQ,213) +FD_MNEMONIC(EVX_CVTTPS2UQQ,214) +FD_MNEMONIC(EVX_CVTTSD2SI,215) +FD_MNEMONIC(EVX_CVTTSD2USI,216) +FD_MNEMONIC(EVX_CVTTSH2SI,217) +FD_MNEMONIC(EVX_CVTTSH2USI,218) +FD_MNEMONIC(EVX_CVTTSS2SI,219) +FD_MNEMONIC(EVX_CVTTSS2USI,220) +FD_MNEMONIC(EVX_CVTUDQ2PD,221) +FD_MNEMONIC(EVX_CVTUDQ2PH,222) +FD_MNEMONIC(EVX_CVTUDQ2PS,223) +FD_MNEMONIC(EVX_CVTUQQ2PD,224) +FD_MNEMONIC(EVX_CVTUQQ2PH,225) +FD_MNEMONIC(EVX_CVTUQQ2PS,226) +FD_MNEMONIC(EVX_CVTUSI2SD,227) +FD_MNEMONIC(EVX_CVTUSI2SH,228) +FD_MNEMONIC(EVX_CVTUSI2SS,229) +FD_MNEMONIC(EVX_CVTUW2PH,230) +FD_MNEMONIC(EVX_CVTW2PH,231) +FD_MNEMONIC(EVX_DBPSADBW,232) +FD_MNEMONIC(EVX_DIVPD,233) +FD_MNEMONIC(EVX_DIVPH,234) +FD_MNEMONIC(EVX_DIVPS,235) +FD_MNEMONIC(EVX_DIVSD,236) +FD_MNEMONIC(EVX_DIVSH,237) +FD_MNEMONIC(EVX_DIVSS,238) +FD_MNEMONIC(EVX_DPBF16PS,239) +FD_MNEMONIC(EVX_EXPANDPD,240) +FD_MNEMONIC(EVX_EXPANDPS,241) +FD_MNEMONIC(EVX_EXTRACTF32X4,242) +FD_MNEMONIC(EVX_EXTRACTF32X8,243) +FD_MNEMONIC(EVX_EXTRACTF64X2,244) +FD_MNEMONIC(EVX_EXTRACTF64X4,245) +FD_MNEMONIC(EVX_EXTRACTI32X4,246) +FD_MNEMONIC(EVX_EXTRACTI32X8,247) +FD_MNEMONIC(EVX_EXTRACTI64X2,248) +FD_MNEMONIC(EVX_EXTRACTI64X4,249) +FD_MNEMONIC(EVX_EXTRACTPS,250) +FD_MNEMONIC(EVX_FCMADDCPH,251) +FD_MNEMONIC(EVX_FCMADDCSH,252) +FD_MNEMONIC(EVX_FCMULCPH,253) +FD_MNEMONIC(EVX_FCMULCSH,254) +FD_MNEMONIC(EVX_FIXUPIMMPD,255) +FD_MNEMONIC(EVX_FIXUPIMMPS,256) +FD_MNEMONIC(EVX_FIXUPIMMSD,257) +FD_MNEMONIC(EVX_FIXUPIMMSS,258) +FD_MNEMONIC(EVX_FMADD132PD,259) +FD_MNEMONIC(EVX_FMADD132PH,260) +FD_MNEMONIC(EVX_FMADD132PS,261) +FD_MNEMONIC(EVX_FMADD132SD,262) +FD_MNEMONIC(EVX_FMADD132SH,263) +FD_MNEMONIC(EVX_FMADD132SS,264) +FD_MNEMONIC(EVX_FMADD213PD,265) +FD_MNEMONIC(EVX_FMADD213PH,266) +FD_MNEMONIC(EVX_FMADD213PS,267) +FD_MNEMONIC(EVX_FMADD213SD,268) +FD_MNEMONIC(EVX_FMADD213SH,269) +FD_MNEMONIC(EVX_FMADD213SS,270) +FD_MNEMONIC(EVX_FMADD231PD,271) +FD_MNEMONIC(EVX_FMADD231PH,272) +FD_MNEMONIC(EVX_FMADD231PS,273) +FD_MNEMONIC(EVX_FMADD231SD,274) +FD_MNEMONIC(EVX_FMADD231SH,275) +FD_MNEMONIC(EVX_FMADD231SS,276) +FD_MNEMONIC(EVX_FMADDCPH,277) +FD_MNEMONIC(EVX_FMADDCSH,278) +FD_MNEMONIC(EVX_FMADDSUB132PD,279) +FD_MNEMONIC(EVX_FMADDSUB132PH,280) +FD_MNEMONIC(EVX_FMADDSUB132PS,281) +FD_MNEMONIC(EVX_FMADDSUB213PD,282) +FD_MNEMONIC(EVX_FMADDSUB213PH,283) +FD_MNEMONIC(EVX_FMADDSUB213PS,284) +FD_MNEMONIC(EVX_FMADDSUB231PD,285) +FD_MNEMONIC(EVX_FMADDSUB231PH,286) +FD_MNEMONIC(EVX_FMADDSUB231PS,287) +FD_MNEMONIC(EVX_FMSUB132PD,288) +FD_MNEMONIC(EVX_FMSUB132PH,289) +FD_MNEMONIC(EVX_FMSUB132PS,290) +FD_MNEMONIC(EVX_FMSUB132SD,291) +FD_MNEMONIC(EVX_FMSUB132SH,292) +FD_MNEMONIC(EVX_FMSUB132SS,293) +FD_MNEMONIC(EVX_FMSUB213PD,294) +FD_MNEMONIC(EVX_FMSUB213PH,295) +FD_MNEMONIC(EVX_FMSUB213PS,296) +FD_MNEMONIC(EVX_FMSUB213SD,297) +FD_MNEMONIC(EVX_FMSUB213SH,298) +FD_MNEMONIC(EVX_FMSUB213SS,299) +FD_MNEMONIC(EVX_FMSUB231PD,300) +FD_MNEMONIC(EVX_FMSUB231PH,301) +FD_MNEMONIC(EVX_FMSUB231PS,302) +FD_MNEMONIC(EVX_FMSUB231SD,303) +FD_MNEMONIC(EVX_FMSUB231SH,304) +FD_MNEMONIC(EVX_FMSUB231SS,305) +FD_MNEMONIC(EVX_FMSUBADD132PD,306) +FD_MNEMONIC(EVX_FMSUBADD132PH,307) +FD_MNEMONIC(EVX_FMSUBADD132PS,308) +FD_MNEMONIC(EVX_FMSUBADD213PD,309) +FD_MNEMONIC(EVX_FMSUBADD213PH,310) +FD_MNEMONIC(EVX_FMSUBADD213PS,311) +FD_MNEMONIC(EVX_FMSUBADD231PD,312) +FD_MNEMONIC(EVX_FMSUBADD231PH,313) +FD_MNEMONIC(EVX_FMSUBADD231PS,314) +FD_MNEMONIC(EVX_FMULCPH,315) +FD_MNEMONIC(EVX_FMULCSH,316) +FD_MNEMONIC(EVX_FNMADD132PD,317) +FD_MNEMONIC(EVX_FNMADD132PH,318) +FD_MNEMONIC(EVX_FNMADD132PS,319) +FD_MNEMONIC(EVX_FNMADD132SD,320) +FD_MNEMONIC(EVX_FNMADD132SH,321) +FD_MNEMONIC(EVX_FNMADD132SS,322) +FD_MNEMONIC(EVX_FNMADD213PD,323) +FD_MNEMONIC(EVX_FNMADD213PH,324) +FD_MNEMONIC(EVX_FNMADD213PS,325) +FD_MNEMONIC(EVX_FNMADD213SD,326) +FD_MNEMONIC(EVX_FNMADD213SH,327) +FD_MNEMONIC(EVX_FNMADD213SS,328) +FD_MNEMONIC(EVX_FNMADD231PD,329) +FD_MNEMONIC(EVX_FNMADD231PH,330) +FD_MNEMONIC(EVX_FNMADD231PS,331) +FD_MNEMONIC(EVX_FNMADD231SD,332) +FD_MNEMONIC(EVX_FNMADD231SH,333) +FD_MNEMONIC(EVX_FNMADD231SS,334) +FD_MNEMONIC(EVX_FNMSUB132PD,335) +FD_MNEMONIC(EVX_FNMSUB132PH,336) +FD_MNEMONIC(EVX_FNMSUB132PS,337) +FD_MNEMONIC(EVX_FNMSUB132SD,338) +FD_MNEMONIC(EVX_FNMSUB132SH,339) +FD_MNEMONIC(EVX_FNMSUB132SS,340) +FD_MNEMONIC(EVX_FNMSUB213PD,341) +FD_MNEMONIC(EVX_FNMSUB213PH,342) +FD_MNEMONIC(EVX_FNMSUB213PS,343) +FD_MNEMONIC(EVX_FNMSUB213SD,344) +FD_MNEMONIC(EVX_FNMSUB213SH,345) +FD_MNEMONIC(EVX_FNMSUB213SS,346) +FD_MNEMONIC(EVX_FNMSUB231PD,347) +FD_MNEMONIC(EVX_FNMSUB231PH,348) +FD_MNEMONIC(EVX_FNMSUB231PS,349) +FD_MNEMONIC(EVX_FNMSUB231SD,350) +FD_MNEMONIC(EVX_FNMSUB231SH,351) +FD_MNEMONIC(EVX_FNMSUB231SS,352) +FD_MNEMONIC(EVX_FPCLASSPD,353) +FD_MNEMONIC(EVX_FPCLASSPH,354) +FD_MNEMONIC(EVX_FPCLASSPS,355) +FD_MNEMONIC(EVX_FPCLASSSD,356) +FD_MNEMONIC(EVX_FPCLASSSH,357) +FD_MNEMONIC(EVX_FPCLASSSS,358) +FD_MNEMONIC(EVX_GATHERDPD,359) +FD_MNEMONIC(EVX_GATHERDPS,360) +FD_MNEMONIC(EVX_GATHERQPD,361) +FD_MNEMONIC(EVX_GATHERQPS,362) +FD_MNEMONIC(EVX_GETEXPPD,363) +FD_MNEMONIC(EVX_GETEXPPH,364) +FD_MNEMONIC(EVX_GETEXPPS,365) +FD_MNEMONIC(EVX_GETEXPSD,366) +FD_MNEMONIC(EVX_GETEXPSH,367) +FD_MNEMONIC(EVX_GETEXPSS,368) +FD_MNEMONIC(EVX_GETMANTPD,369) +FD_MNEMONIC(EVX_GETMANTPH,370) +FD_MNEMONIC(EVX_GETMANTPS,371) +FD_MNEMONIC(EVX_GETMANTSD,372) +FD_MNEMONIC(EVX_GETMANTSH,373) +FD_MNEMONIC(EVX_GETMANTSS,374) +FD_MNEMONIC(EVX_GF2P8AFFINEINVQB,375) +FD_MNEMONIC(EVX_GF2P8AFFINEQB,376) +FD_MNEMONIC(EVX_GF2P8MULB,377) +FD_MNEMONIC(EVX_INSERTF32X4,378) +FD_MNEMONIC(EVX_INSERTF32X8,379) +FD_MNEMONIC(EVX_INSERTF64X2,380) +FD_MNEMONIC(EVX_INSERTF64X4,381) +FD_MNEMONIC(EVX_INSERTI32X4,382) +FD_MNEMONIC(EVX_INSERTI32X8,383) +FD_MNEMONIC(EVX_INSERTI64X2,384) +FD_MNEMONIC(EVX_INSERTI64X4,385) +FD_MNEMONIC(EVX_INSERTPS,386) +FD_MNEMONIC(EVX_MAXPD,387) +FD_MNEMONIC(EVX_MAXPH,388) +FD_MNEMONIC(EVX_MAXPS,389) +FD_MNEMONIC(EVX_MAXSD,390) +FD_MNEMONIC(EVX_MAXSH,391) +FD_MNEMONIC(EVX_MAXSS,392) +FD_MNEMONIC(EVX_MINPD,393) +FD_MNEMONIC(EVX_MINPH,394) +FD_MNEMONIC(EVX_MINPS,395) +FD_MNEMONIC(EVX_MINSD,396) +FD_MNEMONIC(EVX_MINSH,397) +FD_MNEMONIC(EVX_MINSS,398) +FD_MNEMONIC(EVX_MOVAPD,399) +FD_MNEMONIC(EVX_MOVAPS,400) +FD_MNEMONIC(EVX_MOVDDUP,401) +FD_MNEMONIC(EVX_MOVDQA32,402) +FD_MNEMONIC(EVX_MOVDQA64,403) +FD_MNEMONIC(EVX_MOVDQU16,404) +FD_MNEMONIC(EVX_MOVDQU32,405) +FD_MNEMONIC(EVX_MOVDQU64,406) +FD_MNEMONIC(EVX_MOVDQU8,407) +FD_MNEMONIC(EVX_MOVHLPS,408) +FD_MNEMONIC(EVX_MOVHPD,409) +FD_MNEMONIC(EVX_MOVHPS,410) +FD_MNEMONIC(EVX_MOVLHPS,411) +FD_MNEMONIC(EVX_MOVLPD,412) +FD_MNEMONIC(EVX_MOVLPS,413) +FD_MNEMONIC(EVX_MOVNTDQ,414) +FD_MNEMONIC(EVX_MOVNTDQA,415) +FD_MNEMONIC(EVX_MOVNTPD,416) +FD_MNEMONIC(EVX_MOVNTPS,417) +FD_MNEMONIC(EVX_MOVQ,418) +FD_MNEMONIC(EVX_MOVSD,419) +FD_MNEMONIC(EVX_MOVSH,420) +FD_MNEMONIC(EVX_MOVSHDUP,421) +FD_MNEMONIC(EVX_MOVSLDUP,422) +FD_MNEMONIC(EVX_MOVSS,423) +FD_MNEMONIC(EVX_MOVUPD,424) +FD_MNEMONIC(EVX_MOVUPS,425) +FD_MNEMONIC(EVX_MOVW_G2X,426) +FD_MNEMONIC(EVX_MOVW_X2G,427) +FD_MNEMONIC(EVX_MOV_G2X,428) +FD_MNEMONIC(EVX_MOV_X2G,429) +FD_MNEMONIC(EVX_MULPD,430) +FD_MNEMONIC(EVX_MULPH,431) +FD_MNEMONIC(EVX_MULPS,432) +FD_MNEMONIC(EVX_MULSD,433) +FD_MNEMONIC(EVX_MULSH,434) +FD_MNEMONIC(EVX_MULSS,435) +FD_MNEMONIC(EVX_ORPD,436) +FD_MNEMONIC(EVX_ORPS,437) +FD_MNEMONIC(EVX_P2INTERSECTD,438) +FD_MNEMONIC(EVX_P2INTERSECTQ,439) +FD_MNEMONIC(EVX_PABSB,440) +FD_MNEMONIC(EVX_PABSD,441) +FD_MNEMONIC(EVX_PABSQ,442) +FD_MNEMONIC(EVX_PABSW,443) +FD_MNEMONIC(EVX_PACKSSDW,444) +FD_MNEMONIC(EVX_PACKSSWB,445) +FD_MNEMONIC(EVX_PACKUSDW,446) +FD_MNEMONIC(EVX_PACKUSWB,447) +FD_MNEMONIC(EVX_PADDB,448) +FD_MNEMONIC(EVX_PADDD,449) +FD_MNEMONIC(EVX_PADDQ,450) +FD_MNEMONIC(EVX_PADDSB,451) +FD_MNEMONIC(EVX_PADDSW,452) +FD_MNEMONIC(EVX_PADDUSB,453) +FD_MNEMONIC(EVX_PADDUSW,454) +FD_MNEMONIC(EVX_PADDW,455) +FD_MNEMONIC(EVX_PALIGNR,456) +FD_MNEMONIC(EVX_PANDD,457) +FD_MNEMONIC(EVX_PANDND,458) +FD_MNEMONIC(EVX_PANDNQ,459) +FD_MNEMONIC(EVX_PANDQ,460) +FD_MNEMONIC(EVX_PAVGB,461) +FD_MNEMONIC(EVX_PAVGW,462) +FD_MNEMONIC(EVX_PBLENDMB,463) +FD_MNEMONIC(EVX_PBLENDMD,464) +FD_MNEMONIC(EVX_PBLENDMQ,465) +FD_MNEMONIC(EVX_PBLENDMW,466) +FD_MNEMONIC(EVX_PBROADCAST,467) +FD_MNEMONIC(EVX_PBROADCASTB,468) +FD_MNEMONIC(EVX_PBROADCASTD,469) +FD_MNEMONIC(EVX_PBROADCASTMB2Q,470) +FD_MNEMONIC(EVX_PBROADCASTMW2D,471) +FD_MNEMONIC(EVX_PBROADCASTQ,472) +FD_MNEMONIC(EVX_PBROADCASTW,473) +FD_MNEMONIC(EVX_PCLMULQDQ,474) +FD_MNEMONIC(EVX_PCMPB,475) +FD_MNEMONIC(EVX_PCMPD,476) +FD_MNEMONIC(EVX_PCMPEQB,477) +FD_MNEMONIC(EVX_PCMPEQD,478) +FD_MNEMONIC(EVX_PCMPEQQ,479) +FD_MNEMONIC(EVX_PCMPEQW,480) +FD_MNEMONIC(EVX_PCMPGTB,481) +FD_MNEMONIC(EVX_PCMPGTD,482) +FD_MNEMONIC(EVX_PCMPGTQ,483) +FD_MNEMONIC(EVX_PCMPGTW,484) +FD_MNEMONIC(EVX_PCMPQ,485) +FD_MNEMONIC(EVX_PCMPUB,486) +FD_MNEMONIC(EVX_PCMPUD,487) +FD_MNEMONIC(EVX_PCMPUQ,488) +FD_MNEMONIC(EVX_PCMPUW,489) +FD_MNEMONIC(EVX_PCMPW,490) +FD_MNEMONIC(EVX_PCOMPRESSB,491) +FD_MNEMONIC(EVX_PCOMPRESSD,492) +FD_MNEMONIC(EVX_PCOMPRESSQ,493) +FD_MNEMONIC(EVX_PCOMPRESSW,494) +FD_MNEMONIC(EVX_PCONFLICTD,495) +FD_MNEMONIC(EVX_PCONFLICTQ,496) +FD_MNEMONIC(EVX_PDPBUSD,497) +FD_MNEMONIC(EVX_PDPBUSDS,498) +FD_MNEMONIC(EVX_PDPWSSD,499) +FD_MNEMONIC(EVX_PDPWSSDS,500) +FD_MNEMONIC(EVX_PERMB,501) +FD_MNEMONIC(EVX_PERMD,502) +FD_MNEMONIC(EVX_PERMI2B,503) +FD_MNEMONIC(EVX_PERMI2D,504) +FD_MNEMONIC(EVX_PERMI2PD,505) +FD_MNEMONIC(EVX_PERMI2PS,506) +FD_MNEMONIC(EVX_PERMI2Q,507) +FD_MNEMONIC(EVX_PERMI2W,508) +FD_MNEMONIC(EVX_PERMILPD,509) +FD_MNEMONIC(EVX_PERMILPS,510) +FD_MNEMONIC(EVX_PERMPD,511) +FD_MNEMONIC(EVX_PERMPS,512) +FD_MNEMONIC(EVX_PERMQ,513) +FD_MNEMONIC(EVX_PERMT2B,514) +FD_MNEMONIC(EVX_PERMT2D,515) +FD_MNEMONIC(EVX_PERMT2PD,516) +FD_MNEMONIC(EVX_PERMT2PS,517) +FD_MNEMONIC(EVX_PERMT2Q,518) +FD_MNEMONIC(EVX_PERMT2W,519) +FD_MNEMONIC(EVX_PERMW,520) +FD_MNEMONIC(EVX_PEXPANDB,521) +FD_MNEMONIC(EVX_PEXPANDD,522) +FD_MNEMONIC(EVX_PEXPANDQ,523) +FD_MNEMONIC(EVX_PEXPANDW,524) +FD_MNEMONIC(EVX_PEXTR,525) +FD_MNEMONIC(EVX_PEXTRB,526) +FD_MNEMONIC(EVX_PEXTRW,527) +FD_MNEMONIC(EVX_PGATHERDD,528) +FD_MNEMONIC(EVX_PGATHERDQ,529) +FD_MNEMONIC(EVX_PGATHERQD,530) +FD_MNEMONIC(EVX_PGATHERQQ,531) +FD_MNEMONIC(EVX_PINSR,532) +FD_MNEMONIC(EVX_PLZCNTD,533) +FD_MNEMONIC(EVX_PLZCNTQ,534) +FD_MNEMONIC(EVX_PMADD52HUQ,535) +FD_MNEMONIC(EVX_PMADD52LUQ,536) +FD_MNEMONIC(EVX_PMADDUBSW,537) +FD_MNEMONIC(EVX_PMADDWD,538) +FD_MNEMONIC(EVX_PMAXSB,539) +FD_MNEMONIC(EVX_PMAXSD,540) +FD_MNEMONIC(EVX_PMAXSQ,541) +FD_MNEMONIC(EVX_PMAXSW,542) +FD_MNEMONIC(EVX_PMAXUB,543) +FD_MNEMONIC(EVX_PMAXUD,544) +FD_MNEMONIC(EVX_PMAXUQ,545) +FD_MNEMONIC(EVX_PMAXUW,546) +FD_MNEMONIC(EVX_PMINSB,547) +FD_MNEMONIC(EVX_PMINSD,548) +FD_MNEMONIC(EVX_PMINSQ,549) +FD_MNEMONIC(EVX_PMINSW,550) +FD_MNEMONIC(EVX_PMINUB,551) +FD_MNEMONIC(EVX_PMINUD,552) +FD_MNEMONIC(EVX_PMINUQ,553) +FD_MNEMONIC(EVX_PMINUW,554) +FD_MNEMONIC(EVX_PMOVB2M,555) +FD_MNEMONIC(EVX_PMOVD2M,556) +FD_MNEMONIC(EVX_PMOVDB,557) +FD_MNEMONIC(EVX_PMOVDW,558) +FD_MNEMONIC(EVX_PMOVM2B,559) +FD_MNEMONIC(EVX_PMOVM2D,560) +FD_MNEMONIC(EVX_PMOVM2Q,561) +FD_MNEMONIC(EVX_PMOVM2W,562) +FD_MNEMONIC(EVX_PMOVQ2M,563) +FD_MNEMONIC(EVX_PMOVQB,564) +FD_MNEMONIC(EVX_PMOVQD,565) +FD_MNEMONIC(EVX_PMOVQW,566) +FD_MNEMONIC(EVX_PMOVSDB,567) +FD_MNEMONIC(EVX_PMOVSDW,568) +FD_MNEMONIC(EVX_PMOVSQB,569) +FD_MNEMONIC(EVX_PMOVSQD,570) +FD_MNEMONIC(EVX_PMOVSQW,571) +FD_MNEMONIC(EVX_PMOVSWB,572) +FD_MNEMONIC(EVX_PMOVSXBD,573) +FD_MNEMONIC(EVX_PMOVSXBQ,574) +FD_MNEMONIC(EVX_PMOVSXBW,575) +FD_MNEMONIC(EVX_PMOVSXDQ,576) +FD_MNEMONIC(EVX_PMOVSXWD,577) +FD_MNEMONIC(EVX_PMOVSXWQ,578) +FD_MNEMONIC(EVX_PMOVUSDB,579) +FD_MNEMONIC(EVX_PMOVUSDW,580) +FD_MNEMONIC(EVX_PMOVUSQB,581) +FD_MNEMONIC(EVX_PMOVUSQD,582) +FD_MNEMONIC(EVX_PMOVUSQW,583) +FD_MNEMONIC(EVX_PMOVUSWB,584) +FD_MNEMONIC(EVX_PMOVW2M,585) +FD_MNEMONIC(EVX_PMOVWB,586) +FD_MNEMONIC(EVX_PMOVZXBD,587) +FD_MNEMONIC(EVX_PMOVZXBQ,588) +FD_MNEMONIC(EVX_PMOVZXBW,589) +FD_MNEMONIC(EVX_PMOVZXDQ,590) +FD_MNEMONIC(EVX_PMOVZXWD,591) +FD_MNEMONIC(EVX_PMOVZXWQ,592) +FD_MNEMONIC(EVX_PMULDQ,593) +FD_MNEMONIC(EVX_PMULHRSW,594) +FD_MNEMONIC(EVX_PMULHUW,595) +FD_MNEMONIC(EVX_PMULHW,596) +FD_MNEMONIC(EVX_PMULLD,597) +FD_MNEMONIC(EVX_PMULLQ,598) +FD_MNEMONIC(EVX_PMULLW,599) +FD_MNEMONIC(EVX_PMULTISHIFTQB,600) +FD_MNEMONIC(EVX_PMULUDQ,601) +FD_MNEMONIC(EVX_POPCNTB,602) +FD_MNEMONIC(EVX_POPCNTD,603) +FD_MNEMONIC(EVX_POPCNTQ,604) +FD_MNEMONIC(EVX_POPCNTW,605) +FD_MNEMONIC(EVX_PORD,606) +FD_MNEMONIC(EVX_PORQ,607) +FD_MNEMONIC(EVX_PROLD,608) +FD_MNEMONIC(EVX_PROLQ,609) +FD_MNEMONIC(EVX_PROLVD,610) +FD_MNEMONIC(EVX_PROLVQ,611) +FD_MNEMONIC(EVX_PRORD,612) +FD_MNEMONIC(EVX_PRORQ,613) +FD_MNEMONIC(EVX_PRORVD,614) +FD_MNEMONIC(EVX_PRORVQ,615) +FD_MNEMONIC(EVX_PSADBW,616) +FD_MNEMONIC(EVX_PSCATTERDD,617) +FD_MNEMONIC(EVX_PSCATTERDQ,618) +FD_MNEMONIC(EVX_PSCATTERQD,619) +FD_MNEMONIC(EVX_PSCATTERQQ,620) +FD_MNEMONIC(EVX_PSHLDD,621) +FD_MNEMONIC(EVX_PSHLDQ,622) +FD_MNEMONIC(EVX_PSHLDVD,623) +FD_MNEMONIC(EVX_PSHLDVQ,624) +FD_MNEMONIC(EVX_PSHLDVW,625) +FD_MNEMONIC(EVX_PSHLDW,626) +FD_MNEMONIC(EVX_PSHRDD,627) +FD_MNEMONIC(EVX_PSHRDQ,628) +FD_MNEMONIC(EVX_PSHRDVD,629) +FD_MNEMONIC(EVX_PSHRDVQ,630) +FD_MNEMONIC(EVX_PSHRDVW,631) +FD_MNEMONIC(EVX_PSHRDW,632) +FD_MNEMONIC(EVX_PSHUFB,633) +FD_MNEMONIC(EVX_PSHUFBITQMB,634) +FD_MNEMONIC(EVX_PSHUFD,635) +FD_MNEMONIC(EVX_PSHUFHW,636) +FD_MNEMONIC(EVX_PSHUFLW,637) +FD_MNEMONIC(EVX_PSLLD,638) +FD_MNEMONIC(EVX_PSLLDQ,639) +FD_MNEMONIC(EVX_PSLLQ,640) +FD_MNEMONIC(EVX_PSLLVD,641) +FD_MNEMONIC(EVX_PSLLVQ,642) +FD_MNEMONIC(EVX_PSLLVW,643) +FD_MNEMONIC(EVX_PSLLW,644) +FD_MNEMONIC(EVX_PSRAD,645) +FD_MNEMONIC(EVX_PSRAQ,646) +FD_MNEMONIC(EVX_PSRAVD,647) +FD_MNEMONIC(EVX_PSRAVQ,648) +FD_MNEMONIC(EVX_PSRAVW,649) +FD_MNEMONIC(EVX_PSRAW,650) +FD_MNEMONIC(EVX_PSRLD,651) +FD_MNEMONIC(EVX_PSRLDQ,652) +FD_MNEMONIC(EVX_PSRLQ,653) +FD_MNEMONIC(EVX_PSRLVD,654) +FD_MNEMONIC(EVX_PSRLVQ,655) +FD_MNEMONIC(EVX_PSRLVW,656) +FD_MNEMONIC(EVX_PSRLW,657) +FD_MNEMONIC(EVX_PSUBB,658) +FD_MNEMONIC(EVX_PSUBD,659) +FD_MNEMONIC(EVX_PSUBQ,660) +FD_MNEMONIC(EVX_PSUBSB,661) +FD_MNEMONIC(EVX_PSUBSW,662) +FD_MNEMONIC(EVX_PSUBUSB,663) +FD_MNEMONIC(EVX_PSUBUSW,664) +FD_MNEMONIC(EVX_PSUBW,665) +FD_MNEMONIC(EVX_PTERNLOGD,666) +FD_MNEMONIC(EVX_PTERNLOGQ,667) +FD_MNEMONIC(EVX_PTESTMB,668) +FD_MNEMONIC(EVX_PTESTMD,669) +FD_MNEMONIC(EVX_PTESTMQ,670) +FD_MNEMONIC(EVX_PTESTMW,671) +FD_MNEMONIC(EVX_PTESTNMB,672) +FD_MNEMONIC(EVX_PTESTNMD,673) +FD_MNEMONIC(EVX_PTESTNMQ,674) +FD_MNEMONIC(EVX_PTESTNMW,675) +FD_MNEMONIC(EVX_PUNPCKHBW,676) +FD_MNEMONIC(EVX_PUNPCKHDQ,677) +FD_MNEMONIC(EVX_PUNPCKHQDQ,678) +FD_MNEMONIC(EVX_PUNPCKHWD,679) +FD_MNEMONIC(EVX_PUNPCKLBW,680) +FD_MNEMONIC(EVX_PUNPCKLDQ,681) +FD_MNEMONIC(EVX_PUNPCKLQDQ,682) +FD_MNEMONIC(EVX_PUNPCKLWD,683) +FD_MNEMONIC(EVX_PXORD,684) +FD_MNEMONIC(EVX_PXORQ,685) +FD_MNEMONIC(EVX_RANGEPD,686) +FD_MNEMONIC(EVX_RANGEPS,687) +FD_MNEMONIC(EVX_RANGESD,688) +FD_MNEMONIC(EVX_RANGESS,689) +FD_MNEMONIC(EVX_RCP14PD,690) +FD_MNEMONIC(EVX_RCP14PS,691) +FD_MNEMONIC(EVX_RCP14SD,692) +FD_MNEMONIC(EVX_RCP14SS,693) +FD_MNEMONIC(EVX_RCPPH,694) +FD_MNEMONIC(EVX_RCPSH,695) +FD_MNEMONIC(EVX_REDUCEPD,696) +FD_MNEMONIC(EVX_REDUCEPH,697) +FD_MNEMONIC(EVX_REDUCEPS,698) +FD_MNEMONIC(EVX_REDUCESD,699) +FD_MNEMONIC(EVX_REDUCESH,700) +FD_MNEMONIC(EVX_REDUCESS,701) +FD_MNEMONIC(EVX_RNDSCALEPD,702) +FD_MNEMONIC(EVX_RNDSCALEPH,703) +FD_MNEMONIC(EVX_RNDSCALEPS,704) +FD_MNEMONIC(EVX_RNDSCALESD,705) +FD_MNEMONIC(EVX_RNDSCALESH,706) +FD_MNEMONIC(EVX_RNDSCALESS,707) +FD_MNEMONIC(EVX_RSQRT14PD,708) +FD_MNEMONIC(EVX_RSQRT14PS,709) +FD_MNEMONIC(EVX_RSQRT14SD,710) +FD_MNEMONIC(EVX_RSQRT14SS,711) +FD_MNEMONIC(EVX_RSQRTPH,712) +FD_MNEMONIC(EVX_RSQRTSH,713) +FD_MNEMONIC(EVX_SCALEFPD,714) +FD_MNEMONIC(EVX_SCALEFPH,715) +FD_MNEMONIC(EVX_SCALEFPS,716) +FD_MNEMONIC(EVX_SCALEFSD,717) +FD_MNEMONIC(EVX_SCALEFSH,718) +FD_MNEMONIC(EVX_SCALEFSS,719) +FD_MNEMONIC(EVX_SCATTERDPD,720) +FD_MNEMONIC(EVX_SCATTERDPS,721) +FD_MNEMONIC(EVX_SCATTERQPD,722) +FD_MNEMONIC(EVX_SCATTERQPS,723) +FD_MNEMONIC(EVX_SHUFF32X4,724) +FD_MNEMONIC(EVX_SHUFF64X2,725) +FD_MNEMONIC(EVX_SHUFI32X4,726) +FD_MNEMONIC(EVX_SHUFI64X2,727) +FD_MNEMONIC(EVX_SHUFPD,728) +FD_MNEMONIC(EVX_SHUFPS,729) +FD_MNEMONIC(EVX_SQRTPD,730) +FD_MNEMONIC(EVX_SQRTPH,731) +FD_MNEMONIC(EVX_SQRTPS,732) +FD_MNEMONIC(EVX_SQRTSD,733) +FD_MNEMONIC(EVX_SQRTSH,734) +FD_MNEMONIC(EVX_SQRTSS,735) +FD_MNEMONIC(EVX_SUBPD,736) +FD_MNEMONIC(EVX_SUBPH,737) +FD_MNEMONIC(EVX_SUBPS,738) +FD_MNEMONIC(EVX_SUBSD,739) +FD_MNEMONIC(EVX_SUBSH,740) +FD_MNEMONIC(EVX_SUBSS,741) +FD_MNEMONIC(EVX_UCOMISD,742) +FD_MNEMONIC(EVX_UCOMISH,743) +FD_MNEMONIC(EVX_UCOMISS,744) +FD_MNEMONIC(EVX_UNPCKHPD,745) +FD_MNEMONIC(EVX_UNPCKHPS,746) +FD_MNEMONIC(EVX_UNPCKLPD,747) +FD_MNEMONIC(EVX_UNPCKLPS,748) +FD_MNEMONIC(EVX_XORPD,749) +FD_MNEMONIC(EVX_XORPS,750) +FD_MNEMONIC(F2XM1,751) +FD_MNEMONIC(FABS,752) +FD_MNEMONIC(FADD,753) +FD_MNEMONIC(FADDP,754) +FD_MNEMONIC(FBLD,755) +FD_MNEMONIC(FBSTP,756) +FD_MNEMONIC(FCHS,757) +FD_MNEMONIC(FCLEX,758) +FD_MNEMONIC(FCMOVB,759) +FD_MNEMONIC(FCMOVBE,760) +FD_MNEMONIC(FCMOVE,761) +FD_MNEMONIC(FCMOVNB,762) +FD_MNEMONIC(FCMOVNBE,763) +FD_MNEMONIC(FCMOVNE,764) +FD_MNEMONIC(FCMOVNU,765) +FD_MNEMONIC(FCMOVU,766) +FD_MNEMONIC(FCOM,767) +FD_MNEMONIC(FCOMI,768) +FD_MNEMONIC(FCOMIP,769) +FD_MNEMONIC(FCOMP,770) +FD_MNEMONIC(FCOMPP,771) +FD_MNEMONIC(FCOS,772) +FD_MNEMONIC(FDECSTP,773) +FD_MNEMONIC(FDIV,774) +FD_MNEMONIC(FDIVP,775) +FD_MNEMONIC(FDIVR,776) +FD_MNEMONIC(FDIVRP,777) +FD_MNEMONIC(FEMMS,778) +FD_MNEMONIC(FFREE,779) +FD_MNEMONIC(FIADD,780) +FD_MNEMONIC(FICOM,781) +FD_MNEMONIC(FICOMP,782) +FD_MNEMONIC(FIDIV,783) +FD_MNEMONIC(FIDIVR,784) +FD_MNEMONIC(FILD,785) +FD_MNEMONIC(FIMUL,786) +FD_MNEMONIC(FINCSTP,787) +FD_MNEMONIC(FINIT,788) +FD_MNEMONIC(FIST,789) +FD_MNEMONIC(FISTP,790) +FD_MNEMONIC(FISTTP,791) +FD_MNEMONIC(FISUB,792) +FD_MNEMONIC(FISUBR,793) +FD_MNEMONIC(FLD,794) +FD_MNEMONIC(FLD1,795) +FD_MNEMONIC(FLDCW,796) +FD_MNEMONIC(FLDENV,797) +FD_MNEMONIC(FLDL2E,798) +FD_MNEMONIC(FLDL2T,799) +FD_MNEMONIC(FLDLG2,800) +FD_MNEMONIC(FLDLN2,801) +FD_MNEMONIC(FLDPI,802) +FD_MNEMONIC(FLDZ,803) +FD_MNEMONIC(FMUL,804) +FD_MNEMONIC(FMULP,805) +FD_MNEMONIC(FNOP,806) +FD_MNEMONIC(FPATAN,807) +FD_MNEMONIC(FPREM,808) +FD_MNEMONIC(FPREM1,809) +FD_MNEMONIC(FPTAN,810) +FD_MNEMONIC(FRNDINT,811) +FD_MNEMONIC(FRSTOR,812) +FD_MNEMONIC(FSAVE,813) +FD_MNEMONIC(FSCALE,814) +FD_MNEMONIC(FSIN,815) +FD_MNEMONIC(FSINCOS,816) +FD_MNEMONIC(FSQRT,817) +FD_MNEMONIC(FST,818) +FD_MNEMONIC(FSTCW,819) +FD_MNEMONIC(FSTENV,820) +FD_MNEMONIC(FSTP,821) +FD_MNEMONIC(FSTSW,822) +FD_MNEMONIC(FSUB,823) +FD_MNEMONIC(FSUBP,824) +FD_MNEMONIC(FSUBR,825) +FD_MNEMONIC(FSUBRP,826) +FD_MNEMONIC(FTST,827) +FD_MNEMONIC(FUCOM,828) +FD_MNEMONIC(FUCOMI,829) +FD_MNEMONIC(FUCOMIP,830) +FD_MNEMONIC(FUCOMP,831) +FD_MNEMONIC(FUCOMPP,832) +FD_MNEMONIC(FWAIT,833) +FD_MNEMONIC(FXAM,834) +FD_MNEMONIC(FXCH,835) +FD_MNEMONIC(FXRSTOR,836) +FD_MNEMONIC(FXSAVE,837) +FD_MNEMONIC(FXTRACT,838) +FD_MNEMONIC(FYL2X,839) +FD_MNEMONIC(FYL2XP1,840) +FD_MNEMONIC(GETSEC,841) +FD_MNEMONIC(GF2P8AFFINEINVQB,842) +FD_MNEMONIC(GF2P8AFFINEQB,843) +FD_MNEMONIC(GF2P8MULB,844) +FD_MNEMONIC(HLT,845) +FD_MNEMONIC(HRESET,846) +FD_MNEMONIC(IDIV,847) +FD_MNEMONIC(IMUL,848) +FD_MNEMONIC(IN,849) +FD_MNEMONIC(INC,850) +FD_MNEMONIC(INCSSP,851) +FD_MNEMONIC(INS,852) +FD_MNEMONIC(INT,853) +FD_MNEMONIC(INT1,854) +FD_MNEMONIC(INT3,855) +FD_MNEMONIC(INTO,856) +FD_MNEMONIC(INVD,857) +FD_MNEMONIC(INVEPT,858) +FD_MNEMONIC(INVLPG,859) +FD_MNEMONIC(INVLPGA,860) +FD_MNEMONIC(INVLPGB,861) +FD_MNEMONIC(INVPCID,862) +FD_MNEMONIC(INVVPID,863) +FD_MNEMONIC(IRET,864) +FD_MNEMONIC(JA,865) +FD_MNEMONIC(JBE,866) +FD_MNEMONIC(JC,867) +FD_MNEMONIC(JCXZ,868) +FD_MNEMONIC(JG,869) +FD_MNEMONIC(JGE,870) +FD_MNEMONIC(JL,871) +FD_MNEMONIC(JLE,872) +FD_MNEMONIC(JMP,873) +FD_MNEMONIC(JMPF,874) +FD_MNEMONIC(JNC,875) +FD_MNEMONIC(JNO,876) +FD_MNEMONIC(JNP,877) +FD_MNEMONIC(JNS,878) +FD_MNEMONIC(JNZ,879) +FD_MNEMONIC(JO,880) +FD_MNEMONIC(JP,881) +FD_MNEMONIC(JS,882) +FD_MNEMONIC(JZ,883) +FD_MNEMONIC(KADDB,884) +FD_MNEMONIC(KADDD,885) +FD_MNEMONIC(KADDQ,886) +FD_MNEMONIC(KADDW,887) +FD_MNEMONIC(KANDB,888) +FD_MNEMONIC(KANDD,889) +FD_MNEMONIC(KANDNB,890) +FD_MNEMONIC(KANDND,891) +FD_MNEMONIC(KANDNQ,892) +FD_MNEMONIC(KANDNW,893) +FD_MNEMONIC(KANDQ,894) +FD_MNEMONIC(KANDW,895) +FD_MNEMONIC(KMOVB,896) +FD_MNEMONIC(KMOVD,897) +FD_MNEMONIC(KMOVQ,898) +FD_MNEMONIC(KMOVW,899) +FD_MNEMONIC(KNOTB,900) +FD_MNEMONIC(KNOTD,901) +FD_MNEMONIC(KNOTQ,902) +FD_MNEMONIC(KNOTW,903) +FD_MNEMONIC(KORB,904) +FD_MNEMONIC(KORD,905) +FD_MNEMONIC(KORQ,906) +FD_MNEMONIC(KORTESTB,907) +FD_MNEMONIC(KORTESTD,908) +FD_MNEMONIC(KORTESTQ,909) +FD_MNEMONIC(KORTESTW,910) +FD_MNEMONIC(KORW,911) +FD_MNEMONIC(KSHIFTLB,912) +FD_MNEMONIC(KSHIFTLD,913) +FD_MNEMONIC(KSHIFTLQ,914) +FD_MNEMONIC(KSHIFTLW,915) +FD_MNEMONIC(KSHIFTRB,916) +FD_MNEMONIC(KSHIFTRD,917) +FD_MNEMONIC(KSHIFTRQ,918) +FD_MNEMONIC(KSHIFTRW,919) +FD_MNEMONIC(KTESTB,920) +FD_MNEMONIC(KTESTD,921) +FD_MNEMONIC(KTESTQ,922) +FD_MNEMONIC(KTESTW,923) +FD_MNEMONIC(KUNPCKBW,924) +FD_MNEMONIC(KUNPCKDQ,925) +FD_MNEMONIC(KUNPCKWD,926) +FD_MNEMONIC(KXNORB,927) +FD_MNEMONIC(KXNORD,928) +FD_MNEMONIC(KXNORQ,929) +FD_MNEMONIC(KXNORW,930) +FD_MNEMONIC(KXORB,931) +FD_MNEMONIC(KXORD,932) +FD_MNEMONIC(KXORQ,933) +FD_MNEMONIC(KXORW,934) +FD_MNEMONIC(LAHF,935) +FD_MNEMONIC(LAR,936) +FD_MNEMONIC(LDMXCSR,937) +FD_MNEMONIC(LDS,938) +FD_MNEMONIC(LDTILECFG,939) +FD_MNEMONIC(LEA,940) +FD_MNEMONIC(LEAVE,941) +FD_MNEMONIC(LES,942) +FD_MNEMONIC(LFENCE,943) +FD_MNEMONIC(LFS,944) +FD_MNEMONIC(LGDT,945) +FD_MNEMONIC(LGS,946) +FD_MNEMONIC(LIDT,947) +FD_MNEMONIC(LKGS,948) +FD_MNEMONIC(LLDT,949) +FD_MNEMONIC(LMSW,950) +FD_MNEMONIC(LOADIWKEY,951) +FD_MNEMONIC(LODS,952) +FD_MNEMONIC(LOOP,953) +FD_MNEMONIC(LOOPNZ,954) +FD_MNEMONIC(LOOPZ,955) +FD_MNEMONIC(LSL,956) +FD_MNEMONIC(LSS,957) +FD_MNEMONIC(LTR,958) +FD_MNEMONIC(LZCNT,959) +FD_MNEMONIC(MCOMMIT,960) +FD_MNEMONIC(MFENCE,961) +FD_MNEMONIC(MMX_CVTPD2PI,962) +FD_MNEMONIC(MMX_CVTPI2PD,963) +FD_MNEMONIC(MMX_CVTPI2PS,964) +FD_MNEMONIC(MMX_CVTPS2PI,965) +FD_MNEMONIC(MMX_CVTTPD2PI,966) +FD_MNEMONIC(MMX_CVTTPS2PI,967) +FD_MNEMONIC(MMX_EMMS,968) +FD_MNEMONIC(MMX_MASKMOVQ,969) +FD_MNEMONIC(MMX_MOVD,970) +FD_MNEMONIC(MMX_MOVDQ2Q,971) +FD_MNEMONIC(MMX_MOVNTQ,972) +FD_MNEMONIC(MMX_MOVQ,973) +FD_MNEMONIC(MMX_MOVQ2DQ,974) +FD_MNEMONIC(MMX_PABSB,975) +FD_MNEMONIC(MMX_PABSD,976) +FD_MNEMONIC(MMX_PABSW,977) +FD_MNEMONIC(MMX_PACKSSDW,978) +FD_MNEMONIC(MMX_PACKSSWB,979) +FD_MNEMONIC(MMX_PACKUSWB,980) +FD_MNEMONIC(MMX_PADDB,981) +FD_MNEMONIC(MMX_PADDD,982) +FD_MNEMONIC(MMX_PADDQ,983) +FD_MNEMONIC(MMX_PADDSB,984) +FD_MNEMONIC(MMX_PADDSW,985) +FD_MNEMONIC(MMX_PADDUSB,986) +FD_MNEMONIC(MMX_PADDUSW,987) +FD_MNEMONIC(MMX_PADDW,988) +FD_MNEMONIC(MMX_PALIGNR,989) +FD_MNEMONIC(MMX_PAND,990) +FD_MNEMONIC(MMX_PANDN,991) +FD_MNEMONIC(MMX_PAVGB,992) +FD_MNEMONIC(MMX_PAVGW,993) +FD_MNEMONIC(MMX_PCMPEQB,994) +FD_MNEMONIC(MMX_PCMPEQD,995) +FD_MNEMONIC(MMX_PCMPEQW,996) +FD_MNEMONIC(MMX_PCMPGTB,997) +FD_MNEMONIC(MMX_PCMPGTD,998) +FD_MNEMONIC(MMX_PCMPGTW,999) +FD_MNEMONIC(MMX_PEXTRW,1000) +FD_MNEMONIC(MMX_PHADDD,1001) +FD_MNEMONIC(MMX_PHADDSW,1002) +FD_MNEMONIC(MMX_PHADDW,1003) +FD_MNEMONIC(MMX_PHSUBD,1004) +FD_MNEMONIC(MMX_PHSUBSW,1005) +FD_MNEMONIC(MMX_PHSUBW,1006) +FD_MNEMONIC(MMX_PINSRW,1007) +FD_MNEMONIC(MMX_PMADDUBSW,1008) +FD_MNEMONIC(MMX_PMADDWD,1009) +FD_MNEMONIC(MMX_PMAXSW,1010) +FD_MNEMONIC(MMX_PMAXUB,1011) +FD_MNEMONIC(MMX_PMINSW,1012) +FD_MNEMONIC(MMX_PMINUB,1013) +FD_MNEMONIC(MMX_PMOVMSKB,1014) +FD_MNEMONIC(MMX_PMULHRSW,1015) +FD_MNEMONIC(MMX_PMULHUW,1016) +FD_MNEMONIC(MMX_PMULHW,1017) +FD_MNEMONIC(MMX_PMULLW,1018) +FD_MNEMONIC(MMX_PMULUDQ,1019) +FD_MNEMONIC(MMX_POR,1020) +FD_MNEMONIC(MMX_PSADBW,1021) +FD_MNEMONIC(MMX_PSHUFB,1022) +FD_MNEMONIC(MMX_PSHUFW,1023) +FD_MNEMONIC(MMX_PSIGNB,1024) +FD_MNEMONIC(MMX_PSIGND,1025) +FD_MNEMONIC(MMX_PSIGNW,1026) +FD_MNEMONIC(MMX_PSLLD,1027) +FD_MNEMONIC(MMX_PSLLQ,1028) +FD_MNEMONIC(MMX_PSLLW,1029) +FD_MNEMONIC(MMX_PSRAD,1030) +FD_MNEMONIC(MMX_PSRAW,1031) +FD_MNEMONIC(MMX_PSRLD,1032) +FD_MNEMONIC(MMX_PSRLQ,1033) +FD_MNEMONIC(MMX_PSRLW,1034) +FD_MNEMONIC(MMX_PSUBB,1035) +FD_MNEMONIC(MMX_PSUBD,1036) +FD_MNEMONIC(MMX_PSUBQ,1037) +FD_MNEMONIC(MMX_PSUBSB,1038) +FD_MNEMONIC(MMX_PSUBSW,1039) +FD_MNEMONIC(MMX_PSUBUSB,1040) +FD_MNEMONIC(MMX_PSUBUSW,1041) +FD_MNEMONIC(MMX_PSUBW,1042) +FD_MNEMONIC(MMX_PUNPCKHBW,1043) +FD_MNEMONIC(MMX_PUNPCKHDQ,1044) +FD_MNEMONIC(MMX_PUNPCKHWD,1045) +FD_MNEMONIC(MMX_PUNPCKLBW,1046) +FD_MNEMONIC(MMX_PUNPCKLDQ,1047) +FD_MNEMONIC(MMX_PUNPCKLWD,1048) +FD_MNEMONIC(MMX_PXOR,1049) +FD_MNEMONIC(MONITOR,1050) +FD_MNEMONIC(MONITORX,1051) +FD_MNEMONIC(MOV,1052) +FD_MNEMONIC(MOVABS,1053) +FD_MNEMONIC(MOVBE,1054) +FD_MNEMONIC(MOVDIR64B,1055) +FD_MNEMONIC(MOVDIRI,1056) +FD_MNEMONIC(MOVNTI,1057) +FD_MNEMONIC(MOVS,1058) +FD_MNEMONIC(MOVSX,1059) +FD_MNEMONIC(MOVZX,1060) +FD_MNEMONIC(MOV_CR,1061) +FD_MNEMONIC(MOV_DR,1062) +FD_MNEMONIC(MOV_G2S,1063) +FD_MNEMONIC(MOV_S2G,1064) +FD_MNEMONIC(MUL,1065) +FD_MNEMONIC(MULX,1066) +FD_MNEMONIC(MWAIT,1067) +FD_MNEMONIC(MWAITX,1068) +FD_MNEMONIC(NEG,1069) +FD_MNEMONIC(NOP,1070) +FD_MNEMONIC(NOT,1071) +FD_MNEMONIC(OR,1072) +FD_MNEMONIC(OUT,1073) +FD_MNEMONIC(OUTS,1074) +FD_MNEMONIC(PAUSE,1075) +FD_MNEMONIC(PBNDKB,1076) +FD_MNEMONIC(PCONFIG,1077) +FD_MNEMONIC(PDEP,1078) +FD_MNEMONIC(PEXT,1079) +FD_MNEMONIC(POP,1080) +FD_MNEMONIC(POPA,1081) +FD_MNEMONIC(POPCNT,1082) +FD_MNEMONIC(POPF,1083) +FD_MNEMONIC(PREFETCH,1084) +FD_MNEMONIC(PREFETCHIT0,1085) +FD_MNEMONIC(PREFETCHIT1,1086) +FD_MNEMONIC(PREFETCHNTA,1087) +FD_MNEMONIC(PREFETCHT0,1088) +FD_MNEMONIC(PREFETCHT1,1089) +FD_MNEMONIC(PREFETCHT2,1090) +FD_MNEMONIC(PREFETCHW,1091) +FD_MNEMONIC(PREFETCHWT1,1092) +FD_MNEMONIC(PSMASH,1093) +FD_MNEMONIC(PTWRITE,1094) +FD_MNEMONIC(PUSH,1095) +FD_MNEMONIC(PUSHA,1096) +FD_MNEMONIC(PUSHF,1097) +FD_MNEMONIC(PVALIDATE,1098) +FD_MNEMONIC(RCL,1099) +FD_MNEMONIC(RCR,1100) +FD_MNEMONIC(RDFSBASE,1101) +FD_MNEMONIC(RDGSBASE,1102) +FD_MNEMONIC(RDMSR,1103) +FD_MNEMONIC(RDMSRLIST,1104) +FD_MNEMONIC(RDPID,1105) +FD_MNEMONIC(RDPKRU,1106) +FD_MNEMONIC(RDPMC,1107) +FD_MNEMONIC(RDPRU,1108) +FD_MNEMONIC(RDRAND,1109) +FD_MNEMONIC(RDSEED,1110) +FD_MNEMONIC(RDSSP,1111) +FD_MNEMONIC(RDTSC,1112) +FD_MNEMONIC(RDTSCP,1113) +FD_MNEMONIC(REP_MONTMUL,1114) +FD_MNEMONIC(REP_XCRYPTCBC,1115) +FD_MNEMONIC(REP_XCRYPTCFB,1116) +FD_MNEMONIC(REP_XCRYPTCTR,1117) +FD_MNEMONIC(REP_XCRYPTECB,1118) +FD_MNEMONIC(REP_XCRYPTOFB,1119) +FD_MNEMONIC(REP_XSHA1,1120) +FD_MNEMONIC(REP_XSHA256,1121) +FD_MNEMONIC(REP_XSTORE,1122) +FD_MNEMONIC(RESERVED_NOP,1123) +FD_MNEMONIC(RESERVED_PREFETCH,1124) +FD_MNEMONIC(RET,1125) +FD_MNEMONIC(RETF,1126) +FD_MNEMONIC(RMPADJUST,1127) +FD_MNEMONIC(RMPQUERY,1128) +FD_MNEMONIC(RMPREAD,1129) +FD_MNEMONIC(RMPUPDATE,1130) +FD_MNEMONIC(ROL,1131) +FD_MNEMONIC(ROR,1132) +FD_MNEMONIC(RORX,1133) +FD_MNEMONIC(RSM,1134) +FD_MNEMONIC(RSTORSSP,1135) +FD_MNEMONIC(SAHF,1136) +FD_MNEMONIC(SAR,1137) +FD_MNEMONIC(SARX,1138) +FD_MNEMONIC(SAVEPREVSSP,1139) +FD_MNEMONIC(SBB,1140) +FD_MNEMONIC(SCAS,1141) +FD_MNEMONIC(SEAMCALL,1142) +FD_MNEMONIC(SEAMOPS,1143) +FD_MNEMONIC(SEAMRET,1144) +FD_MNEMONIC(SENDUIPI,1145) +FD_MNEMONIC(SERIALIZE,1146) +FD_MNEMONIC(SETA,1147) +FD_MNEMONIC(SETBE,1148) +FD_MNEMONIC(SETC,1149) +FD_MNEMONIC(SETG,1150) +FD_MNEMONIC(SETGE,1151) +FD_MNEMONIC(SETL,1152) +FD_MNEMONIC(SETLE,1153) +FD_MNEMONIC(SETNC,1154) +FD_MNEMONIC(SETNO,1155) +FD_MNEMONIC(SETNP,1156) +FD_MNEMONIC(SETNS,1157) +FD_MNEMONIC(SETNZ,1158) +FD_MNEMONIC(SETO,1159) +FD_MNEMONIC(SETP,1160) +FD_MNEMONIC(SETS,1161) +FD_MNEMONIC(SETSSBSY,1162) +FD_MNEMONIC(SETZ,1163) +FD_MNEMONIC(SFENCE,1164) +FD_MNEMONIC(SGDT,1165) +FD_MNEMONIC(SHA1MSG1,1166) +FD_MNEMONIC(SHA1MSG2,1167) +FD_MNEMONIC(SHA1NEXTE,1168) +FD_MNEMONIC(SHA1RNDS4,1169) +FD_MNEMONIC(SHA256MSG1,1170) +FD_MNEMONIC(SHA256MSG2,1171) +FD_MNEMONIC(SHA256RNDS2,1172) +FD_MNEMONIC(SHL,1173) +FD_MNEMONIC(SHLD,1174) +FD_MNEMONIC(SHLX,1175) +FD_MNEMONIC(SHR,1176) +FD_MNEMONIC(SHRD,1177) +FD_MNEMONIC(SHRX,1178) +FD_MNEMONIC(SIDT,1179) +FD_MNEMONIC(SKINIT,1180) +FD_MNEMONIC(SLDT,1181) +FD_MNEMONIC(SMSW,1182) +FD_MNEMONIC(SSE_ADDPD,1183) +FD_MNEMONIC(SSE_ADDPS,1184) +FD_MNEMONIC(SSE_ADDSD,1185) +FD_MNEMONIC(SSE_ADDSS,1186) +FD_MNEMONIC(SSE_ADDSUBPD,1187) +FD_MNEMONIC(SSE_ADDSUBPS,1188) +FD_MNEMONIC(SSE_ANDNPD,1189) +FD_MNEMONIC(SSE_ANDNPS,1190) +FD_MNEMONIC(SSE_ANDPD,1191) +FD_MNEMONIC(SSE_ANDPS,1192) +FD_MNEMONIC(SSE_BLENDPD,1193) +FD_MNEMONIC(SSE_BLENDPS,1194) +FD_MNEMONIC(SSE_BLENDVPD,1195) +FD_MNEMONIC(SSE_BLENDVPS,1196) +FD_MNEMONIC(SSE_CMPPD,1197) +FD_MNEMONIC(SSE_CMPPS,1198) +FD_MNEMONIC(SSE_CMPSD,1199) +FD_MNEMONIC(SSE_CMPSS,1200) +FD_MNEMONIC(SSE_COMISD,1201) +FD_MNEMONIC(SSE_COMISS,1202) +FD_MNEMONIC(SSE_CVTDQ2PD,1203) +FD_MNEMONIC(SSE_CVTDQ2PS,1204) +FD_MNEMONIC(SSE_CVTPD2DQ,1205) +FD_MNEMONIC(SSE_CVTPD2PS,1206) +FD_MNEMONIC(SSE_CVTPS2DQ,1207) +FD_MNEMONIC(SSE_CVTPS2PD,1208) +FD_MNEMONIC(SSE_CVTSD2SI,1209) +FD_MNEMONIC(SSE_CVTSD2SS,1210) +FD_MNEMONIC(SSE_CVTSI2SD,1211) +FD_MNEMONIC(SSE_CVTSI2SS,1212) +FD_MNEMONIC(SSE_CVTSS2SD,1213) +FD_MNEMONIC(SSE_CVTSS2SI,1214) +FD_MNEMONIC(SSE_CVTTPD2DQ,1215) +FD_MNEMONIC(SSE_CVTTPS2DQ,1216) +FD_MNEMONIC(SSE_CVTTSD2SI,1217) +FD_MNEMONIC(SSE_CVTTSS2SI,1218) +FD_MNEMONIC(SSE_DIVPD,1219) +FD_MNEMONIC(SSE_DIVPS,1220) +FD_MNEMONIC(SSE_DIVSD,1221) +FD_MNEMONIC(SSE_DIVSS,1222) +FD_MNEMONIC(SSE_DPPD,1223) +FD_MNEMONIC(SSE_DPPS,1224) +FD_MNEMONIC(SSE_EXTRACTPS,1225) +FD_MNEMONIC(SSE_EXTRQ,1226) +FD_MNEMONIC(SSE_HADDPD,1227) +FD_MNEMONIC(SSE_HADDPS,1228) +FD_MNEMONIC(SSE_HSUBPD,1229) +FD_MNEMONIC(SSE_HSUBPS,1230) +FD_MNEMONIC(SSE_INSERTPS,1231) +FD_MNEMONIC(SSE_INSERTQ,1232) +FD_MNEMONIC(SSE_LDDQU,1233) +FD_MNEMONIC(SSE_MASKMOVDQU,1234) +FD_MNEMONIC(SSE_MAXPD,1235) +FD_MNEMONIC(SSE_MAXPS,1236) +FD_MNEMONIC(SSE_MAXSD,1237) +FD_MNEMONIC(SSE_MAXSS,1238) +FD_MNEMONIC(SSE_MINPD,1239) +FD_MNEMONIC(SSE_MINPS,1240) +FD_MNEMONIC(SSE_MINSD,1241) +FD_MNEMONIC(SSE_MINSS,1242) +FD_MNEMONIC(SSE_MOVAPD,1243) +FD_MNEMONIC(SSE_MOVAPS,1244) +FD_MNEMONIC(SSE_MOVD,1245) +FD_MNEMONIC(SSE_MOVDDUP,1246) +FD_MNEMONIC(SSE_MOVDQA,1247) +FD_MNEMONIC(SSE_MOVDQU,1248) +FD_MNEMONIC(SSE_MOVHLPS,1249) +FD_MNEMONIC(SSE_MOVHPD,1250) +FD_MNEMONIC(SSE_MOVHPS,1251) +FD_MNEMONIC(SSE_MOVLHPS,1252) +FD_MNEMONIC(SSE_MOVLPD,1253) +FD_MNEMONIC(SSE_MOVLPS,1254) +FD_MNEMONIC(SSE_MOVMSKPD,1255) +FD_MNEMONIC(SSE_MOVMSKPS,1256) +FD_MNEMONIC(SSE_MOVNTDQ,1257) +FD_MNEMONIC(SSE_MOVNTDQA,1258) +FD_MNEMONIC(SSE_MOVNTPD,1259) +FD_MNEMONIC(SSE_MOVNTPS,1260) +FD_MNEMONIC(SSE_MOVNTSD,1261) +FD_MNEMONIC(SSE_MOVNTSS,1262) +FD_MNEMONIC(SSE_MOVQ,1263) +FD_MNEMONIC(SSE_MOVSD,1264) +FD_MNEMONIC(SSE_MOVSHDUP,1265) +FD_MNEMONIC(SSE_MOVSLDUP,1266) +FD_MNEMONIC(SSE_MOVSS,1267) +FD_MNEMONIC(SSE_MOVUPD,1268) +FD_MNEMONIC(SSE_MOVUPS,1269) +FD_MNEMONIC(SSE_MPSADBW,1270) +FD_MNEMONIC(SSE_MULPD,1271) +FD_MNEMONIC(SSE_MULPS,1272) +FD_MNEMONIC(SSE_MULSD,1273) +FD_MNEMONIC(SSE_MULSS,1274) +FD_MNEMONIC(SSE_ORPD,1275) +FD_MNEMONIC(SSE_ORPS,1276) +FD_MNEMONIC(SSE_PABSB,1277) +FD_MNEMONIC(SSE_PABSD,1278) +FD_MNEMONIC(SSE_PABSW,1279) +FD_MNEMONIC(SSE_PACKSSDW,1280) +FD_MNEMONIC(SSE_PACKSSWB,1281) +FD_MNEMONIC(SSE_PACKUSDW,1282) +FD_MNEMONIC(SSE_PACKUSWB,1283) +FD_MNEMONIC(SSE_PADDB,1284) +FD_MNEMONIC(SSE_PADDD,1285) +FD_MNEMONIC(SSE_PADDQ,1286) +FD_MNEMONIC(SSE_PADDSB,1287) +FD_MNEMONIC(SSE_PADDSW,1288) +FD_MNEMONIC(SSE_PADDUSB,1289) +FD_MNEMONIC(SSE_PADDUSW,1290) +FD_MNEMONIC(SSE_PADDW,1291) +FD_MNEMONIC(SSE_PALIGNR,1292) +FD_MNEMONIC(SSE_PAND,1293) +FD_MNEMONIC(SSE_PANDN,1294) +FD_MNEMONIC(SSE_PAVGB,1295) +FD_MNEMONIC(SSE_PAVGW,1296) +FD_MNEMONIC(SSE_PBLENDVB,1297) +FD_MNEMONIC(SSE_PBLENDW,1298) +FD_MNEMONIC(SSE_PCLMULQDQ,1299) +FD_MNEMONIC(SSE_PCMPEQB,1300) +FD_MNEMONIC(SSE_PCMPEQD,1301) +FD_MNEMONIC(SSE_PCMPEQQ,1302) +FD_MNEMONIC(SSE_PCMPEQW,1303) +FD_MNEMONIC(SSE_PCMPESTRI,1304) +FD_MNEMONIC(SSE_PCMPESTRM,1305) +FD_MNEMONIC(SSE_PCMPGTB,1306) +FD_MNEMONIC(SSE_PCMPGTD,1307) +FD_MNEMONIC(SSE_PCMPGTQ,1308) +FD_MNEMONIC(SSE_PCMPGTW,1309) +FD_MNEMONIC(SSE_PCMPISTRI,1310) +FD_MNEMONIC(SSE_PCMPISTRM,1311) +FD_MNEMONIC(SSE_PEXTRB,1312) +FD_MNEMONIC(SSE_PEXTRD,1313) +FD_MNEMONIC(SSE_PEXTRQ,1314) +FD_MNEMONIC(SSE_PEXTRW,1315) +FD_MNEMONIC(SSE_PHADDD,1316) +FD_MNEMONIC(SSE_PHADDSW,1317) +FD_MNEMONIC(SSE_PHADDW,1318) +FD_MNEMONIC(SSE_PHMINPOSUW,1319) +FD_MNEMONIC(SSE_PHSUBD,1320) +FD_MNEMONIC(SSE_PHSUBSW,1321) +FD_MNEMONIC(SSE_PHSUBW,1322) +FD_MNEMONIC(SSE_PINSRB,1323) +FD_MNEMONIC(SSE_PINSRD,1324) +FD_MNEMONIC(SSE_PINSRQ,1325) +FD_MNEMONIC(SSE_PINSRW,1326) +FD_MNEMONIC(SSE_PMADDUBSW,1327) +FD_MNEMONIC(SSE_PMADDWD,1328) +FD_MNEMONIC(SSE_PMAXSB,1329) +FD_MNEMONIC(SSE_PMAXSD,1330) +FD_MNEMONIC(SSE_PMAXSW,1331) +FD_MNEMONIC(SSE_PMAXUB,1332) +FD_MNEMONIC(SSE_PMAXUD,1333) +FD_MNEMONIC(SSE_PMAXUW,1334) +FD_MNEMONIC(SSE_PMINSB,1335) +FD_MNEMONIC(SSE_PMINSD,1336) +FD_MNEMONIC(SSE_PMINSW,1337) +FD_MNEMONIC(SSE_PMINUB,1338) +FD_MNEMONIC(SSE_PMINUD,1339) +FD_MNEMONIC(SSE_PMINUW,1340) +FD_MNEMONIC(SSE_PMOVMSKB,1341) +FD_MNEMONIC(SSE_PMOVSXBD,1342) +FD_MNEMONIC(SSE_PMOVSXBQ,1343) +FD_MNEMONIC(SSE_PMOVSXBW,1344) +FD_MNEMONIC(SSE_PMOVSXDQ,1345) +FD_MNEMONIC(SSE_PMOVSXWD,1346) +FD_MNEMONIC(SSE_PMOVSXWQ,1347) +FD_MNEMONIC(SSE_PMOVZXBD,1348) +FD_MNEMONIC(SSE_PMOVZXBQ,1349) +FD_MNEMONIC(SSE_PMOVZXBW,1350) +FD_MNEMONIC(SSE_PMOVZXDQ,1351) +FD_MNEMONIC(SSE_PMOVZXWD,1352) +FD_MNEMONIC(SSE_PMOVZXWQ,1353) +FD_MNEMONIC(SSE_PMULDQ,1354) +FD_MNEMONIC(SSE_PMULHRSW,1355) +FD_MNEMONIC(SSE_PMULHUW,1356) +FD_MNEMONIC(SSE_PMULHW,1357) +FD_MNEMONIC(SSE_PMULLD,1358) +FD_MNEMONIC(SSE_PMULLW,1359) +FD_MNEMONIC(SSE_PMULUDQ,1360) +FD_MNEMONIC(SSE_POR,1361) +FD_MNEMONIC(SSE_PSADBW,1362) +FD_MNEMONIC(SSE_PSHUFB,1363) +FD_MNEMONIC(SSE_PSHUFD,1364) +FD_MNEMONIC(SSE_PSHUFHW,1365) +FD_MNEMONIC(SSE_PSHUFLW,1366) +FD_MNEMONIC(SSE_PSIGNB,1367) +FD_MNEMONIC(SSE_PSIGND,1368) +FD_MNEMONIC(SSE_PSIGNW,1369) +FD_MNEMONIC(SSE_PSLLD,1370) +FD_MNEMONIC(SSE_PSLLDQ,1371) +FD_MNEMONIC(SSE_PSLLQ,1372) +FD_MNEMONIC(SSE_PSLLW,1373) +FD_MNEMONIC(SSE_PSRAD,1374) +FD_MNEMONIC(SSE_PSRAW,1375) +FD_MNEMONIC(SSE_PSRLD,1376) +FD_MNEMONIC(SSE_PSRLDQ,1377) +FD_MNEMONIC(SSE_PSRLQ,1378) +FD_MNEMONIC(SSE_PSRLW,1379) +FD_MNEMONIC(SSE_PSUBB,1380) +FD_MNEMONIC(SSE_PSUBD,1381) +FD_MNEMONIC(SSE_PSUBQ,1382) +FD_MNEMONIC(SSE_PSUBSB,1383) +FD_MNEMONIC(SSE_PSUBSW,1384) +FD_MNEMONIC(SSE_PSUBUSB,1385) +FD_MNEMONIC(SSE_PSUBUSW,1386) +FD_MNEMONIC(SSE_PSUBW,1387) +FD_MNEMONIC(SSE_PTEST,1388) +FD_MNEMONIC(SSE_PUNPCKHBW,1389) +FD_MNEMONIC(SSE_PUNPCKHDQ,1390) +FD_MNEMONIC(SSE_PUNPCKHQDQ,1391) +FD_MNEMONIC(SSE_PUNPCKHWD,1392) +FD_MNEMONIC(SSE_PUNPCKLBW,1393) +FD_MNEMONIC(SSE_PUNPCKLDQ,1394) +FD_MNEMONIC(SSE_PUNPCKLQDQ,1395) +FD_MNEMONIC(SSE_PUNPCKLWD,1396) +FD_MNEMONIC(SSE_PXOR,1397) +FD_MNEMONIC(SSE_RCPPS,1398) +FD_MNEMONIC(SSE_RCPSS,1399) +FD_MNEMONIC(SSE_ROUNDPD,1400) +FD_MNEMONIC(SSE_ROUNDPS,1401) +FD_MNEMONIC(SSE_ROUNDSD,1402) +FD_MNEMONIC(SSE_ROUNDSS,1403) +FD_MNEMONIC(SSE_RSQRTPS,1404) +FD_MNEMONIC(SSE_RSQRTSS,1405) +FD_MNEMONIC(SSE_SHUFPD,1406) +FD_MNEMONIC(SSE_SHUFPS,1407) +FD_MNEMONIC(SSE_SQRTPD,1408) +FD_MNEMONIC(SSE_SQRTPS,1409) +FD_MNEMONIC(SSE_SQRTSD,1410) +FD_MNEMONIC(SSE_SQRTSS,1411) +FD_MNEMONIC(SSE_SUBPD,1412) +FD_MNEMONIC(SSE_SUBPS,1413) +FD_MNEMONIC(SSE_SUBSD,1414) +FD_MNEMONIC(SSE_SUBSS,1415) +FD_MNEMONIC(SSE_UCOMISD,1416) +FD_MNEMONIC(SSE_UCOMISS,1417) +FD_MNEMONIC(SSE_UNPCKHPD,1418) +FD_MNEMONIC(SSE_UNPCKHPS,1419) +FD_MNEMONIC(SSE_UNPCKLPD,1420) +FD_MNEMONIC(SSE_UNPCKLPS,1421) +FD_MNEMONIC(SSE_XORPD,1422) +FD_MNEMONIC(SSE_XORPS,1423) +FD_MNEMONIC(STAC,1424) +FD_MNEMONIC(STC,1425) +FD_MNEMONIC(STD,1426) +FD_MNEMONIC(STGI,1427) +FD_MNEMONIC(STI,1428) +FD_MNEMONIC(STMXCSR,1429) +FD_MNEMONIC(STOS,1430) +FD_MNEMONIC(STR,1431) +FD_MNEMONIC(STTILECFG,1432) +FD_MNEMONIC(STUI,1433) +FD_MNEMONIC(SUB,1434) +FD_MNEMONIC(SWAPGS,1435) +FD_MNEMONIC(SYSCALL,1436) +FD_MNEMONIC(SYSENTER,1437) +FD_MNEMONIC(SYSEXIT,1438) +FD_MNEMONIC(SYSRET,1439) +FD_MNEMONIC(TCMMIMFP16PS,1440) +FD_MNEMONIC(TCMMRLFP16PS,1441) +FD_MNEMONIC(TDCALL,1442) +FD_MNEMONIC(TDPBF16PS,1443) +FD_MNEMONIC(TDPBSSD,1444) +FD_MNEMONIC(TDPBSUD,1445) +FD_MNEMONIC(TDPBUSD,1446) +FD_MNEMONIC(TDPBUUD,1447) +FD_MNEMONIC(TDPFP16PS,1448) +FD_MNEMONIC(TEST,1449) +FD_MNEMONIC(TESTUI,1450) +FD_MNEMONIC(TILELOADD,1451) +FD_MNEMONIC(TILELOADDT1,1452) +FD_MNEMONIC(TILERELEASE,1453) +FD_MNEMONIC(TILESTORED,1454) +FD_MNEMONIC(TILEZERO,1455) +FD_MNEMONIC(TLBSYNC,1456) +FD_MNEMONIC(TPAUSE,1457) +FD_MNEMONIC(TZCNT,1458) +FD_MNEMONIC(UD0,1459) +FD_MNEMONIC(UD1,1460) +FD_MNEMONIC(UD2,1461) +FD_MNEMONIC(UIRET,1462) +FD_MNEMONIC(UMONITOR,1463) +FD_MNEMONIC(UMWAIT,1464) +FD_MNEMONIC(URDMSR,1465) +FD_MNEMONIC(UWRMSR,1466) +FD_MNEMONIC(VADDPD,1467) +FD_MNEMONIC(VADDPS,1468) +FD_MNEMONIC(VADDSD,1469) +FD_MNEMONIC(VADDSS,1470) +FD_MNEMONIC(VADDSUBPD,1471) +FD_MNEMONIC(VADDSUBPS,1472) +FD_MNEMONIC(VAESDEC,1473) +FD_MNEMONIC(VAESDECLAST,1474) +FD_MNEMONIC(VAESENC,1475) +FD_MNEMONIC(VAESENCLAST,1476) +FD_MNEMONIC(VAESIMC,1477) +FD_MNEMONIC(VAESKEYGENASSIST,1478) +FD_MNEMONIC(VANDNPD,1479) +FD_MNEMONIC(VANDNPS,1480) +FD_MNEMONIC(VANDPD,1481) +FD_MNEMONIC(VANDPS,1482) +FD_MNEMONIC(VBCSTNEBF162PS,1483) +FD_MNEMONIC(VBCSTNESH2PS,1484) +FD_MNEMONIC(VBLENDPD,1485) +FD_MNEMONIC(VBLENDPS,1486) +FD_MNEMONIC(VBLENDVPD,1487) +FD_MNEMONIC(VBLENDVPS,1488) +FD_MNEMONIC(VBROADCASTF128,1489) +FD_MNEMONIC(VBROADCASTI128,1490) +FD_MNEMONIC(VBROADCASTSD,1491) +FD_MNEMONIC(VBROADCASTSS,1492) +FD_MNEMONIC(VCMPPD,1493) +FD_MNEMONIC(VCMPPS,1494) +FD_MNEMONIC(VCMPSD,1495) +FD_MNEMONIC(VCMPSS,1496) +FD_MNEMONIC(VCOMISD,1497) +FD_MNEMONIC(VCOMISS,1498) +FD_MNEMONIC(VCVTDQ2PD,1499) +FD_MNEMONIC(VCVTDQ2PS,1500) +FD_MNEMONIC(VCVTNEEBF162PS,1501) +FD_MNEMONIC(VCVTNEEPH2PS,1502) +FD_MNEMONIC(VCVTNEOBF162PS,1503) +FD_MNEMONIC(VCVTNEOPH2PS,1504) +FD_MNEMONIC(VCVTNEPS2BF16,1505) +FD_MNEMONIC(VCVTPD2DQ,1506) +FD_MNEMONIC(VCVTPD2PS,1507) +FD_MNEMONIC(VCVTPH2PS,1508) +FD_MNEMONIC(VCVTPS2DQ,1509) +FD_MNEMONIC(VCVTPS2PD,1510) +FD_MNEMONIC(VCVTPS2PH,1511) +FD_MNEMONIC(VCVTSD2SI,1512) +FD_MNEMONIC(VCVTSD2SS,1513) +FD_MNEMONIC(VCVTSI2SD,1514) +FD_MNEMONIC(VCVTSI2SS,1515) +FD_MNEMONIC(VCVTSS2SD,1516) +FD_MNEMONIC(VCVTSS2SI,1517) +FD_MNEMONIC(VCVTTPD2DQ,1518) +FD_MNEMONIC(VCVTTPS2DQ,1519) +FD_MNEMONIC(VCVTTSD2SI,1520) +FD_MNEMONIC(VCVTTSS2SI,1521) +FD_MNEMONIC(VDIVPD,1522) +FD_MNEMONIC(VDIVPS,1523) +FD_MNEMONIC(VDIVSD,1524) +FD_MNEMONIC(VDIVSS,1525) +FD_MNEMONIC(VDPPD,1526) +FD_MNEMONIC(VDPPS,1527) +FD_MNEMONIC(VERR,1528) +FD_MNEMONIC(VERW,1529) +FD_MNEMONIC(VEXTRACTF128,1530) +FD_MNEMONIC(VEXTRACTI128,1531) +FD_MNEMONIC(VEXTRACTPS,1532) +FD_MNEMONIC(VFMADD132PD,1533) +FD_MNEMONIC(VFMADD132PS,1534) +FD_MNEMONIC(VFMADD132SD,1535) +FD_MNEMONIC(VFMADD132SS,1536) +FD_MNEMONIC(VFMADD213PD,1537) +FD_MNEMONIC(VFMADD213PS,1538) +FD_MNEMONIC(VFMADD213SD,1539) +FD_MNEMONIC(VFMADD213SS,1540) +FD_MNEMONIC(VFMADD231PD,1541) +FD_MNEMONIC(VFMADD231PS,1542) +FD_MNEMONIC(VFMADD231SD,1543) +FD_MNEMONIC(VFMADD231SS,1544) +FD_MNEMONIC(VFMADDSUB132PD,1545) +FD_MNEMONIC(VFMADDSUB132PS,1546) +FD_MNEMONIC(VFMADDSUB213PD,1547) +FD_MNEMONIC(VFMADDSUB213PS,1548) +FD_MNEMONIC(VFMADDSUB231PD,1549) +FD_MNEMONIC(VFMADDSUB231PS,1550) +FD_MNEMONIC(VFMSUB132PD,1551) +FD_MNEMONIC(VFMSUB132PS,1552) +FD_MNEMONIC(VFMSUB132SD,1553) +FD_MNEMONIC(VFMSUB132SS,1554) +FD_MNEMONIC(VFMSUB213PD,1555) +FD_MNEMONIC(VFMSUB213PS,1556) +FD_MNEMONIC(VFMSUB213SD,1557) +FD_MNEMONIC(VFMSUB213SS,1558) +FD_MNEMONIC(VFMSUB231PD,1559) +FD_MNEMONIC(VFMSUB231PS,1560) +FD_MNEMONIC(VFMSUB231SD,1561) +FD_MNEMONIC(VFMSUB231SS,1562) +FD_MNEMONIC(VFMSUBADD132PD,1563) +FD_MNEMONIC(VFMSUBADD132PS,1564) +FD_MNEMONIC(VFMSUBADD213PD,1565) +FD_MNEMONIC(VFMSUBADD213PS,1566) +FD_MNEMONIC(VFMSUBADD231PD,1567) +FD_MNEMONIC(VFMSUBADD231PS,1568) +FD_MNEMONIC(VFNMADD132PD,1569) +FD_MNEMONIC(VFNMADD132PS,1570) +FD_MNEMONIC(VFNMADD132SD,1571) +FD_MNEMONIC(VFNMADD132SS,1572) +FD_MNEMONIC(VFNMADD213PD,1573) +FD_MNEMONIC(VFNMADD213PS,1574) +FD_MNEMONIC(VFNMADD213SD,1575) +FD_MNEMONIC(VFNMADD213SS,1576) +FD_MNEMONIC(VFNMADD231PD,1577) +FD_MNEMONIC(VFNMADD231PS,1578) +FD_MNEMONIC(VFNMADD231SD,1579) +FD_MNEMONIC(VFNMADD231SS,1580) +FD_MNEMONIC(VFNMSUB132PD,1581) +FD_MNEMONIC(VFNMSUB132PS,1582) +FD_MNEMONIC(VFNMSUB132SD,1583) +FD_MNEMONIC(VFNMSUB132SS,1584) +FD_MNEMONIC(VFNMSUB213PD,1585) +FD_MNEMONIC(VFNMSUB213PS,1586) +FD_MNEMONIC(VFNMSUB213SD,1587) +FD_MNEMONIC(VFNMSUB213SS,1588) +FD_MNEMONIC(VFNMSUB231PD,1589) +FD_MNEMONIC(VFNMSUB231PS,1590) +FD_MNEMONIC(VFNMSUB231SD,1591) +FD_MNEMONIC(VFNMSUB231SS,1592) +FD_MNEMONIC(VGATHERDPD,1593) +FD_MNEMONIC(VGATHERDPS,1594) +FD_MNEMONIC(VGATHERQPD,1595) +FD_MNEMONIC(VGATHERQPS,1596) +FD_MNEMONIC(VGF2P8AFFINEINVQB,1597) +FD_MNEMONIC(VGF2P8AFFINEQB,1598) +FD_MNEMONIC(VGF2P8MULB,1599) +FD_MNEMONIC(VHADDPD,1600) +FD_MNEMONIC(VHADDPS,1601) +FD_MNEMONIC(VHSUBPD,1602) +FD_MNEMONIC(VHSUBPS,1603) +FD_MNEMONIC(VINSERTF128,1604) +FD_MNEMONIC(VINSERTI128,1605) +FD_MNEMONIC(VINSERTPS,1606) +FD_MNEMONIC(VLDDQU,1607) +FD_MNEMONIC(VLDMXCSR,1608) +FD_MNEMONIC(VMASKMOVDQU,1609) +FD_MNEMONIC(VMASKMOVPD,1610) +FD_MNEMONIC(VMASKMOVPS,1611) +FD_MNEMONIC(VMAXPD,1612) +FD_MNEMONIC(VMAXPS,1613) +FD_MNEMONIC(VMAXSD,1614) +FD_MNEMONIC(VMAXSS,1615) +FD_MNEMONIC(VMCALL,1616) +FD_MNEMONIC(VMCLEAR,1617) +FD_MNEMONIC(VMFUNC,1618) +FD_MNEMONIC(VMGEXIT,1619) +FD_MNEMONIC(VMINPD,1620) +FD_MNEMONIC(VMINPS,1621) +FD_MNEMONIC(VMINSD,1622) +FD_MNEMONIC(VMINSS,1623) +FD_MNEMONIC(VMLAUNCH,1624) +FD_MNEMONIC(VMLOAD,1625) +FD_MNEMONIC(VMMCALL,1626) +FD_MNEMONIC(VMOVAPD,1627) +FD_MNEMONIC(VMOVAPS,1628) +FD_MNEMONIC(VMOVD,1629) +FD_MNEMONIC(VMOVDDUP,1630) +FD_MNEMONIC(VMOVDQA,1631) +FD_MNEMONIC(VMOVDQU,1632) +FD_MNEMONIC(VMOVHLPS,1633) +FD_MNEMONIC(VMOVHPD,1634) +FD_MNEMONIC(VMOVHPS,1635) +FD_MNEMONIC(VMOVLHPS,1636) +FD_MNEMONIC(VMOVLPD,1637) +FD_MNEMONIC(VMOVLPS,1638) +FD_MNEMONIC(VMOVMSKPD,1639) +FD_MNEMONIC(VMOVMSKPS,1640) +FD_MNEMONIC(VMOVNTDQ,1641) +FD_MNEMONIC(VMOVNTDQA,1642) +FD_MNEMONIC(VMOVNTPD,1643) +FD_MNEMONIC(VMOVNTPS,1644) +FD_MNEMONIC(VMOVQ,1645) +FD_MNEMONIC(VMOVSD,1646) +FD_MNEMONIC(VMOVSHDUP,1647) +FD_MNEMONIC(VMOVSLDUP,1648) +FD_MNEMONIC(VMOVSS,1649) +FD_MNEMONIC(VMOVUPD,1650) +FD_MNEMONIC(VMOVUPS,1651) +FD_MNEMONIC(VMPSADBW,1652) +FD_MNEMONIC(VMPTRLD,1653) +FD_MNEMONIC(VMPTRST,1654) +FD_MNEMONIC(VMREAD,1655) +FD_MNEMONIC(VMRESUME,1656) +FD_MNEMONIC(VMRUN,1657) +FD_MNEMONIC(VMSAVE,1658) +FD_MNEMONIC(VMULPD,1659) +FD_MNEMONIC(VMULPS,1660) +FD_MNEMONIC(VMULSD,1661) +FD_MNEMONIC(VMULSS,1662) +FD_MNEMONIC(VMWRITE,1663) +FD_MNEMONIC(VMXOFF,1664) +FD_MNEMONIC(VMXON,1665) +FD_MNEMONIC(VORPD,1666) +FD_MNEMONIC(VORPS,1667) +FD_MNEMONIC(VPABSB,1668) +FD_MNEMONIC(VPABSD,1669) +FD_MNEMONIC(VPABSW,1670) +FD_MNEMONIC(VPACKSSDW,1671) +FD_MNEMONIC(VPACKSSWB,1672) +FD_MNEMONIC(VPACKUSDW,1673) +FD_MNEMONIC(VPACKUSWB,1674) +FD_MNEMONIC(VPADDB,1675) +FD_MNEMONIC(VPADDD,1676) +FD_MNEMONIC(VPADDQ,1677) +FD_MNEMONIC(VPADDSB,1678) +FD_MNEMONIC(VPADDSW,1679) +FD_MNEMONIC(VPADDUSB,1680) +FD_MNEMONIC(VPADDUSW,1681) +FD_MNEMONIC(VPADDW,1682) +FD_MNEMONIC(VPALIGNR,1683) +FD_MNEMONIC(VPAND,1684) +FD_MNEMONIC(VPANDN,1685) +FD_MNEMONIC(VPAVGB,1686) +FD_MNEMONIC(VPAVGW,1687) +FD_MNEMONIC(VPBLENDD,1688) +FD_MNEMONIC(VPBLENDVB,1689) +FD_MNEMONIC(VPBLENDW,1690) +FD_MNEMONIC(VPBROADCASTB,1691) +FD_MNEMONIC(VPBROADCASTD,1692) +FD_MNEMONIC(VPBROADCASTQ,1693) +FD_MNEMONIC(VPBROADCASTW,1694) +FD_MNEMONIC(VPCLMULQDQ,1695) +FD_MNEMONIC(VPCMPEQB,1696) +FD_MNEMONIC(VPCMPEQD,1697) +FD_MNEMONIC(VPCMPEQQ,1698) +FD_MNEMONIC(VPCMPEQW,1699) +FD_MNEMONIC(VPCMPESTRI,1700) +FD_MNEMONIC(VPCMPESTRM,1701) +FD_MNEMONIC(VPCMPGTB,1702) +FD_MNEMONIC(VPCMPGTD,1703) +FD_MNEMONIC(VPCMPGTQ,1704) +FD_MNEMONIC(VPCMPGTW,1705) +FD_MNEMONIC(VPCMPISTRI,1706) +FD_MNEMONIC(VPCMPISTRM,1707) +FD_MNEMONIC(VPDPBSSD,1708) +FD_MNEMONIC(VPDPBSSDS,1709) +FD_MNEMONIC(VPDPBSUD,1710) +FD_MNEMONIC(VPDPBSUDS,1711) +FD_MNEMONIC(VPDPBUSD,1712) +FD_MNEMONIC(VPDPBUSDS,1713) +FD_MNEMONIC(VPDPBUUD,1714) +FD_MNEMONIC(VPDPBUUDS,1715) +FD_MNEMONIC(VPDPWSSD,1716) +FD_MNEMONIC(VPDPWSSDS,1717) +FD_MNEMONIC(VPERM2F128,1718) +FD_MNEMONIC(VPERM2I128,1719) +FD_MNEMONIC(VPERMD,1720) +FD_MNEMONIC(VPERMILPD,1721) +FD_MNEMONIC(VPERMILPS,1722) +FD_MNEMONIC(VPERMPD,1723) +FD_MNEMONIC(VPERMPS,1724) +FD_MNEMONIC(VPERMQ,1725) +FD_MNEMONIC(VPEXTRB,1726) +FD_MNEMONIC(VPEXTRD,1727) +FD_MNEMONIC(VPEXTRQ,1728) +FD_MNEMONIC(VPEXTRW,1729) +FD_MNEMONIC(VPGATHERDD,1730) +FD_MNEMONIC(VPGATHERDQ,1731) +FD_MNEMONIC(VPGATHERQD,1732) +FD_MNEMONIC(VPGATHERQQ,1733) +FD_MNEMONIC(VPHADDD,1734) +FD_MNEMONIC(VPHADDSW,1735) +FD_MNEMONIC(VPHADDW,1736) +FD_MNEMONIC(VPHMINPOSUW,1737) +FD_MNEMONIC(VPHSUBD,1738) +FD_MNEMONIC(VPHSUBSW,1739) +FD_MNEMONIC(VPHSUBW,1740) +FD_MNEMONIC(VPINSRB,1741) +FD_MNEMONIC(VPINSRD,1742) +FD_MNEMONIC(VPINSRQ,1743) +FD_MNEMONIC(VPINSRW,1744) +FD_MNEMONIC(VPMADD52HUQ,1745) +FD_MNEMONIC(VPMADD52LUQ,1746) +FD_MNEMONIC(VPMADDUBSW,1747) +FD_MNEMONIC(VPMADDWD,1748) +FD_MNEMONIC(VPMASKMOVD,1749) +FD_MNEMONIC(VPMASKMOVQ,1750) +FD_MNEMONIC(VPMAXSB,1751) +FD_MNEMONIC(VPMAXSD,1752) +FD_MNEMONIC(VPMAXSW,1753) +FD_MNEMONIC(VPMAXUB,1754) +FD_MNEMONIC(VPMAXUD,1755) +FD_MNEMONIC(VPMAXUW,1756) +FD_MNEMONIC(VPMINSB,1757) +FD_MNEMONIC(VPMINSD,1758) +FD_MNEMONIC(VPMINSW,1759) +FD_MNEMONIC(VPMINUB,1760) +FD_MNEMONIC(VPMINUD,1761) +FD_MNEMONIC(VPMINUW,1762) +FD_MNEMONIC(VPMOVMSKB,1763) +FD_MNEMONIC(VPMOVSXBD,1764) +FD_MNEMONIC(VPMOVSXBQ,1765) +FD_MNEMONIC(VPMOVSXBW,1766) +FD_MNEMONIC(VPMOVSXDQ,1767) +FD_MNEMONIC(VPMOVSXWD,1768) +FD_MNEMONIC(VPMOVSXWQ,1769) +FD_MNEMONIC(VPMOVZXBD,1770) +FD_MNEMONIC(VPMOVZXBQ,1771) +FD_MNEMONIC(VPMOVZXBW,1772) +FD_MNEMONIC(VPMOVZXDQ,1773) +FD_MNEMONIC(VPMOVZXWD,1774) +FD_MNEMONIC(VPMOVZXWQ,1775) +FD_MNEMONIC(VPMULDQ,1776) +FD_MNEMONIC(VPMULHRSW,1777) +FD_MNEMONIC(VPMULHUW,1778) +FD_MNEMONIC(VPMULHW,1779) +FD_MNEMONIC(VPMULLD,1780) +FD_MNEMONIC(VPMULLW,1781) +FD_MNEMONIC(VPMULUDQ,1782) +FD_MNEMONIC(VPOR,1783) +FD_MNEMONIC(VPSADBW,1784) +FD_MNEMONIC(VPSHUFB,1785) +FD_MNEMONIC(VPSHUFD,1786) +FD_MNEMONIC(VPSHUFHW,1787) +FD_MNEMONIC(VPSHUFLW,1788) +FD_MNEMONIC(VPSIGNB,1789) +FD_MNEMONIC(VPSIGND,1790) +FD_MNEMONIC(VPSIGNW,1791) +FD_MNEMONIC(VPSLLD,1792) +FD_MNEMONIC(VPSLLDQ,1793) +FD_MNEMONIC(VPSLLQ,1794) +FD_MNEMONIC(VPSLLVD,1795) +FD_MNEMONIC(VPSLLVQ,1796) +FD_MNEMONIC(VPSLLW,1797) +FD_MNEMONIC(VPSRAD,1798) +FD_MNEMONIC(VPSRAVD,1799) +FD_MNEMONIC(VPSRAW,1800) +FD_MNEMONIC(VPSRLD,1801) +FD_MNEMONIC(VPSRLDQ,1802) +FD_MNEMONIC(VPSRLQ,1803) +FD_MNEMONIC(VPSRLVD,1804) +FD_MNEMONIC(VPSRLVQ,1805) +FD_MNEMONIC(VPSRLW,1806) +FD_MNEMONIC(VPSUBB,1807) +FD_MNEMONIC(VPSUBD,1808) +FD_MNEMONIC(VPSUBQ,1809) +FD_MNEMONIC(VPSUBSB,1810) +FD_MNEMONIC(VPSUBSW,1811) +FD_MNEMONIC(VPSUBUSB,1812) +FD_MNEMONIC(VPSUBUSW,1813) +FD_MNEMONIC(VPSUBW,1814) +FD_MNEMONIC(VPTEST,1815) +FD_MNEMONIC(VPUNPCKHBW,1816) +FD_MNEMONIC(VPUNPCKHDQ,1817) +FD_MNEMONIC(VPUNPCKHQDQ,1818) +FD_MNEMONIC(VPUNPCKHWD,1819) +FD_MNEMONIC(VPUNPCKLBW,1820) +FD_MNEMONIC(VPUNPCKLDQ,1821) +FD_MNEMONIC(VPUNPCKLQDQ,1822) +FD_MNEMONIC(VPUNPCKLWD,1823) +FD_MNEMONIC(VPXOR,1824) +FD_MNEMONIC(VRCPPS,1825) +FD_MNEMONIC(VRCPSS,1826) +FD_MNEMONIC(VROUNDPD,1827) +FD_MNEMONIC(VROUNDPS,1828) +FD_MNEMONIC(VROUNDSD,1829) +FD_MNEMONIC(VROUNDSS,1830) +FD_MNEMONIC(VRSQRTPS,1831) +FD_MNEMONIC(VRSQRTSS,1832) +FD_MNEMONIC(VSHUFPD,1833) +FD_MNEMONIC(VSHUFPS,1834) +FD_MNEMONIC(VSM4KEY4,1835) +FD_MNEMONIC(VSM4RNDS4,1836) +FD_MNEMONIC(VSQRTPD,1837) +FD_MNEMONIC(VSQRTPS,1838) +FD_MNEMONIC(VSQRTSD,1839) +FD_MNEMONIC(VSQRTSS,1840) +FD_MNEMONIC(VSTMXCSR,1841) +FD_MNEMONIC(VSUBPD,1842) +FD_MNEMONIC(VSUBPS,1843) +FD_MNEMONIC(VSUBSD,1844) +FD_MNEMONIC(VSUBSS,1845) +FD_MNEMONIC(VTESTPD,1846) +FD_MNEMONIC(VTESTPS,1847) +FD_MNEMONIC(VUCOMISD,1848) +FD_MNEMONIC(VUCOMISS,1849) +FD_MNEMONIC(VUNPCKHPD,1850) +FD_MNEMONIC(VUNPCKHPS,1851) +FD_MNEMONIC(VUNPCKLPD,1852) +FD_MNEMONIC(VUNPCKLPS,1853) +FD_MNEMONIC(VXORPD,1854) +FD_MNEMONIC(VXORPS,1855) +FD_MNEMONIC(VZEROALL,1856) +FD_MNEMONIC(VZEROUPPER,1857) +FD_MNEMONIC(WBINVD,1858) +FD_MNEMONIC(WBNOINVD,1859) +FD_MNEMONIC(WRFSBASE,1860) +FD_MNEMONIC(WRGSBASE,1861) +FD_MNEMONIC(WRMSR,1862) +FD_MNEMONIC(WRMSRLIST,1863) +FD_MNEMONIC(WRMSRNS,1864) +FD_MNEMONIC(WRPKRU,1865) +FD_MNEMONIC(WRSS,1866) +FD_MNEMONIC(WRUSS,1867) +FD_MNEMONIC(XABORT,1868) +FD_MNEMONIC(XADD,1869) +FD_MNEMONIC(XBEGIN,1870) +FD_MNEMONIC(XCHG,1871) +FD_MNEMONIC(XCHG_NOP,1872) +FD_MNEMONIC(XEND,1873) +FD_MNEMONIC(XGETBV,1874) +FD_MNEMONIC(XLATB,1875) +FD_MNEMONIC(XOR,1876) +FD_MNEMONIC(XRESLDTRK,1877) +FD_MNEMONIC(XRSTOR,1878) +FD_MNEMONIC(XRSTORS,1879) +FD_MNEMONIC(XSAVE,1880) +FD_MNEMONIC(XSAVEC,1881) +FD_MNEMONIC(XSAVEOPT,1882) +FD_MNEMONIC(XSAVES,1883) +FD_MNEMONIC(XSETBV,1884) +FD_MNEMONIC(XSTORE,1885) +FD_MNEMONIC(XSUSLDTRK,1886) +FD_MNEMONIC(XTEST,1887) diff --git a/third_party/fadec/fadec-enc.h b/third_party/fadec/fadec-enc.h new file mode 100644 index 0000000..5505ed3 --- /dev/null +++ b/third_party/fadec/fadec-enc.h @@ -0,0 +1,113 @@ + +#ifndef FD_FADEC_ENC_H_ +#define FD_FADEC_ENC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + FE_AX = 0x100, FE_CX, FE_DX, FE_BX, FE_SP, FE_BP, FE_SI, FE_DI, + FE_R8, FE_R9, FE_R10, FE_R11, FE_R12, FE_R13, FE_R14, FE_R15, + FE_IP = 0x120, + FE_AH = 0x204, FE_CH, FE_DH, FE_BH, + FE_ES = 0x300, FE_CS, FE_SS, FE_DS, FE_FS, FE_GS, + FE_ST0 = 0x400, FE_ST1, FE_ST2, FE_ST3, FE_ST4, FE_ST5, FE_ST6, FE_ST7, + FE_MM0 = 0x500, FE_MM1, FE_MM2, FE_MM3, FE_MM4, FE_MM5, FE_MM6, FE_MM7, + FE_XMM0 = 0x600, FE_XMM1, FE_XMM2, FE_XMM3, FE_XMM4, FE_XMM5, FE_XMM6, FE_XMM7, + FE_XMM8, FE_XMM9, FE_XMM10, FE_XMM11, FE_XMM12, FE_XMM13, FE_XMM14, FE_XMM15, + FE_XMM16, FE_XMM17, FE_XMM18, FE_XMM19, FE_XMM20, FE_XMM21, FE_XMM22, FE_XMM23, + FE_XMM24, FE_XMM25, FE_XMM26, FE_XMM27, FE_XMM28, FE_XMM29, FE_XMM30, FE_XMM31, + FE_K0 = 0x700, FE_K1, FE_K2, FE_K3, FE_K4, FE_K5, FE_K6, FE_K7, + FE_TMM0 = 0x800, FE_TMM1, FE_TMM2, FE_TMM3, FE_TMM4, FE_TMM5, FE_TMM6, FE_TMM7, +} FeReg; + +typedef int64_t FeOp; + +/** Construct a memory operand. Unused parts can be set to 0 and will be + * ignored. FE_IP can be used as base register, in which case the offset is + * interpreted as the offset from the /current/ position -- the size of the + * encoded instruction will be subtracted during encoding. scale must be 1, 2, + * 4, or 8; but is ignored if idx == 0. **/ +#define FE_MEM(base,sc,idx,off) (INT64_MIN | ((int64_t) ((base) & 0xfff) << 32) | ((int64_t) ((idx) & 0xfff) << 44) | ((int64_t) ((sc) & 0xf) << 56) | ((off) & 0xffffffff)) +#define FE_NOREG ((FeReg) 0) + +/** Add segment override prefix. This may or may not generate prefixes for the + * ignored prefixes ES/CS/DS/SS in 64-bit mode. **/ +#define FE_SEG(seg) ((uint64_t) (((seg) & 0x7) + 1) << 29) +/** Do not use. **/ +#define FE_SEG_MASK 0xe0000000 +/** Overrides address size. **/ +#define FE_ADDR32 0x10000000 +/** Used together with a RIP-relative (conditional) jump, this will force the + * use of the encoding with the largest distance. Useful for reserving a jump + * when the target offset is still unknown; if the jump is re-encoded later on, + * FE_JMPL must be specified there, too, so that the encoding lengths match. **/ +#define FE_JMPL 0x100000000 +#define FE_MASK(kreg) ((uint64_t) ((kreg) & 0x7) << 33) +#define FE_RC_RN 0x0000000 +#define FE_RC_RD 0x0800000 +#define FE_RC_RU 0x1000000 +#define FE_RC_RZ 0x1800000 + +enum { + FE_CC_O = 0x0, + FE_CC_NO = 0x1, + FE_CC_C = 0x2, + FE_CC_B = FE_CC_C, + FE_CC_NAE = FE_CC_C, + FE_CC_NC = 0x3, + FE_CC_AE = FE_CC_NC, + FE_CC_NB = FE_CC_NC, + FE_CC_Z = 0x4, + FE_CC_E = FE_CC_Z, + FE_CC_NZ = 0x5, + FE_CC_NE = FE_CC_NZ, + FE_CC_BE = 0x6, + FE_CC_NA = FE_CC_BE, + FE_CC_A = 0x7, + FE_CC_NBE = FE_CC_A, + FE_CC_S = 0x8, + FE_CC_NS = 0x9, + FE_CC_P = 0xa, + FE_CC_PE = FE_CC_P, + FE_CC_NP = 0xb, + FE_CC_PO = FE_CC_NP, + FE_CC_L = 0xc, + FE_CC_NGE = FE_CC_L, + FE_CC_GE = 0xd, + FE_CC_NL = FE_CC_GE, + FE_CC_LE = 0xe, + FE_CC_NG = FE_CC_LE, + FE_CC_G = 0xf, + FE_CC_NLE = FE_CC_G, +}; + +#include + +/** Do not use. **/ +#define fe_enc64_1(buf, mnem, op0, op1, op2, op3, ...) fe_enc64_impl(buf, mnem, op0, op1, op2, op3) +/** Encode a single instruction for 64-bit mode. + * \param buf Pointer to the buffer for instruction bytes, must have a size of + * 15 bytes. The pointer is advanced by the number of bytes used for + * encoding the specified instruction. + * \param mnem Mnemonic, optionally or-ed with FE_SEG(), FE_ADDR32, or FE_JMPL. + * \param operands... Instruction operands. Immediate operands are passed as + * plain value; register operands using the FeReg enum; memory operands + * using FE_MEM(); and offset operands for RIP-relative jumps/calls are + * specified as _address in buf_, e.g. (intptr_t) jmptgt, the address of + * buf and the size of the encoded instruction are subtracted internally. + * \return Zero for success or a negative value in case of an error. + **/ +#define fe_enc64(buf, ...) fe_enc64_1(buf, __VA_ARGS__, 0, 0, 0, 0, 0) +/** Do not use. **/ +int fe_enc64_impl(uint8_t** buf, uint64_t mnem, FeOp op0, FeOp op1, FeOp op2, FeOp op3); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/third_party/fadec/fadec-enc2.h b/third_party/fadec/fadec-enc2.h new file mode 100644 index 0000000..1f76311 --- /dev/null +++ b/third_party/fadec/fadec-enc2.h @@ -0,0 +1,226 @@ + +#ifndef FD_FADEC_ENC2_H_ +#define FD_FADEC_ENC2_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +#define FE_STRUCT(name) name +#else +#define FE_STRUCT(name) (name) +#endif + +// Flags +#define FE_JMPL 0x8 +#define FE_ADDR32 0x10 +#define FE_SEG_MASK 0x7 +#define FE_SEG(seg) (((seg).idx + 1) & FE_SEG_MASK) +#define FE_RC_MASK 0x60 +#define FE_RC_RN 0x00 +#define FE_RC_RD 0x20 +#define FE_RC_RU 0x40 +#define FE_RC_RZ 0x60 + +// Condition codes +typedef enum FeCond { + FE_CC_O = 0x00000, + FE_CC_NO = 0x10000, + FE_CC_C = 0x20000, + FE_CC_B = FE_CC_C, + FE_CC_NAE = FE_CC_C, + FE_CC_NC = 0x30000, + FE_CC_AE = FE_CC_NC, + FE_CC_NB = FE_CC_NC, + FE_CC_Z = 0x40000, + FE_CC_E = FE_CC_Z, + FE_CC_NZ = 0x50000, + FE_CC_NE = FE_CC_NZ, + FE_CC_BE = 0x60000, + FE_CC_NA = FE_CC_BE, + FE_CC_A = 0x70000, + FE_CC_NBE = FE_CC_A, + FE_CC_S = 0x80000, + FE_CC_NS = 0x90000, + FE_CC_P = 0xa0000, + FE_CC_PE = FE_CC_P, + FE_CC_NP = 0xb0000, + FE_CC_PO = FE_CC_NP, + FE_CC_L = 0xc0000, + FE_CC_NGE = FE_CC_L, + FE_CC_GE = 0xd0000, + FE_CC_NL = FE_CC_GE, + FE_CC_LE = 0xe0000, + FE_CC_NG = FE_CC_LE, + FE_CC_G = 0xf0000, + FE_CC_NLE = FE_CC_G, + + FE_CC_MASK = 0xf0000 +} FeCond; + +typedef struct FeRegGP { unsigned char idx; } FeRegGP; +#define FE_GP(idx) (FE_STRUCT(FeRegGP) { idx }) +#define FE_AX FE_GP(0) +#define FE_CX FE_GP(1) +#define FE_DX FE_GP(2) +#define FE_BX FE_GP(3) +#define FE_SP FE_GP(4) +#define FE_BP FE_GP(5) +#define FE_SI FE_GP(6) +#define FE_DI FE_GP(7) +#define FE_R8 FE_GP(8) +#define FE_R9 FE_GP(9) +#define FE_R10 FE_GP(10) +#define FE_R11 FE_GP(11) +#define FE_R12 FE_GP(12) +#define FE_R13 FE_GP(13) +#define FE_R14 FE_GP(14) +#define FE_R15 FE_GP(15) +#define FE_IP FE_GP(0x20) +#define FE_NOREG FE_GP(0x80) +typedef struct FeRegGPH { unsigned char idx; } FeRegGPH; +#define FE_GPH(idx) (FE_STRUCT(FeRegGPH) { idx }) +#define FE_AH FE_GPH(4) +#define FE_CH FE_GPH(5) +#define FE_DH FE_GPH(6) +#define FE_BH FE_GPH(7) +typedef struct FeRegSREG { unsigned char idx; } FeRegSREG; +#define FE_SREG(idx) (FE_STRUCT(FeRegSREG) { idx }) +#define FE_ES FE_SREG(0) +#define FE_CS FE_SREG(1) +#define FE_SS FE_SREG(2) +#define FE_DS FE_SREG(3) +#define FE_FS FE_SREG(4) +#define FE_GS FE_SREG(5) +typedef struct FeRegST { unsigned char idx; } FeRegST; +#define FE_ST(idx) (FE_STRUCT(FeRegST) { idx }) +#define FE_ST0 FE_ST(0) +#define FE_ST1 FE_ST(1) +#define FE_ST2 FE_ST(2) +#define FE_ST3 FE_ST(3) +#define FE_ST4 FE_ST(4) +#define FE_ST5 FE_ST(5) +#define FE_ST6 FE_ST(6) +#define FE_ST7 FE_ST(7) +typedef struct FeRegMM { unsigned char idx; } FeRegMM; +#define FE_MM(idx) (FE_STRUCT(FeRegMM) { idx }) +#define FE_MM0 FE_MM(0) +#define FE_MM1 FE_MM(1) +#define FE_MM2 FE_MM(2) +#define FE_MM3 FE_MM(3) +#define FE_MM4 FE_MM(4) +#define FE_MM5 FE_MM(5) +#define FE_MM6 FE_MM(6) +#define FE_MM7 FE_MM(7) +typedef struct FeRegXMM { unsigned char idx; } FeRegXMM; +#define FE_XMM(idx) (FE_STRUCT(FeRegXMM) { idx }) +#define FE_XMM0 FE_XMM(0) +#define FE_XMM1 FE_XMM(1) +#define FE_XMM2 FE_XMM(2) +#define FE_XMM3 FE_XMM(3) +#define FE_XMM4 FE_XMM(4) +#define FE_XMM5 FE_XMM(5) +#define FE_XMM6 FE_XMM(6) +#define FE_XMM7 FE_XMM(7) +#define FE_XMM8 FE_XMM(8) +#define FE_XMM9 FE_XMM(9) +#define FE_XMM10 FE_XMM(10) +#define FE_XMM11 FE_XMM(11) +#define FE_XMM12 FE_XMM(12) +#define FE_XMM13 FE_XMM(13) +#define FE_XMM14 FE_XMM(14) +#define FE_XMM15 FE_XMM(15) +#define FE_XMM16 FE_XMM(16) +#define FE_XMM17 FE_XMM(17) +#define FE_XMM18 FE_XMM(18) +#define FE_XMM19 FE_XMM(19) +#define FE_XMM20 FE_XMM(20) +#define FE_XMM21 FE_XMM(21) +#define FE_XMM22 FE_XMM(22) +#define FE_XMM23 FE_XMM(23) +#define FE_XMM24 FE_XMM(24) +#define FE_XMM25 FE_XMM(25) +#define FE_XMM26 FE_XMM(26) +#define FE_XMM27 FE_XMM(27) +#define FE_XMM28 FE_XMM(28) +#define FE_XMM29 FE_XMM(29) +#define FE_XMM30 FE_XMM(30) +#define FE_XMM31 FE_XMM(31) +typedef struct FeRegMASK { unsigned char idx; } FeRegMASK; +#define FE_K(idx) (FE_STRUCT(FeRegMASK) { idx }) +#define FE_K0 FE_K(0) +#define FE_K1 FE_K(1) +#define FE_K2 FE_K(2) +#define FE_K3 FE_K(3) +#define FE_K4 FE_K(4) +#define FE_K5 FE_K(5) +#define FE_K6 FE_K(6) +#define FE_K7 FE_K(7) +typedef struct FeRegTMM { unsigned char idx; } FeRegTMM; +#define FE_TMM(idx) (FE_STRUCT(FeRegTMM) { idx }) +#define FE_TMM0 FE_TMM(0) +#define FE_TMM1 FE_TMM(1) +#define FE_TMM2 FE_TMM(2) +#define FE_TMM3 FE_TMM(3) +#define FE_TMM4 FE_TMM(4) +#define FE_TMM5 FE_TMM(5) +#define FE_TMM6 FE_TMM(6) +#define FE_TMM7 FE_TMM(7) +typedef struct FeRegCR { unsigned char idx; } FeRegCR; +#define FE_CR(idx) (FE_STRUCT(FeRegCR) { idx }) +typedef struct FeRegDR { unsigned char idx; } FeRegDR; +#define FE_DR(idx) (FE_STRUCT(FeRegDR) { idx }) + +// Internal only +// Disambiguate GP and GPH -- C++ uses conversion constructors; C uses _Generic. +#ifdef __cplusplus +} +namespace { + struct FeRegGPLH { + unsigned char idx; + FeRegGPLH(FeRegGP gp) : idx(gp.idx) {} + FeRegGPLH(FeRegGPH gp) : idx(gp.idx | 0x20) {} + }; +} +extern "C" { +#define FE_MAKE_GPLH(reg) reg +#else +typedef struct FeRegGPLH { unsigned char idx; } FeRegGPLH; +#define FE_GPLH(idx) (FE_STRUCT(FeRegGPLH) { idx }) +#define FE_MAKE_GPLH(reg) FE_GPLH(_Generic((reg), FeRegGPH: 0x20, FeRegGP: 0) | (reg).idx) +#endif + +typedef struct FeMem { + uint8_t flags; + FeRegGP base; + unsigned char scale; + // union { + FeRegGP idx; + // FeRegXMM idx_xmm; + // }; + int32_t off; +} FeMem; +#define FE_MEM(base,sc,idx,off) (FE_STRUCT(FeMem) { 0, base, sc, idx, off }) +typedef struct FeMemV { + uint8_t flags; + FeRegGP base; + unsigned char scale; + FeRegXMM idx; + int32_t off; +} FeMemV; +#define FE_MEMV(base,sc,idx,off) (FE_STRUCT(FeMemV) { 0, base, sc, idx, off }) + +// NOP is special: flags is interpreted as the length in bytes, 0 = 1 byte, too. +unsigned fe64_NOP(uint8_t* buf, unsigned flags); + +#include + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/third_party/fadec/fadec.h b/third_party/fadec/fadec.h new file mode 100644 index 0000000..2271e5a --- /dev/null +++ b/third_party/fadec/fadec.h @@ -0,0 +1,286 @@ + +#ifndef FD_FADEC_H_ +#define FD_FADEC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + FD_REG_R0 = 0, FD_REG_R1, FD_REG_R2, FD_REG_R3, + FD_REG_R4, FD_REG_R5, FD_REG_R6, FD_REG_R7, + FD_REG_R8, FD_REG_R9, FD_REG_R10, FD_REG_R11, + FD_REG_R12, FD_REG_R13, FD_REG_R14, FD_REG_R15, + // Alternative names for byte registers + FD_REG_AL = 0, FD_REG_CL, FD_REG_DL, FD_REG_BL, + FD_REG_AH, FD_REG_CH, FD_REG_DH, FD_REG_BH, + // Alternative names for general purpose registers + FD_REG_AX = 0, FD_REG_CX, FD_REG_DX, FD_REG_BX, + FD_REG_SP, FD_REG_BP, FD_REG_SI, FD_REG_DI, + // FD_REG_IP can only be accessed in long mode (64-bit) + FD_REG_IP = 0x10, + // Segment register values + FD_REG_ES = 0, FD_REG_CS, FD_REG_SS, FD_REG_DS, FD_REG_FS, FD_REG_GS, + // No register specified + FD_REG_NONE = 0x3f +} FdReg; + +typedef enum { +#define FD_MNEMONIC(name,value) FDI_ ## name = value, +#include +#undef FD_MNEMONIC +} FdInstrType; + +/** Internal use only. **/ +enum { + FD_FLAG_LOCK = 1 << 0, + FD_FLAG_REP = 1 << 2, + FD_FLAG_REPNZ = 1 << 1, + FD_FLAG_64 = 1 << 7, +}; + +/** Operand types. **/ +typedef enum { + FD_OT_NONE = 0, + FD_OT_REG = 1, + FD_OT_IMM = 2, + FD_OT_MEM = 3, + FD_OT_OFF = 4, + FD_OT_MEMBCST = 5, +} FdOpType; + +typedef enum { + /** Vector (SSE/AVX) register XMMn/YMMn/ZMMn **/ + FD_RT_VEC = 0, + /** Low general purpose register **/ + FD_RT_GPL = 1, + /** High-byte general purpose register **/ + FD_RT_GPH = 2, + /** Segment register **/ + FD_RT_SEG = 3, + /** FPU register ST(n) **/ + FD_RT_FPU = 4, + /** MMX register MMn **/ + FD_RT_MMX = 5, + /** TMM register TMMn **/ + FD_RT_TMM = 6, + /** Vector mask (AVX-512) register Kn **/ + FD_RT_MASK = 7, + /** Bound register BNDn **/ + FD_RT_BND = 8, + /** Control Register CRn **/ + FD_RT_CR = 9, + /** Debug Register DRn **/ + FD_RT_DR = 10, + /** Must be a memory operand **/ + FD_RT_MEM = 15, +} FdRegType; + +/** Do not depend on the actual enum values. **/ +typedef enum { + /** Round to nearest (even) **/ + FD_RC_RN = 1, + /** Round down **/ + FD_RC_RD = 3, + /** Round up **/ + FD_RC_RU = 5, + /** Round to zero (truncate) **/ + FD_RC_RZ = 7, + /** Rounding mode as specified in MXCSR **/ + FD_RC_MXCSR = 0, + /** Rounding mode irrelevant, but SAE **/ + FD_RC_SAE = 6, +} FdRoundControl; + +/** Internal use only. **/ +typedef struct { + uint8_t type; + uint8_t size; + uint8_t reg; + uint8_t misc; +} FdOp; + +/** Never(!) access struct fields directly. Use the macros defined below. **/ +typedef struct { + uint16_t type; + uint8_t flags; + uint8_t segment; + uint8_t addrsz; + uint8_t operandsz; + uint8_t size; + uint8_t evex; + + FdOp operands[4]; + + int64_t disp; + int64_t imm; + + uint64_t address; +} FdInstr; + +typedef enum { + FD_ERR_UD = -1, + FD_ERR_INTERNAL = -2, + FD_ERR_PARTIAL = -3, +} FdErr; + + +/** Decode an instruction. + * \param buf Buffer for instruction bytes. + * \param len Length of the buffer (in bytes). An instruction is not longer than + * 15 bytes on all x86 architectures. + * \param mode Decoding mode, either 32 for protected/compatibility mode or 64 + * for long mode. 16-bit mode is not supported. + * \param address Virtual address where the decoded instruction. This is used + * for computing jump targets. If "0" is passed, operands which require + * adding EIP/RIP will be stored as FD_OT_OFF operands. + * DEPRECATED: Strongly prefer passing 0 and using FD_OT_OFF operands. + * \param out_instr Pointer to the instruction buffer. Note that this may get + * partially written even if an error is returned. + * \return The number of bytes consumed by the instruction, or a negative number + * indicating an error. + **/ +int fd_decode(const uint8_t* buf, size_t len, int mode, uintptr_t address, + FdInstr* out_instr); + +/** Format an instruction to a string. + * \param instr The instruction. + * \param buf The buffer to hold the formatted string. + * \param len The length of the buffer. + **/ +void fd_format(const FdInstr* instr, char* buf, size_t len); + +/** Format an instruction to a string. + * NOTE: API stability is currently not guaranteed for this function; its name + * and/or signature may change in future. + * + * \param instr The instruction. + * \param addr The base address to use for printing FD_OT_OFF operands. + * \param buf The buffer to hold the formatted string. + * \param len The length of the buffer. + **/ +void fd_format_abs(const FdInstr* instr, uint64_t addr, char* buf, size_t len); + +/** Get the stringified name of an instruction type. + * NOTE: API stability is currently not guaranteed for this function; changes + * to the signature and/or the returned string can be expected. E.g., a future + * version may take an extra parameter for the instruction operand size; or may + * take a complete decoded instruction as first parameter and return the + * mnemonic returned by fd_format. + * + * \param ty An instruction type + * \return The instruction type as string, or "(invalid)". + **/ +const char* fdi_name(FdInstrType ty); + + +/** Gets the type/mnemonic of the instruction. + * ABI STABILITY NOTE: different versions or builds of the library may use + * different values. When linking as shared library, any interpretation of this + * value is meaningless; in such cases use fdi_name. + * + * API STABILITY NOTE: a future version of this library may decode string + * instructions prefixed with REP/REPNZ and instructions prefixed with LOCK as + * separate instruction types. **/ +#define FD_TYPE(instr) ((FdInstrType) (instr)->type) +/** DEPRECATED: This functionality is obsolete in favor of FD_OT_OFF. + * Gets the address of the instruction. Invalid if decoded address == 0. **/ +#define FD_ADDRESS(instr) ((instr)->address) +/** Gets the size of the instruction in bytes. **/ +#define FD_SIZE(instr) ((instr)->size) +/** Gets the specified segment override, or FD_REG_NONE for default segment. **/ +#define FD_SEGMENT(instr) ((FdReg) (instr)->segment & 0x3f) +/** Gets the address size attribute of the instruction in bytes. **/ +#define FD_ADDRSIZE(instr) (1 << (instr)->addrsz) +/** Get the logarithmic address size; FD_ADDRSIZE == 1 << FD_ADDRSIZELG **/ +#define FD_ADDRSIZELG(instr) ((instr)->addrsz) +/** Gets the operation width in bytes of the instruction if this is not encoded + * in the operands, for example for the string instruction (e.g. MOVS). **/ +#define FD_OPSIZE(instr) (1 << (instr)->operandsz) +/** Get the logarithmic operand size; FD_OPSIZE == 1 << FD_OPSIZELG iff + * FD_OPSIZE is valid. **/ +#define FD_OPSIZELG(instr) ((instr)->operandsz) +/** Indicates whether the instruction was encoded with a REP prefix. Needed for: + * (1) Handling the instructions MOVS, STOS, LODS, INS and OUTS properly. + * (2) Handling the instructions SCAS and CMPS, for which this means REPZ. **/ +#define FD_HAS_REP(instr) ((instr)->flags & FD_FLAG_REP) +/** Indicates whether the instruction was encoded with a REPNZ prefix. **/ +#define FD_HAS_REPNZ(instr) ((instr)->flags & FD_FLAG_REPNZ) +/** Indicates whether the instruction was encoded with a LOCK prefix. **/ +#define FD_HAS_LOCK(instr) ((instr)->flags & FD_FLAG_LOCK) +/** Do not use. **/ +#define FD_IS64(instr) ((instr)->flags & FD_FLAG_64) + +/** Gets the type of an operand at the given index. **/ +#define FD_OP_TYPE(instr,idx) ((FdOpType) (instr)->operands[idx].type) +/** Gets the size in bytes of an operand. However, there are a few exceptions: + * (1) For some register types, e.g., segment registers, or x87 registers, the + * size is zero. (This allows some simplifications internally.) + * (2) On some vector instructions this may be only an approximation of the + * actually needed operand size (that is, an instruction may/must only use + * a smaller part than specified here). The real operand size is always + * fully recoverable in combination with the instruction type. **/ +#define FD_OP_SIZE(instr,idx) (1 << (instr)->operands[idx].size >> 1) +/** Get the logarithmic size of an operand; see FD_OP_SIZE for special cases. + * The following equality holds: FD_OP_SIZE == 1 << (FD_OP_SIZELG + 1) >> 1 + * Note that typically FD_OP_SIZE == 1 << FD_OP_SIZELG unless a zero-sized + * memory operand, FPU register, or mask register is involved. **/ +#define FD_OP_SIZELG(instr,idx) ((instr)->operands[idx].size - 1) +/** Gets the accessed register index of a register operand. Note that /only/ the + * index is returned, no further interpretation of the index (which depends on + * the instruction type) is done. The register type can be fetched using + * FD_OP_REG_TYPE, e.g. for distinguishing high-byte registers. + * Only valid if FD_OP_TYPE == FD_OT_REG **/ +#define FD_OP_REG(instr,idx) ((FdReg) (instr)->operands[idx].reg) +/** Gets the type of the accessed register. + * Only valid if FD_OP_TYPE == FD_OT_REG **/ +#define FD_OP_REG_TYPE(instr,idx) ((FdRegType) (instr)->operands[idx].misc) +/** DEPRECATED: use FD_OP_REG_TYPE() == FD_RT_GPH instead. + * Returns whether the accessed register is a high-byte register. In that case, + * the register index has to be decreased by 4. + * Only valid if FD_OP_TYPE == FD_OT_REG **/ +#define FD_OP_REG_HIGH(instr,idx) (FD_OP_REG_TYPE(instr,idx) == FD_RT_GPH) +/** Gets the index of the base register from a memory operand, or FD_REG_NONE, + * if the memory operand has no base register. This is the only case where the + * 64-bit register RIP can be returned, in which case the operand also has no + * scaled index register. + * Only valid if FD_OP_TYPE == FD_OT_MEM/MEMBCST **/ +#define FD_OP_BASE(instr,idx) ((FdReg) (instr)->operands[idx].reg) +/** Gets the index of the index register from a memory operand, or FD_REG_NONE, + * if the memory operand has no scaled index register. + * Only valid if FD_OP_TYPE == FD_OT_MEM/MEMBCST **/ +#define FD_OP_INDEX(instr,idx) ((FdReg) (instr)->operands[idx].misc & 0x3f) +/** Gets the scale of the index register from a memory operand when existent. + * This does /not/ return the scale in an absolute value but returns the amount + * of bits the index register is shifted to the left (i.e. the value in in the + * range 0-3). The actual scale can be computed easily using 1<operands[idx].misc >> 6) +/** Gets the sign-extended displacement of a memory operand. + * Only valid if FD_OP_TYPE == FD_OT_MEM/MEMBCST **/ +#define FD_OP_DISP(instr,idx) ((int64_t) (instr)->disp) +/** Get memory broadcast size in bytes. + * Only valid if FD_OP_TYPE == FD_OT_MEMBCST **/ +#define FD_OP_BCSTSZ(instr,idx) (1 << FD_OP_BCSTSZLG(instr,idx)) +/** Get logarithmic memory broadcast size (1 = 2-byte; 2=4-byte; 3=8-byte). + * Only valid if FD_OP_TYPE == FD_OT_MEMBCST **/ +#define FD_OP_BCSTSZLG(instr,idx) ((instr)->segment >> 6) +/** Gets the (sign-extended) encoded constant for an immediate operand. + * Only valid if FD_OP_TYPE == FD_OT_IMM or FD_OP_TYPE == FD_OT_OFF **/ +#define FD_OP_IMM(instr,idx) ((instr)->imm) + +/** Get the opmask register for EVEX-encoded instructions; 0 for no mask. **/ +#define FD_MASKREG(instr) ((instr)->evex & 0x07) +/** Get whether zero masking shall be used. Only valid if FD_MASKREG != 0. **/ +#define FD_MASKZERO(instr) ((instr)->evex & 0x80) +/** Get rounding mode for EVEX-encoded instructions. See FdRoundControl. **/ +#define FD_ROUNDCONTROL(instr) ((FdRoundControl) (((instr)->evex & 0x70) >> 4)) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/third_party/fadec/format.c b/third_party/fadec/format.c new file mode 100644 index 0000000..a25f13c --- /dev/null +++ b/third_party/fadec/format.c @@ -0,0 +1,563 @@ + +#include +#include +#include +#ifdef _MSC_VER +#include +#endif + +#include + + +#ifdef __GNUC__ +#define LIKELY(x) __builtin_expect(!!(x), 1) +#define UNLIKELY(x) __builtin_expect(!!(x), 0) +#define DECLARE_ARRAY_SIZE(n) static n +#define DECLARE_RESTRICTED_ARRAY_SIZE(n) restrict static n +#else +#define LIKELY(x) (x) +#define UNLIKELY(x) (x) +#define DECLARE_ARRAY_SIZE(n) n +#define DECLARE_RESTRICTED_ARRAY_SIZE(n) n +#endif + +#if defined(__has_attribute) +#if __has_attribute(fallthrough) +#define FALLTHROUGH() __attribute__((fallthrough)) +#endif +#endif +#if !defined(FALLTHROUGH) +#define FALLTHROUGH() ((void)0) +#endif + +struct FdStr { + const char* s; + unsigned sz; +}; + +#define fd_stre(s) ((struct FdStr) { (s "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"), sizeof (s)-1 }) + +static char* +fd_strpcat(char* restrict dst, struct FdStr src) { +#ifdef __GNUC__ + unsigned lim = __builtin_constant_p(src.sz) && src.sz <= 8 ? 8 : 16; +#else + unsigned lim = 16; +#endif + for (unsigned i = 0; i < lim; i++) + dst[i] = src.s[i]; + // __builtin_memcpy(dst, src.s, 16); + return dst + src.sz; +} + +static unsigned +fd_clz64(uint64_t v) { +#if defined(__GNUC__) + return __builtin_clzll(v); +#elif defined(_MSC_VER) + unsigned long index; + + // 32-bit MSVC doesn't support _BitScanReverse64. This is an attempt to + // identify this case. +#if INTPTR_MAX == INT64_MAX + _BitScanReverse64(&index, v); +#else + if (_BitScanReverse(&index, v >> 32)) + return 31 - index; + + _BitScanReverse(&index, v & 0xffffffff); +#endif + + return 63 - index; +#else +#error Unsupported compiler. +#endif +} + +#if defined(__SSE2__) +#include +#endif + +static char* +fd_strpcatnum(char dst[DECLARE_ARRAY_SIZE(18)], uint64_t val) { + unsigned lz = fd_clz64(val|1); + unsigned numbytes = 16 - (lz / 4); +#if defined(__SSE2__) + __m128i mv = _mm_set_epi64x(0, val << (lz & -4)); + __m128i mvp = _mm_unpacklo_epi8(mv, mv); + __m128i mva = _mm_srli_epi16(mvp, 12); + __m128i mvb = _mm_and_si128(mvp, _mm_set1_epi16(0x0f00u)); + __m128i ml = _mm_or_si128(mva, mvb); + __m128i mn = _mm_or_si128(ml, _mm_set1_epi8(0x30)); + __m128i mgt = _mm_cmpgt_epi8(ml, _mm_set1_epi8(9)); + __m128i mgtm = _mm_and_si128(mgt, _mm_set1_epi8(0x61 - 0x3a)); + __m128i ma = _mm_add_epi8(mn, mgtm); + __m128i msw = _mm_shufflehi_epi16(_mm_shufflelo_epi16(ma, 0x1b), 0x1b); + __m128i ms = _mm_shuffle_epi32(msw, 0x4e); + _mm_storeu_si128((__m128i_u*) (dst + 2), ms); +#else + unsigned idx = numbytes + 2; + do { + dst[--idx] = "0123456789abcdef"[val % 16]; + val /= 16; + } while (val); +#endif + dst[0] = '0'; + dst[1] = 'x'; + return dst + numbytes + 2; +} + +static char* +fd_strpcatreg(char* restrict dst, size_t rt, size_t ri, unsigned size) { + const char* nametab = + "\2al\4bnd0\2cl\4bnd1\2dl\4bnd2\2bl\4bnd3" + "\3spl\0 \3bpl\0 \3sil\0 \3dil\0 " + "\3r8b\0 \3r9b\0 \4r10b\0 \4r11b\0 " + "\4r12b\2ah\4r13b\2ch\4r14b\2dh\4r15b\2bh\0\0 " + + "\2ax\4tmm0\2cx\4tmm1\2dx\4tmm2\2bx\4tmm3" + "\2sp\4tmm4\2bp\4tmm5\2si\4tmm6\2di\4tmm7" + "\3r8w \2es\3r9w \2cs\4r10w\2ss\4r11w\2ds" + "\4r12w\2fs\4r13w\2gs\4r14w\0 \4r15w\0 \2ip\0 " + + "\3eax\3mm0\3ecx\3mm1\3edx\3mm2\3ebx\3mm3" + "\3esp\3mm4\3ebp\3mm5\3esi\3mm6\3edi\3mm7" + "\3r8d \2k0\3r9d \2k1\4r10d\2k2\4r11d\2k3" + "\4r12d\2k4\4r13d\2k5\4r14d\2k6\4r15d\2k7\3eip\0 " + + "\3rax\3cr0\3rcx\0 \3rdx\3cr2\3rbx\3cr3" + "\3rsp\3cr4\3rbp\0 \3rsi\0 \3rdi\0 " + "\2r8 \3cr8\2r9 \3dr0\3r10\3dr1\3r11\3dr2" + "\3r12\3dr3\3r13\3dr4\3r14\3dr5\3r15\3dr6\3rip\3dr7" + + "\5st(0)\0 \5st(1)\0 \5st(2)\0 \5st(3)\0 " + "\5st(4)\0 \5st(5)\0 \5st(6)\0 \5st(7)\0 " + + "\4xmm0\0 \4xmm1\0 \4xmm2\0 \4xmm3\0 " + "\4xmm4\0 \4xmm5\0 \4xmm6\0 \4xmm7\0 " + "\4xmm8\0 \4xmm9\0 \5xmm10\0 \5xmm11\0 " + "\5xmm12\0 \5xmm13\0 \5xmm14\0 \5xmm15\0 " + "\5xmm16\0 \5xmm17\0 \5xmm18\0 \5xmm19\0 " + "\5xmm20\0 \5xmm21\0 \5xmm22\0 \5xmm23\0 " + "\5xmm24\0 \5xmm25\0 \5xmm26\0 \5xmm27\0 " + "\5xmm28\0 \5xmm29\0 \5xmm30\0 \5xmm31\0 "; + + static const uint16_t nametabidx[] = { + [FD_RT_GPL] = 0 * 17*8 + 0 * 8 + 0, + [FD_RT_GPH] = 0 * 17*8 + 8 * 8 + 5, + [FD_RT_SEG] = 1 * 17*8 + 8 * 8 + 5, + [FD_RT_FPU] = 4 * 17*8 + 0 * 8 + 0, + [FD_RT_MMX] = 2 * 17*8 + 0 * 8 + 4, + [FD_RT_VEC] = 4 * 17*8 + 8 * 8 + 0, + [FD_RT_MASK]= 2 * 17*8 + 8 * 8 + 5, + [FD_RT_BND] = 0 * 17*8 + 0 * 8 + 3, + [FD_RT_CR] = 3 * 17*8 + 0 * 8 + 4, + [FD_RT_DR] = 3 * 17*8 + 9 * 8 + 4, + [FD_RT_TMM] = 1 * 17*8 + 0 * 8 + 3, + }; + + unsigned idx = rt == FD_RT_GPL ? size * 17*8 : nametabidx[rt]; + const char* name = nametab + idx + 8*ri; + for (unsigned i = 0; i < 8; i++) + dst[i] = name[i+1]; + if (UNLIKELY(rt == FD_RT_VEC && size > 4)) + dst[0] += size - 4; + return dst + *name; +} + +const char* +fdi_name(FdInstrType ty) { + (void) ty; + return "(invalid)"; +} + +static char* +fd_mnemonic(char buf[DECLARE_RESTRICTED_ARRAY_SIZE(48)], const FdInstr* instr) { +#define FD_DECODE_TABLE_STRTAB1 + static const char* mnemonic_str = +#include + // 20 NULL Bytes to prevent out-of-bounds reads + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"; +#undef FD_DECODE_TABLE_STRTAB1 + +#define FD_DECODE_TABLE_STRTAB2 + static const uint16_t mnemonic_offs[] = { +#include + }; +#undef FD_DECODE_TABLE_STRTAB2 + +#define FD_DECODE_TABLE_STRTAB3 + static const uint8_t mnemonic_lens[] = { +#include + }; +#undef FD_DECODE_TABLE_STRTAB3 + + const char* mnem = &mnemonic_str[mnemonic_offs[FD_TYPE(instr)]]; + unsigned mnemlen = mnemonic_lens[FD_TYPE(instr)]; + + bool prefix_xacq_xrel = false; + bool prefix_segment = false; + + char sizesuffix[4] = {0}; + unsigned sizesuffixlen = 0; + + if (UNLIKELY(FD_OP_TYPE(instr, 0) == FD_OT_OFF && FD_OP_SIZELG(instr, 0) == 1)) + sizesuffix[0] = 'w', sizesuffixlen = 1; + + switch (FD_TYPE(instr)) { + case FDI_C_SEP: + mnem += FD_OPSIZE(instr) & 0xc; + mnemlen = 3; + break; + case FDI_C_EX: + mnem += FD_OPSIZE(instr) & 0xc; + mnemlen = FD_OPSIZE(instr) < 4 ? 3 : 4; + break; + case FDI_CMPXCHGD: + switch (FD_OPSIZELG(instr)) { + default: break; + case 2: sizesuffix[0] = '8', sizesuffix[1] = 'b', sizesuffixlen = 2; break; + case 3: sizesuffix[0] = '1', sizesuffix[1] = '6', sizesuffix[2] = 'b', sizesuffixlen = 3; break; + } + break; + case FDI_JCXZ: + mnemlen = FD_ADDRSIZELG(instr) == 1 ? 4 : 5; + mnem += 5 * (FD_ADDRSIZELG(instr) - 1); + break; + case FDI_PUSH: + if (FD_OP_SIZELG(instr, 0) == 1 && FD_OP_TYPE(instr, 0) == FD_OT_IMM) + sizesuffix[0] = 'w', sizesuffixlen = 1; + FALLTHROUGH(); + case FDI_POP: + if (FD_OP_SIZELG(instr, 0) == 1 && FD_OP_TYPE(instr, 0) == FD_OT_REG && + FD_OP_REG_TYPE(instr, 0) == FD_RT_SEG) + sizesuffix[0] = 'w', sizesuffixlen = 1; + break; + case FDI_XCHG: + if (FD_OP_TYPE(instr, 0) == FD_OT_MEM) + prefix_xacq_xrel = true; + break; + case FDI_MOV: + // MOV C6h/C7h can have XRELEASE prefix. + if (FD_HAS_REP(instr) && FD_OP_TYPE(instr, 0) == FD_OT_MEM && + FD_OP_TYPE(instr, 1) == FD_OT_IMM) + prefix_xacq_xrel = true; + break; + case FDI_FXSAVE: + case FDI_FXRSTOR: + case FDI_XSAVE: + case FDI_XSAVEC: + case FDI_XSAVEOPT: + case FDI_XSAVES: + case FDI_XRSTOR: + case FDI_XRSTORS: + if (FD_OPSIZELG(instr) == 3) + sizesuffix[0] = '6', sizesuffix[1] = '4', sizesuffixlen = 2; + break; + case FDI_EVX_MOV_G2X: + case FDI_EVX_MOV_X2G: + case FDI_EVX_PEXTR: + sizesuffix[0] = "bwdq"[FD_OP_SIZELG(instr, 0)]; + sizesuffixlen = 1; + break; + case FDI_EVX_PBROADCAST: + sizesuffix[0] = "bwdq"[FD_OP_SIZELG(instr, 1)]; + sizesuffixlen = 1; + break; + case FDI_EVX_PINSR: + sizesuffix[0] = "bwdq"[FD_OP_SIZELG(instr, 2)]; + sizesuffixlen = 1; + break; + case FDI_RET: + case FDI_ENTER: + case FDI_LEAVE: + if (FD_OPSIZELG(instr) == 1) + sizesuffix[0] = 'w', sizesuffixlen = 1; + break; + case FDI_LODS: + case FDI_MOVS: + case FDI_CMPS: + case FDI_OUTS: + prefix_segment = true; + FALLTHROUGH(); + case FDI_STOS: + case FDI_SCAS: + case FDI_INS: + if (FD_HAS_REP(instr)) + buf = fd_strpcat(buf, fd_stre("rep ")); + if (FD_HAS_REPNZ(instr)) + buf = fd_strpcat(buf, fd_stre("repnz ")); + if (FD_IS64(instr) && FD_ADDRSIZELG(instr) == 2) + buf = fd_strpcat(buf, fd_stre("addr32 ")); + if (!FD_IS64(instr) && FD_ADDRSIZELG(instr) == 1) + buf = fd_strpcat(buf, fd_stre("addr16 ")); + FALLTHROUGH(); + case FDI_IN: + case FDI_OUT: + if (FD_OP_TYPE(instr, 0) != FD_OT_NONE) + break; + FALLTHROUGH(); + case FDI_PUSHA: + case FDI_POPA: + case FDI_PUSHF: + case FDI_POPF: + case FDI_RETF: + case FDI_IRET: + sizesuffix[0] = "bwdq"[FD_OPSIZELG(instr)]; + sizesuffixlen = 1; + break; + default: break; + } + + if (UNLIKELY(prefix_xacq_xrel || FD_HAS_LOCK(instr))) { + if (FD_HAS_REP(instr)) + buf = fd_strpcat(buf, fd_stre("xrelease ")); + if (FD_HAS_REPNZ(instr)) + buf = fd_strpcat(buf, fd_stre("xacquire ")); + } + if (UNLIKELY(FD_HAS_LOCK(instr))) + buf = fd_strpcat(buf, fd_stre("lock ")); + if (UNLIKELY(prefix_segment && FD_SEGMENT(instr) != FD_REG_NONE)) { + *buf++ = "ecsdfg\0"[FD_SEGMENT(instr) & 7]; + *buf++ = 's'; + *buf++ = ' '; + } + + for (unsigned i = 0; i < 20; i++) + buf[i] = mnem[i]; + buf += mnemlen; + for (unsigned i = 0; i < 4; i++) + buf[i] = sizesuffix[i]; + buf += sizesuffixlen; + + return buf; +} + +static char* +fd_format_impl(char buf[DECLARE_RESTRICTED_ARRAY_SIZE(128)], const FdInstr* instr, uint64_t addr) { + buf = fd_mnemonic(buf, instr); + + for (int i = 0; i < 4; i++) + { + FdOpType op_type = FD_OP_TYPE(instr, i); + if (op_type == FD_OT_NONE) + break; + if (i > 0) + *buf++ = ','; + *buf++ = ' '; + + int size = FD_OP_SIZELG(instr, i); + + if (op_type == FD_OT_REG) { + unsigned type = FD_OP_REG_TYPE(instr, i); + unsigned idx = FD_OP_REG(instr, i); + buf = fd_strpcatreg(buf, type, idx, size); + } else if (op_type == FD_OT_MEM || op_type == FD_OT_MEMBCST) { + unsigned idx_rt = FD_RT_GPL; + unsigned idx_sz = FD_ADDRSIZELG(instr); + switch (FD_TYPE(instr)) { + case FDI_CMPXCHGD: size = FD_OPSIZELG(instr) + 1; break; + case FDI_BOUND: size += 1; break; + case FDI_JMPF: + case FDI_CALLF: + case FDI_LDS: + case FDI_LES: + case FDI_LFS: + case FDI_LGS: + case FDI_LSS: + size += 6; + break; + case FDI_FLD: + case FDI_FSTP: + case FDI_FBLD: + case FDI_FBSTP: + size = size >= 0 ? size : 9; + break; + case FDI_VPGATHERQD: + case FDI_VGATHERQPS: + case FDI_EVX_PGATHERQD: + case FDI_EVX_GATHERQPS: + idx_rt = FD_RT_VEC; + idx_sz = FD_OP_SIZELG(instr, 0) + 1; + break; + case FDI_EVX_PSCATTERQD: + case FDI_EVX_SCATTERQPS: + idx_rt = FD_RT_VEC; + idx_sz = FD_OP_SIZELG(instr, 1) + 1; + break; + case FDI_VPGATHERDQ: + case FDI_VGATHERDPD: + case FDI_EVX_PGATHERDQ: + case FDI_EVX_GATHERDPD: + idx_rt = FD_RT_VEC; + idx_sz = FD_OP_SIZELG(instr, 0) - 1; + break; + case FDI_EVX_PSCATTERDQ: + case FDI_EVX_SCATTERDPD: + idx_rt = FD_RT_VEC; + idx_sz = FD_OP_SIZELG(instr, 1) - 1; + break; + case FDI_VPGATHERDD: + case FDI_VPGATHERQQ: + case FDI_VGATHERDPS: + case FDI_VGATHERQPD: + case FDI_EVX_PGATHERDD: + case FDI_EVX_PGATHERQQ: + case FDI_EVX_GATHERDPS: + case FDI_EVX_GATHERQPD: + idx_rt = FD_RT_VEC; + idx_sz = FD_OP_SIZELG(instr, 0); + break; + case FDI_EVX_PSCATTERDD: + case FDI_EVX_PSCATTERQQ: + case FDI_EVX_SCATTERDPS: + case FDI_EVX_SCATTERQPD: + idx_rt = FD_RT_VEC; + idx_sz = FD_OP_SIZELG(instr, 1); + break; + default: break; + } + + if (op_type == FD_OT_MEMBCST) + size = FD_OP_BCSTSZLG(instr, i); + + const char* ptrsizes = + "\00 " + "\11byte ptr " + "\11word ptr " + "\12dword ptr " + "\12qword ptr " + "\14xmmword ptr " + "\14ymmword ptr " + "\14zmmword ptr " + "\12dword ptr " // far ptr; word + 2 + "\12fword ptr " // far ptr; dword + 2 + "\12tbyte ptr "; // far ptr/FPU; qword + 2 + const char* ptrsize = ptrsizes + 16 * (size + 1); + buf = fd_strpcat(buf, (struct FdStr) { ptrsize+1, *ptrsize }); + + unsigned seg = FD_SEGMENT(instr); + if (seg != FD_REG_NONE) { + *buf++ = "ecsdfg\0"[seg & 7]; + *buf++ = 's'; + *buf++ = ':'; + } + *buf++ = '['; + + bool has_base = FD_OP_BASE(instr, i) != FD_REG_NONE; + bool has_idx = FD_OP_INDEX(instr, i) != FD_REG_NONE; + if (has_base) + buf = fd_strpcatreg(buf, FD_RT_GPL, FD_OP_BASE(instr, i), FD_ADDRSIZELG(instr)); + if (has_idx) { + if (has_base) + *buf++ = '+'; + *buf++ = '0' + (1 << FD_OP_SCALE(instr, i)); + *buf++ = '*'; + buf = fd_strpcatreg(buf, idx_rt, FD_OP_INDEX(instr, i), idx_sz); + } + uint64_t disp = FD_OP_DISP(instr, i); + if (disp && (has_base || has_idx)) { + *buf++ = (int64_t) disp < 0 ? '-' : '+'; + if ((int64_t) disp < 0) + disp = -disp; + } + if (FD_ADDRSIZELG(instr) == 1) + disp &= 0xffff; + else if (FD_ADDRSIZELG(instr) == 2) + disp &= 0xffffffff; + if (disp || (!has_base && !has_idx)) + buf = fd_strpcatnum(buf, disp); + *buf++ = ']'; + + if (UNLIKELY(op_type == FD_OT_MEMBCST)) { + // {1toX}, X = FD_OP_SIZE(instr, i) / BCSTSZ (=> 2/4/8/16/32) + unsigned bcstszidx = FD_OP_SIZELG(instr, i) - FD_OP_BCSTSZLG(instr, i) - 1; + const char* bcstsizes = "\6{1to2} \6{1to4} \6{1to8} \7{1to16}\7{1to32} "; + const char* bcstsize = bcstsizes + bcstszidx * 8; + buf = fd_strpcat(buf, (struct FdStr) { bcstsize+1, *bcstsize }); + } + } else if (op_type == FD_OT_IMM || op_type == FD_OT_OFF) { + uint64_t immediate = FD_OP_IMM(instr, i); + // Some instructions have actually two immediate operands which are + // decoded as a single operand. Split them here appropriately. + switch (FD_TYPE(instr)) { + default: + goto nosplitimm; + case FDI_SSE_EXTRQ: + case FDI_SSE_INSERTQ: + buf = fd_strpcatnum(buf, immediate & 0xff); + buf = fd_strpcat(buf, fd_stre(", ")); + immediate = (immediate >> 8) & 0xff; + break; + case FDI_ENTER: + buf = fd_strpcatnum(buf, immediate & 0xffff); + buf = fd_strpcat(buf, fd_stre(", ")); + immediate = (immediate >> 16) & 0xff; + break; + case FDI_JMPF: + case FDI_CALLF: + buf = fd_strpcatnum(buf, (immediate >> (8 << size)) & 0xffff); + *buf++ = ':'; + // immediate is masked below. + break; + } + + nosplitimm: + if (op_type == FD_OT_OFF) + immediate += addr + FD_SIZE(instr); + if (size == 0) + immediate &= 0xff; + else if (size == 1) + immediate &= 0xffff; + else if (size == 2) + immediate &= 0xffffffff; + buf = fd_strpcatnum(buf, immediate); + } + + if (i == 0 && FD_MASKREG(instr)) { + *buf++ = '{'; + buf = fd_strpcatreg(buf, FD_RT_MASK, FD_MASKREG(instr), 0); + *buf++ = '}'; + if (FD_MASKZERO(instr)) + buf = fd_strpcat(buf, fd_stre("{z}")); + } + } + if (UNLIKELY(FD_ROUNDCONTROL(instr) != FD_RC_MXCSR)) { + switch (FD_ROUNDCONTROL(instr)) { + case FD_RC_RN: buf = fd_strpcat(buf, fd_stre(", {rn-sae}")); break; + case FD_RC_RD: buf = fd_strpcat(buf, fd_stre(", {rd-sae}")); break; + case FD_RC_RU: buf = fd_strpcat(buf, fd_stre(", {ru-sae}")); break; + case FD_RC_RZ: buf = fd_strpcat(buf, fd_stre(", {rz-sae}")); break; + case FD_RC_SAE: buf = fd_strpcat(buf, fd_stre(", {sae}")); break; + default: break; // should not happen + } + } + *buf++ = '\0'; + return buf; +} + +void +fd_format(const FdInstr* instr, char* buffer, size_t len) +{ + fd_format_abs(instr, 0, buffer, len); +} + +void +fd_format_abs(const FdInstr* instr, uint64_t addr, char* restrict buffer, size_t len) { + char tmp[128]; + char* buf = buffer; + if (UNLIKELY(len < 128)) { + if (!len) + return; + buf = tmp; + } + + char* end = fd_format_impl(buf, instr, addr); + + if (buf != buffer) { + unsigned i; + for (i = 0; i < (end - tmp) && i < len-1; i++) + buffer[i] = tmp[i]; + buffer[i] = '\0'; + } +} diff --git a/third_party/fadec/instrs.txt b/third_party/fadec/instrs.txt new file mode 100644 index 0000000..2433c1e --- /dev/null +++ b/third_party/fadec/instrs.txt @@ -0,0 +1,2596 @@ +# Fadec Instruction Description Table +# +# This file table contains all supported instructions. The format is custom, +# this parsed and processed into decode tables/encoders in parseinstrs.py. +# +# +# The opcode is used to determine the instruction row when decoding from +# instruction bytes. There are multiple components up to the opcode byte: +# +# (VEX\.|EVEX\.)? -> VEX/EVEX prefix; or legacy if absent +# ((NP|66|F2|F3|NFx)\.)? -> optional mandatory prefix +# (W[01]\.)? -> W0/W1, ignored if absent +# (L(0|1|12|IG)\.)? -> VEX.L/EVEX.L'L constraint, must not occur for legacy +# opcodes; not really used for distinguishing instructions/encodings +# (exceptions: VZEROUPPER/VZEROALL and VMOVDDUP) +# (|0f|0f38|0f3a|M[56]\.) -> legacy escape; or VEX/EVEX opcode map +# [0-9a-f]{2} -> actual opcode byte +# +# After the opcode byte, at most one of the following specifiers can follow: +# +# /[rm] -> ModRM.mod specifier (register or memory operand only) +# /[0-7] -> ModRM.reg specifier (used as opcode extension) +# /[0-7][rm] -> ModRM.mod and ModRM.reg specifier +# /[rm][0-7] -> ModRM.mod and ModRM.r/m specifier (AMX only) +# [c-f][0-9a-f] -> complete ModRM specifier, whole byte used as opcode ext. +# + -> for O-encoded instructions, the last three bits are an operand +# +# A legacy opcode may be prefixed with "*", making it a weak opcode which can be +# overwritten by later opcode definitions. This is used for reserved nops, +# reserved prefetch, BSF/BSR (overwritten by TZCNT/LZCNT), and WBINVD +# (overwritten by WBNOINVD). +# +# The encoding description follows the naming found in older (pre-AVX-512) Intel +# SDMs. It maps encoding fields to operand indices and specifies the immediate +# encoding. The gist is: M=ModRM.r/m; R=ModRM.reg; V=VEX.vvvv; A=EAX/XMM0; C=CL; +# I=imm; O=opcode bits 5:7; S=opcode bits 2:4; FD/TD=absolute address; D=jump +# destination. RVMR is an exception, the register is encoded in imm8[7:4]. +# MOV_CR/MOV_DR are another exception, they ignore ModRM.mod and always encode a +# register operand. +# +# For operands, the first letter specified the operand kind. Naming is mostly +# consistent with Intel's SDM, except for F (Intel: eflags; here: FPU). +# +# GP MMX XMM MSK TMM FPU CR DR SEG +# ModRM.r/m (reg) R N U K T F - - - +# ModRM.r/m (r/m) E Q W K T - - - - +# ModRM.reg G P V K T F C D S +# VEX.vvvv B - H K T - - - - +# imm8[7:4] - - L - - - - - - +# +# M=memory only; O=direct address +# I=immediate; A=address/far jmp; J=rip-relative address/jmp +# +# The remaining one or two letters specify the operand size: +# +# - Fixed sizes: b=1; w=2, d/ss=4; q/sd=8; dq=16; qq=32; oq=64 +# - GP operand sizes: v=2/4/8 (66/REX.W); y=4/8 (66 ignored) +# - Vector sizes: x/ps/pd=16/32/64 (EVEX.L'L); h=half x, f=fourth x; e=eighth x +# - Other immediate sizes: z=v with max. 4 bytes; bs=v (sign-extended byte); +# zd=z (but always four byte imm); zq=z (but always eight byte imm) +# - Special operand size: a=z:z (BOUND only); p=w:z (far pointer) +# - If not letter is specified, the operand size is decoded as zero. The size +# is implicitly part of the operand and can be reconstructed by the user. +# +# The instruction mnemonic is generally specified as decoded/formatted (there +# are a few exceptions, see parseinstrs.py decode_table and encode_mnems). +# +# After the mnemonic, flags can be specified. Some common flags have a short +# form immediately after the mnemonic (e.g., EVX_ADDSD+kr), others do not. +# +# - I64: invalid in 64-bit mode +# - O64: only valid in 64-bit mode +# - +w (INSTR_WIDTH): store operand size as instruction attribute; used for +# instructions that depend on the operand size but have no explicit operands. +# - +a (U67): respects addr-size override even without memory operand. +# - +s (USEG): respects segment override even without memory operand. +# - +k (MASK): supports EVEX masking. +# - +e (SAE): supports EVEX suppress all exceptions. +# - +r (ER): supports EVEX embedded rounding control. +# - +b (BCST): supports EVEX embedded broadcast. Broadcast size depends on REX.W +# (REX.W=0 => 32 bits; REX.W=1 => 64 bits). +# - BCST16: set EVEX embedded broadcast size to 16 bits. +# - SZ8: has effective operand size of 8 bits (encode only). +# - U66: uses 66 prefix as operand size override even with a mandatory prefix. +# - I66: ignores 66 prefix as operand size override. +# - LOCK: supports LOCK prefix when the first operand is memory. +# - D64: defaults to 64-bit operand size in 64-bit mode (REX.W ignored). +# - F64: forced to 64-bit operand size in 64-bit mode (66/REX.W ignored). +# NB: this is Intel-specific. On AMD, F64 behaves like D64. +# - VSIB: memory operand uses VSIB encoding (SIB required, idx is vector). +# - ENC_SEPSZ: attach size suffixes to each operand (encode only). +# - ENC_NOSZ: do not attach size suffix (encode only). +# - ENC_REP: supports REP prefix. +# - ENC_REPCC: supports REPZ/REPNZ prefix. +# - UNDOC: undocumented, ignored by default. +# - TUPLE_*: AVX-512 tuple size. Only used to verify operand sizes. +# - CPL0: only valid if CPL=0 (system mode). Annotation only. +# - F=: feature flags. Annotation only. +# - EFL=: status flags use/modifications. Order: OF/DF/IF/SF/ZF/AF/PF/CF. +# t=test; m=modify; 0=clear; 1=set; M=test-and-modify; u=undefined +# +# +# Opcode ENC OP1 OP2 OP3 OP4 MNEM COND SZ? MISC FLAGS +# LOCK SZ8 +# I64 D64 +# O64 F64 +# VSIB U66 +# I66 +# ------------------- ---- --- --- --- --- ------- ---- --- ---------- +00 MR Eb Gb - - ADD LOCK SZ8 EFL=m--mmmmm +01 MR Ev Gv - - ADD LOCK EFL=m--mmmmm +02 RM Gb Eb - - ADD SZ8 EFL=m--mmmmm +03 RM Gv Ev - - ADD EFL=m--mmmmm +04 IA Rb Ib - - ADD SZ8 EFL=m--mmmmm +05 IA Rv Iz - - ADD EFL=m--mmmmm +06 S Sv - - - PUSH_SEG I64 +07 S Sv - - - POP_SEG I64 +08 MR Eb Gb - - OR LOCK SZ8 EFL=0--mmum0 +09 MR Ev Gv - - OR LOCK EFL=0--mmum0 +0a RM Gb Eb - - OR SZ8 EFL=0--mmum0 +0b RM Gv Ev - - OR EFL=0--mmum0 +0c IA Rb Ib - - OR SZ8 EFL=0--mmum0 +0d IA Rv Iz - - OR EFL=0--mmum0 +0e S Sv - - - PUSH_SEG I64 +#0f escape opcode +10 MR Eb Gb - - ADC LOCK SZ8 EFL=m--mmmmM +11 MR Ev Gv - - ADC LOCK EFL=m--mmmmM +12 RM Gb Eb - - ADC SZ8 EFL=m--mmmmM +13 RM Gv Ev - - ADC EFL=m--mmmmM +14 IA Rb Ib - - ADC SZ8 EFL=m--mmmmM +15 IA Rv Iz - - ADC EFL=m--mmmmM +16 S Sv - - - PUSH_SEG I64 +17 S Sv - - - POP_SEG I64 +18 MR Eb Gb - - SBB LOCK SZ8 EFL=m--mmmmM +19 MR Ev Gv - - SBB LOCK EFL=m--mmmmM +1a RM Gb Eb - - SBB SZ8 EFL=m--mmmmM +1b RM Gv Ev - - SBB EFL=m--mmmmM +1c IA Rb Ib - - SBB SZ8 EFL=m--mmmmM +1d IA Rv Iz - - SBB EFL=m--mmmmM +1e S Sv - - - PUSH_SEG I64 +1f S Sv - - - POP_SEG I64 +20 MR Eb Gb - - AND LOCK SZ8 EFL=0--mmum0 +21 MR Ev Gv - - AND LOCK EFL=0--mmum0 +22 RM Gb Eb - - AND SZ8 EFL=0--mmum0 +23 RM Gv Ev - - AND EFL=0--mmum0 +24 IA Rb Ib - - AND SZ8 EFL=0--mmum0 +25 IA Rv Iz - - AND EFL=0--mmum0 +#26 SEG=ES prefix +27 NP - - - - DAA I64 EFL=u--mmMmM +28 MR Eb Gb - - SUB LOCK SZ8 EFL=m--mmmmm +29 MR Ev Gv - - SUB LOCK EFL=m--mmmmm +2a RM Gb Eb - - SUB SZ8 EFL=m--mmmmm +2b RM Gv Ev - - SUB EFL=m--mmmmm +2c IA Rb Ib - - SUB SZ8 EFL=m--mmmmm +2d IA Rv Iz - - SUB EFL=m--mmmmm +#2e SEG=CS prefix +2f NP - - - - DAS I64 EFL=u--mmMmM +30 MR Eb Gb - - XOR LOCK SZ8 EFL=0--mmum0 +31 MR Ev Gv - - XOR LOCK EFL=0--mmum0 +32 RM Gb Eb - - XOR SZ8 EFL=0--mmum0 +33 RM Gv Ev - - XOR EFL=0--mmum0 +34 IA Rb Ib - - XOR SZ8 EFL=0--mmum0 +35 IA Rv Iz - - XOR EFL=0--mmum0 +#36 SEG=SS prefix +37 NP - - - - AAA I64 EFL=u--uuMum +38 MR Eb Gb - - CMP SZ8 EFL=m--mmmmm +39 MR Ev Gv - - CMP EFL=m--mmmmm +3a RM Gb Eb - - CMP SZ8 EFL=m--mmmmm +3b RM Gv Ev - - CMP EFL=m--mmmmm +3c IA Rb Ib - - CMP SZ8 EFL=m--mmmmm +3d IA Rv Iz - - CMP EFL=m--mmmmm +#3e SEG=DS prefix +3f NP - - - - AAS I64 EFL=u--uuMum +40+ O Rv - - - INC I64 EFL=m--mmmm- +48+ O Rv - - - DEC I64 EFL=m--mmmm- +50+ O Rv - - - PUSH D64 +58+ O Rv - - - POP D64 +60 NP - - - - PUSHA+w I64 +61 NP - - - - POPA+w I64 +62/m RM Gv Ma - - BOUND I64 +63 MR Ew Gw - - ARPL I64 EFL=----m--- +63 RM Gv Ed - - MOVSX O64 F=LM ENC_SEPSZ +#64 SEG=FS prefix +#65 SEG=GS prefix +#66 operand size prefix +#67 address size prefix +68 I Iz - - - PUSH D64 +69 RMI Gv Ev Iz - IMUL EFL=m--uuuum +6a I Ibs - - - PUSH D64 +6b RMI Gv Ev Ibs - IMUL EFL=m--uuuum +6c NP - - - - INS+wa SZ8 ENC_REP EFL=-t------ +6d NP - - - - INS+wa ENC_REP EFL=-t------ +6e NP - - - - OUTS+was SZ8 ENC_REP EFL=-t------ +6f NP - - - - OUTS+was ENC_REP EFL=-t------ +70 D Jbs - - - JO F64 EFL=t------- ENC_CC_BEGIN +71 D Jbs - - - JNO F64 EFL=t------- +72 D Jbs - - - JC F64 EFL=-------t +73 D Jbs - - - JNC F64 EFL=-------t +74 D Jbs - - - JZ F64 EFL=----t--- +75 D Jbs - - - JNZ F64 EFL=----t--- +76 D Jbs - - - JBE F64 EFL=----t--t +77 D Jbs - - - JA F64 EFL=----t--t +78 D Jbs - - - JS F64 EFL=---t---- +79 D Jbs - - - JNS F64 EFL=---t---- +7a D Jbs - - - JP F64 EFL=------t- +7b D Jbs - - - JNP F64 EFL=------t- +7c D Jbs - - - JL F64 EFL=t--t---- +7d D Jbs - - - JGE F64 EFL=t--t---- +7e D Jbs - - - JLE F64 EFL=t--tt--- +7f D Jbs - - - JG F64 EFL=t--tt--- +80/0 MI Eb Ib - - ADD LOCK SZ8 EFL=m--mmmmm +80/1 MI Eb Ib - - OR LOCK SZ8 EFL=0--mmum0 +80/2 MI Eb Ib - - ADC LOCK SZ8 EFL=m--mmmmM +80/3 MI Eb Ib - - SBB LOCK SZ8 EFL=m--mmmmM +80/4 MI Eb Ib - - AND LOCK SZ8 EFL=0--mmum0 +80/5 MI Eb Ib - - SUB LOCK SZ8 EFL=m--mmmmm +80/6 MI Eb Ib - - XOR LOCK SZ8 EFL=0--mmum0 +80/7 MI Eb Ib - - CMP SZ8 EFL=m--mmmmm +81/0 MI Ev Iz - - ADD LOCK EFL=m--mmmmm +81/1 MI Ev Iz - - OR LOCK EFL=0--mmum0 +81/2 MI Ev Iz - - ADC LOCK EFL=m--mmmmM +81/3 MI Ev Iz - - SBB LOCK EFL=m--mmmmM +81/4 MI Ev Iz - - AND LOCK EFL=0--mmum0 +81/5 MI Ev Iz - - SUB LOCK EFL=m--mmmmm +81/6 MI Ev Iz - - XOR LOCK EFL=0--mmum0 +81/7 MI Ev Iz - - CMP EFL=m--mmmmm +82/0 MI Eb Ib - - ADD LOCK I64 SZ8 EFL=m--mmmmm +82/1 MI Eb Ib - - OR LOCK I64 SZ8 EFL=0--mmum0 +82/2 MI Eb Ib - - ADC LOCK I64 SZ8 EFL=m--mmmmM +82/3 MI Eb Ib - - SBB LOCK I64 SZ8 EFL=m--mmmmM +82/4 MI Eb Ib - - AND LOCK I64 SZ8 EFL=0--mmum0 +82/5 MI Eb Ib - - SUB LOCK I64 SZ8 EFL=m--mmmmm +82/6 MI Eb Ib - - XOR LOCK I64 SZ8 EFL=0--mmum0 +82/7 MI Eb Ib - - CMP I64 SZ8 EFL=m--mmmmm +83/0 MI Ev Ibs - - ADD LOCK EFL=m--mmmmm +83/1 MI Ev Ibs - - OR LOCK EFL=0--mmum0 +83/2 MI Ev Ibs - - ADC LOCK EFL=m--mmmmM +83/3 MI Ev Ibs - - SBB LOCK EFL=m--mmmmM +83/4 MI Ev Ibs - - AND LOCK EFL=0--mmum0 +83/5 MI Ev Ibs - - SUB LOCK EFL=m--mmmmm +83/6 MI Ev Ibs - - XOR LOCK EFL=0--mmum0 +83/7 MI Ev Ibs - - CMP EFL=m--mmmmm +84 MR Eb Gb - - TEST SZ8 EFL=0--mmum0 +85 MR Ev Gv - - TEST EFL=0--mmum0 +86 MR Eb Gb - - XCHG LOCK SZ8 +87 MR Ev Gv - - XCHG LOCK +88 MR Eb Gb - - MOV SZ8 +89 MR Ev Gv - - MOV +8a RM Gb Eb - - MOV SZ8 +8b RM Gv Ev - - MOV +# TODO: 8c is actually Ev,Sw; exact semantics are TBD +8c/0 MR Ew Sw - - MOV_S2G +8c/1 MR Ew Sw - - MOV_S2G +8c/2 MR Ew Sw - - MOV_S2G +8c/3 MR Ew Sw - - MOV_S2G +8c/4 MR Ew Sw - - MOV_S2G +8c/5 MR Ew Sw - - MOV_S2G +8d/m RM Gv M - - LEA +8e/0 RM Sw Ew - - MOV_G2S +8e/2 RM Sw Ew - - MOV_G2S +8e/3 RM Sw Ew - - MOV_G2S +8e/4 RM Sw Ew - - MOV_G2S +8e/5 RM Sw Ew - - MOV_G2S +8f/0 M Ev - - - POP D64 +# Against frequent belief, only, XCHG (r/e)AX, (r)AX with 90 is NOP. +# As a lacking REX.B cannot be specified here, this is hardcoded. +90+ OA Rv Rv - - XCHG_NOP +98 NP - - - - C_EX+w +99 NP - - - - C_SEP+w +# Far jmp/call immediate size adjusted in code +9a I Ap - - - CALLF I64 +9b NP - - - - FWAIT +9c NP - - - - PUSHF+w D64 EFL=tttttttt +9d NP - - - - POPF+w D64 EFL=mmmmmmmm +9e NP - - - - SAHF EFL=---mmmmm +9f NP - - - - LAHF EFL=---ttttt +a0 FD Rb Ob - - MOV+as SZ8 +a1 FD Rv Ov - - MOV+as +a2 TD Ob Rb - - MOV+as SZ8 +a3 TD Ov Rv - - MOV+as +a4 NP - - - - MOVS+was SZ8 ENC_REP EFL=-t------ +a5 NP - - - - MOVS+was ENC_REP EFL=-t------ +a6 NP - - - - CMPS+was SZ8 ENC_REPCC EFL=mt-mmmmm +a7 NP - - - - CMPS+was ENC_REPCC EFL=mt-mmmmm +a8 IA Rb Ib - - TEST SZ8 EFL=0--mmum0 +a9 IA Rv Iz - - TEST EFL=0--mmum0 +aa NP - - - - STOS+wa SZ8 ENC_REP EFL=-t------ +ab NP - - - - STOS+wa ENC_REP EFL=-t------ +ac NP - - - - LODS+was SZ8 ENC_REP EFL=-t------ +ad NP - - - - LODS+was ENC_REP EFL=-t------ +ae NP - - - - SCAS+wa SZ8 ENC_REPCC EFL=mt-mmmmm +af NP - - - - SCAS+wa ENC_REPCC EFL=mt-mmmmm +b0+ OI Rb Ib - - MOVABS SZ8 +b8+ OI Rv Iv - - MOVABS +c0/0 MI Eb Ib - - ROL SZ8 EFL=m------m +c0/1 MI Eb Ib - - ROR SZ8 EFL=m------m +c0/2 MI Eb Ib - - RCL SZ8 EFL=m------M +c0/3 MI Eb Ib - - RCR SZ8 EFL=m------M +c0/4 MI Eb Ib - - SHL SZ8 EFL=m--mmumm +c0/5 MI Eb Ib - - SHR SZ8 EFL=m--mmumm +c0/6 MI Eb Ib - - SHL SZ8 EFL=m--mmumm +c0/7 MI Eb Ib - - SAR SZ8 EFL=m--mmumm +c1/0 MI Ev Ib - - ROL EFL=m------m +c1/1 MI Ev Ib - - ROR EFL=m------m +c1/2 MI Ev Ib - - RCL EFL=m------M +c1/3 MI Ev Ib - - RCR EFL=m------M +c1/4 MI Ev Ib - - SHL EFL=m--mmumm +c1/5 MI Ev Ib - - SHR EFL=m--mmumm +c1/6 MI Ev Ib - - SHL EFL=m--mmumm +c1/7 MI Ev Ib - - SAR EFL=m--mmumm +# RET immediate size handled in code +c2 I Iw - - - RET+w F64 +c3 NP - - - - RET+w F64 +c4/m RM Gv Mp - - LES I64 +c5/m RM Gv Mp - - LDS I64 +c6/0 MI Eb Ib - - MOV SZ8 +c6f8 I Ib - - - XABORT F=HLERTM +c7/0 MI Ev Iz - - MOV +c7f8 D Jzd - - - XBEGIN I64 F=HLERTM +c7f8 D Jzq - - - XBEGIN O64 F=HLERTM +# ENTER immediate handled in code, actually it is Iw,Ib +c8 I Id - - - ENTER+w D64 +c9 NP - - - - LEAVE+w D64 +# RETF immediate size handled in code +ca I Iw - - - RETF+w +cb NP - - - - RETF+w +cc NP - - - - INT3 EFL=--M----- +cd I Ib - - - INT EFL=--M----- +ce NP - - - - INTO I64 EFL=t-M----- +cf NP - - - - IRET+w EFL=mmmmmmmm +d0/0 M1 Eb Ib - - ROL SZ8 EFL=m------m +d0/1 M1 Eb Ib - - ROR SZ8 EFL=m------m +d0/2 M1 Eb Ib - - RCL SZ8 EFL=m------M +d0/3 M1 Eb Ib - - RCR SZ8 EFL=m------M +d0/4 M1 Eb Ib - - SHL SZ8 EFL=m--mmumm +d0/5 M1 Eb Ib - - SHR SZ8 EFL=m--mmumm +d0/6 M1 Eb Ib - - SHL SZ8 EFL=m--mmumm +d0/7 M1 Eb Ib - - SAR SZ8 EFL=m--mmumm +d1/0 M1 Ev Ib - - ROL EFL=m------m +d1/1 M1 Ev Ib - - ROR EFL=m------m +d1/2 M1 Ev Ib - - RCL EFL=m------M +d1/3 M1 Ev Ib - - RCR EFL=m------M +d1/4 M1 Ev Ib - - SHL EFL=m--mmumm +d1/5 M1 Ev Ib - - SHR EFL=m--mmumm +d1/6 M1 Ev Ib - - SHL EFL=m--mmumm +d1/7 M1 Ev Ib - - SAR EFL=m--mmumm +d2/0 MC Eb Rb - - ROL SZ8 EFL=m------m +d2/1 MC Eb Rb - - ROR SZ8 EFL=m------m +d2/2 MC Eb Rb - - RCL SZ8 EFL=m------M +d2/3 MC Eb Rb - - RCR SZ8 EFL=m------M +d2/4 MC Eb Rb - - SHL SZ8 EFL=m--mmumm +d2/5 MC Eb Rb - - SHR SZ8 EFL=m--mmumm +d2/6 MC Eb Rb - - SHL SZ8 EFL=m--mmumm +d2/7 MC Eb Rb - - SAR SZ8 EFL=m--mmumm +d3/0 MC Ev Rb - - ROL EFL=m------m +d3/1 MC Ev Rb - - ROR EFL=m------m +d3/2 MC Ev Rb - - RCL EFL=m------M +d3/3 MC Ev Rb - - RCR EFL=m------M +d3/4 MC Ev Rb - - SHL EFL=m--mmumm +d3/5 MC Ev Rb - - SHR EFL=m--mmumm +d3/6 MC Ev Rb - - SHL EFL=m--mmumm +d3/7 MC Ev Rb - - SAR EFL=m--mmumm +d4 I Ib - - - AAM I64 SZ8 EFL=u--mmumu +d5 I Ib - - - AAD I64 SZ8 EFL=u--mmumu +d6 NP - - - - SALC I64 UNDOC +d7 NP - - - - XLATB+as +#d8-df FPU Escape +e0 D Jbs - - - LOOPNZ+a F64 EFL=----t--- +e1 D Jbs - - - LOOPZ+a F64 EFL=----t--- +e2 D Jbs - - - LOOP+a F64 +e3 D Jbs - - - JCXZ+a F64 +e4 IA Rb Ib - - IN SZ8 +e5 IA Rz Ib - - IN +e6 IA Rb Ib - - OUT SZ8 +e7 IA Rz Ib - - OUT +e8 D Jz - - - CALL F64 +e9 D Jz - - - JMP F64 +# Far jmp/call immediate size adjusted in code +ea I Ap - - - JMPF I64 +eb D Jbs - - - JMP F64 +ec NP - - - - IN+w SZ8 +ed NP - - - - IN+w +ee NP - - - - OUT+w SZ8 +ef NP - - - - OUT+w +#f0 prefix +f1 NP - - - - INT1 EFL=--M----- +#f2 REPNZ prefix +#f3 REP/REPZ prefix +f4 NP - - - - HLT CPL0 +f5 NP - - - - CMC EFL=-------M +f6/0 MI Eb Ib - - TEST SZ8 EFL=0--mmum0 +f6/1 MI Eb Ib - - TEST SZ8 EFL=0--mmum0 +f6/2 M Eb - - - NOT LOCK SZ8 +f6/3 M Eb - - - NEG LOCK SZ8 EFL=m--mmmmm +f6/4 M Eb - - - MUL SZ8 EFL=m--uuuum +f6/5 M Eb - - - IMUL SZ8 EFL=m--uuuum +f6/6 M Eb - - - DIV SZ8 EFL=u--uuuuu +f6/7 M Eb - - - IDIV SZ8 EFL=u--uuuuu +f7/0 MI Ev Iz - - TEST EFL=0--mmum0 +f7/1 MI Ev Iz - - TEST EFL=0--mmum0 +f7/2 M Ev - - - NOT LOCK +f7/3 M Ev - - - NEG LOCK EFL=m--mmmmm +f7/4 M Ev - - - MUL EFL=m--uuuum +f7/5 M Ev - - - IMUL EFL=m--uuuum +f7/6 M Ev - - - DIV EFL=u--uuuuu +f7/7 M Ev - - - IDIV EFL=u--uuuuu +f8 NP - - - - CLC EFL=-------0 +f9 NP - - - - STC EFL=-------1 +fa NP - - - - CLI EFL=--0----- +fb NP - - - - STI EFL=--1----- +fc NP - - - - CLD EFL=-0------ +fd NP - - - - STD EFL=-1------ +fe/0 M Eb - - - INC LOCK SZ8 EFL=m--mmmm- +fe/1 M Eb - - - DEC LOCK SZ8 EFL=m--mmmm- +ff/0 M Ev - - - INC LOCK EFL=m--mmmm- +ff/1 M Ev - - - DEC LOCK EFL=m--mmmm- +ff/2 M Ev - - - CALL F64 +ff/3m M Mp - - - CALLF +ff/4 M Ev - - - JMP F64 +ff/5m M Mp - - - JMPF +ff/6 M Ev - - - PUSH D64 +# TODO: SDM states taht SLDT/STR are Rv/Mw (like SMSW), but semantics not verified +0f00/0 M Ew - - - SLDT +0f00/1 M Ew - - - STR +0f00/2 M Ew - - - LLDT CPL0 +0f00/3 M Ew - - - LTR CPL0 +0f00/4 M Ew - - - VERR EFL=----m--- +0f00/5 M Ew - - - VERW EFL=----m--- +0f01/0m M M - - - SGDT +0f01/1m M M - - - SIDT +0f01/2m M M - - - LGDT CPL0 +0f01/3m M M - - - LIDT CPL0 +0f01/4m M Mw - - - SMSW +0f01/4r M Rv - - - SMSW +0f01/6 M Ew - - - LMSW CPL0 +0f01/7m M Mb - - - INVLPG SZ8 F=486 CPL0 +NP.0f01c0 NP - - - - ENCLV F=SGX +NP.0f01c8 NP - - - - MONITOR F=MONITOR +NP.0f01c9 NP - - - - MWAIT F=MONITOR +NP.0f01ca NP - - - - CLAC F=SMAP CPL0 +NP.0f01cb NP - - - - STAC F=SMAP CPL0 +NP.0f01cf NP - - - - ENCLS F=SGX +NP.0f01d0 NP - - - - XGETBV F=XSAVE +NP.0f01d1 NP - - - - XSETBV F=XSAVE +NP.0f01d5 NP - - - - XEND F=HLERTM +NP.0f01d6 NP - - - - XTEST F=HLERTM EFL=0--0m000 +NP.0f01d7 NP - - - - ENCLU F=SGX +0f01f8 NP - - - - SWAPGS O64 F=LM +0f01f9 NP - - - - RDTSCP F=RDTSCP +0f02 RM Gv Ew - - LAR EFL=----m--- +0f03 RM Gv Ew - - LSL EFL=----m--- +0f05 NP - - - - SYSCALL O64 F=LM EFL=MMMMMMMM +0f06 NP - - - - CLTS CPL0 +0f07 NP - - - - SYSRET O64 F=LM CPL0 EFL=mmmmmmmm +0f08 NP - - - - INVD F=486 CPL0 +*0f09 NP - - - - WBINVD F=486 CPL0 +0f0b NP - - - - UD2 +0f0d/0m M Mb - - - PREFETCH F=PREFETCH +0f0d/1m M Mb - - - PREFETCHW F=PREFETCHW +0f0d/2m M Mb - - - PREFETCHWT1 F=PREFETCHWT1 +# All other slots are reserved, AMD maps them to /0 +*0f0d/m M Mb - - - RESERVED_PREFETCH ONLYAMD F=PREFETCH +*0f0d/r MR Rv Gv - - RESERVED_NOP +0f0e NP - - - - FEMMS ONLYAMD F=3DNOW +# TODO: actually decode 3DNow! instructions. Given that 3DNow! no longer exists, +# this is unlikely to happen, though. +0f0f RMI Pq Qq Ib - 3DNOW ONLYAMD F=3DNOW +0f18/0m M Mb - - - PREFETCHNTA F=SSE +0f18/1m M Mb - - - PREFETCHT0 F=SSE +0f18/2m M Mb - - - PREFETCHT1 F=SSE +0f18/3m M Mb - - - PREFETCHT2 F=SSE +0f18/6m M Mb - - - PREFETCHIT1 O64 F=PREFETCHI +0f18/7m M Mb - - - PREFETCHIT0 O64 F=PREFETCHI +# Reserved NOPs are weak, they can be overridden by other instructions. +*0f18 MR Ev Gv - - RESERVED_NOP +*0f19 MR Ev Gv - - RESERVED_NOP +*0f1a MR Ev Gv - - RESERVED_NOP +*0f1b MR Ev Gv - - RESERVED_NOP +*0f1c MR Ev Gv - - RESERVED_NOP +*0f1d MR Ev Gv - - RESERVED_NOP +*0f1e MR Ev Gv - - RESERVED_NOP +*0f1f MR Ev Gv - - RESERVED_NOP +0f1f/0 M Ev - - - NOP +0f20 MR Ry Cy - - MOV_CR2G I66 D64 CPL0 EFL=u--uuuuu +0f21 MR Ry Dy - - MOV_DR2G I66 D64 CPL0 EFL=u--uuuuu +0f22 RM Cy Ry - - MOV_G2CR I66 D64 CPL0 EFL=u--uuuuu +0f23 RM Dy Ry - - MOV_G2DR I66 D64 CPL0 EFL=u--uuuuu +0f30 NP - - - - WRMSR F=586 CPL0 +0f31 NP - - - - RDTSC F=586 +0f32 NP - - - - RDMSR F=586 CPL0 +0f33 NP - - - - RDPMC F=686 +0f34 NP - - - - SYSENTER F=686 EFL=--m----- +0f35 NP - - - - SYSEXIT F=686 CPL0 +NP.0f37 NP - - - - GETSEC F=SMX EFL=MMMMMMMM +# 0f38, 0f3a are escape opcodes +0f40 RM Gv Ev - - CMOVO F=CMOV EFL=t------- ENC_CC_BEGIN +0f41 RM Gv Ev - - CMOVNO F=CMOV EFL=t------- +0f42 RM Gv Ev - - CMOVC F=CMOV EFL=-------t +0f43 RM Gv Ev - - CMOVNC F=CMOV EFL=-------t +0f44 RM Gv Ev - - CMOVZ F=CMOV EFL=----t--- +0f45 RM Gv Ev - - CMOVNZ F=CMOV EFL=----t--- +0f46 RM Gv Ev - - CMOVBE F=CMOV EFL=----t--t +0f47 RM Gv Ev - - CMOVA F=CMOV EFL=----t--t +0f48 RM Gv Ev - - CMOVS F=CMOV EFL=---t---- +0f49 RM Gv Ev - - CMOVNS F=CMOV EFL=---t---- +0f4a RM Gv Ev - - CMOVP F=CMOV EFL=------t- +0f4b RM Gv Ev - - CMOVNP F=CMOV EFL=------t- +0f4c RM Gv Ev - - CMOVL F=CMOV EFL=t--t---- +0f4d RM Gv Ev - - CMOVGE F=CMOV EFL=t--t---- +0f4e RM Gv Ev - - CMOVLE F=CMOV EFL=t--tt--- +0f4f RM Gv Ev - - CMOVG F=CMOV EFL=t--tt--- +0f80 D Jz - - - JO F64 EFL=t------- ENC_CC_BEGIN +0f81 D Jz - - - JNO F64 EFL=t------- +0f82 D Jz - - - JC F64 EFL=-------t +0f83 D Jz - - - JNC F64 EFL=-------t +0f84 D Jz - - - JZ F64 EFL=----t--- +0f85 D Jz - - - JNZ F64 EFL=----t--- +0f86 D Jz - - - JBE F64 EFL=----t--t +0f87 D Jz - - - JA F64 EFL=----t--t +0f88 D Jz - - - JS F64 EFL=---t---- +0f89 D Jz - - - JNS F64 EFL=---t---- +0f8a D Jz - - - JP F64 EFL=------t- +0f8b D Jz - - - JNP F64 EFL=------t- +0f8c D Jz - - - JL F64 EFL=t--t---- +0f8d D Jz - - - JGE F64 EFL=t--t---- +0f8e D Jz - - - JLE F64 EFL=t--tt--- +0f8f D Jz - - - JG F64 EFL=t--tt--- +0f90 M Eb - - - SETO SZ8 EFL=t------- ENC_CC_BEGIN +0f91 M Eb - - - SETNO SZ8 EFL=t------- +0f92 M Eb - - - SETC SZ8 EFL=-------t +0f93 M Eb - - - SETNC SZ8 EFL=-------t +0f94 M Eb - - - SETZ SZ8 EFL=----t--- +0f95 M Eb - - - SETNZ SZ8 EFL=----t--- +0f96 M Eb - - - SETBE SZ8 EFL=----t--t +0f97 M Eb - - - SETA SZ8 EFL=----t--t +0f98 M Eb - - - SETS SZ8 EFL=---t---- +0f99 M Eb - - - SETNS SZ8 EFL=---t---- +0f9a M Eb - - - SETP SZ8 EFL=------t- +0f9b M Eb - - - SETNP SZ8 EFL=------t- +0f9c M Eb - - - SETL SZ8 EFL=t--t---- +0f9d M Eb - - - SETGE SZ8 EFL=t--t---- +0f9e M Eb - - - SETLE SZ8 EFL=t--tt--- +0f9f M Eb - - - SETG SZ8 EFL=t--tt--- +0fa0 S Sv - - - PUSH_SEG D64 +0fa1 S Sv - - - POP_SEG D64 +0fa2 NP - - - - CPUID F=586 +0fa3 MR Ev Gv - - BT EFL=u--u-uum +0fa4 MRI Ev Gv Ib - SHLD EFL=u--mmumm +0fa5 MRC Ev Gv Rb - SHLD EFL=u--mmumm +0fa8 S Sv - - - PUSH_SEG D64 +0fa9 S Sv - - - POP_SEG D64 +0faa NP - - - - RSM F=586 +0fab MR Ev Gv - - BTS LOCK EFL=u--u-uum +0fac MRI Ev Gv Ib - SHRD EFL=u--mmumm +0fad MRC Ev Gv Rb - SHRD EFL=u--mmumm +0faf RM Gv Ev - - IMUL EFL=m--uuuum +0fb0 MR Eb Gb - - CMPXCHG LOCK SZ8 F=486 EFL=m--mmmmm +0fb1 MR Ev Gv - - CMPXCHG LOCK F=486 EFL=m--mmmmm +0fb2/m RM Gv Mp - - LSS +0fb3 MR Ev Gv - - BTR LOCK EFL=u--u-uum +0fb4/m RM Gv Mp - - LFS +0fb5/m RM Gv Mp - - LGS +0fb6 RM Gv Eb - - MOVZX ENC_SEPSZ +0fb7 RM Gv Ew - - MOVZX ENC_SEPSZ +F3.0fb8 RM Gv Ev - - POPCNT U66 F=POPCNT EFL=0--0m000 +0fb9 RM Gv Ev - - UD1 +0fba/4 MI Ev Ib - - BT EFL=u--u-uum +0fba/5 MI Ev Ib - - BTS LOCK EFL=u--u-uum +0fba/6 MI Ev Ib - - BTR LOCK EFL=u--u-uum +0fba/7 MI Ev Ib - - BTC LOCK EFL=u--u-uum +0fbb MR Ev Gv - - BTC LOCK EFL=u--u-uum +*0fbc RM Gv Ev - - BSF EFL=u--umuuu +F3.0fbc RM Gv Ev - - TZCNT U66 F=BMI1 EFL=u--umuum +*0fbd RM Gv Ev - - BSR EFL=u--umuuu +F3.0fbd RM Gv Ev - - LZCNT U66 F=LZCNT EFL=u--umuum +0fbe RM Gv Eb - - MOVSX ENC_SEPSZ +0fbf RM Gv Ew - - MOVSX ENC_SEPSZ +0fc0 MR Eb Gb - - XADD LOCK SZ8 F=486 EFL=m--mmmmm +0fc1 MR Ev Gv - - XADD LOCK F=486 EFL=m--mmmmm +NP.0fc3/m MR My Gy - - MOVNTI F=SSE2 +0fc7/1m M M - - - CMPXCHGD+w LOCK I66 F=586 EFL=----m--- +0fc8+ O Rv - - - BSWAP F=486 +0fff RM Gv Ev - - UD0 +# +NFx.0f38f0/m RM Gv Mv - - MOVBE F=MOVBE +F2.0f38f0 RM Gd Eb - - CRC32 SZ8 F=SSE42 +NFx.0f38f1/m MR Mv Gv - - MOVBE F=MOVBE +F2.0f38f1 RM Gd Ev - - CRC32 U66 F=SSE42 +# +# MMX +NP.0f2a RM Vq Qq - - MMX_CVTPI2PS F=SSE2 +66.0f2a RM Vdq Qq - - MMX_CVTPI2PD F=SSE2 +NP.0f2c RM Pq Wq - - MMX_CVTTPS2PI F=SSE2 +66.0f2c RM Pq Wdq - - MMX_CVTTPD2PI F=SSE2 +NP.0f2d RM Pq Wq - - MMX_CVTPS2PI F=SSE2 +66.0f2d RM Pq Wdq - - MMX_CVTPD2PI F=SSE2 +NP.0f60 RM Pq Qd - - MMX_PUNPCKLBW F=MMX +NP.0f61 RM Pq Qd - - MMX_PUNPCKLWD F=MMX +NP.0f62 RM Pq Qd - - MMX_PUNPCKLDQ F=MMX +NP.0f63 RM Pq Qq - - MMX_PACKSSWB F=MMX +NP.0f64 RM Pq Qq - - MMX_PCMPGTB F=MMX +NP.0f65 RM Pq Qq - - MMX_PCMPGTW F=MMX +NP.0f66 RM Pq Qq - - MMX_PCMPGTD F=MMX +NP.0f67 RM Pq Qq - - MMX_PACKUSWB F=MMX +NP.0f68 RM Pq Qq - - MMX_PUNPCKHBW F=MMX +NP.0f69 RM Pq Qq - - MMX_PUNPCKHWD F=MMX +NP.0f6a RM Pq Qq - - MMX_PUNPCKHDQ F=MMX +NP.0f6b RM Pq Qq - - MMX_PACKSSDW F=MMX +NP.W0.0f6e RM Pq Ey - - MMX_MOVD_G2M F=MMX ENC_NOSZ +NP.W1.0f6e RM Pq Ey - - MMX_MOVQ_G2M F=MMX ENC_NOSZ +NP.0f6f RM Pq Qq - - MMX_MOVQ F=MMX +NP.0f70 RMI Pq Qq Ib - MMX_PSHUFW F=SSE +NP.0f71/2r MI Nq Ib - - MMX_PSRLW F=MMX +NP.0f71/4r MI Nq Ib - - MMX_PSRAW F=MMX +NP.0f71/6r MI Nq Ib - - MMX_PSLLW F=MMX +NP.0f72/2r MI Nq Ib - - MMX_PSRLD F=MMX +NP.0f72/4r MI Nq Ib - - MMX_PSRAD F=MMX +NP.0f72/6r MI Nq Ib - - MMX_PSLLD F=MMX +NP.0f73/2r MI Nq Ib - - MMX_PSRLQ F=MMX +NP.0f73/6r MI Nq Ib - - MMX_PSLLQ F=MMX +NP.0f74 RM Pq Qq - - MMX_PCMPEQB F=MMX +NP.0f75 RM Pq Qq - - MMX_PCMPEQW F=MMX +NP.0f76 RM Pq Qq - - MMX_PCMPEQD F=MMX +NP.0f77 NP - - - - MMX_EMMS F=MMX +NP.W0.0f7e MR Ey Py - - MMX_MOVD_M2G F=MMX ENC_NOSZ +NP.W1.0f7e MR Ey Py - - MMX_MOVQ_M2G F=MMX ENC_NOSZ +NP.0f7f MR Qq Pq - - MMX_MOVQ F=MMX +NP.0fc4 RMI Pq Ew Ib - MMX_PINSRW F=SSE ENC_NOSZ +NP.0fc5/r RMI Gy Nq Ib - MMX_PEXTRW D64 F=SSE +NP.0fd1 RM Pq Qq - - MMX_PSRLW F=MMX +NP.0fd2 RM Pq Qq - - MMX_PSRLD F=MMX +NP.0fd3 RM Pq Qq - - MMX_PSRLQ F=MMX +NP.0fd4 RM Pq Qq - - MMX_PADDQ F=MMX +NP.0fd5 RM Pq Qq - - MMX_PMULLW F=MMX +F2.0fd6/r RM Pq Uq - - MMX_MOVDQ2Q F=SSE +F3.0fd6/r RM Vdq Nq - - MMX_MOVQ2DQ F=SSE +NP.0fd7/r RM Gv Nq - - MMX_PMOVMSKB D64 F=SSE +NP.0fd8 RM Pq Qq - - MMX_PSUBUSB F=MMX +NP.0fd9 RM Pq Qq - - MMX_PSUBUSW F=MMX +NP.0fda RM Pq Qq - - MMX_PMINUB F=SSE +NP.0fdb RM Pq Qq - - MMX_PAND F=MMX +NP.0fdc RM Pq Qq - - MMX_PADDUSB F=MMX +NP.0fdd RM Pq Qq - - MMX_PADDUSW F=MMX +NP.0fde RM Pq Qq - - MMX_PMAXUB F=SSE +NP.0fdf RM Pq Qq - - MMX_PANDN F=MMX +NP.0fe0 RM Pq Qq - - MMX_PAVGB F=SSE +NP.0fe1 RM Pq Qq - - MMX_PSRAW F=MMX +NP.0fe2 RM Pq Qq - - MMX_PSRAD F=MMX +NP.0fe3 RM Pq Qq - - MMX_PAVGW F=SSE +NP.0fe4 RM Pq Qq - - MMX_PMULHUW F=SSE +NP.0fe5 RM Pq Qq - - MMX_PMULHW F=MMX +NP.0fe7/m MR Mq Pq - - MMX_MOVNTQ F=SSE +NP.0fe8 RM Pq Qq - - MMX_PSUBSB F=MMX +NP.0fe9 RM Pq Qq - - MMX_PSUBSW F=MMX +NP.0feb RM Pq Qq - - MMX_POR F=MMX +NP.0fec RM Pq Qq - - MMX_PADDSB F=MMX +NP.0fea RM Pq Qq - - MMX_PMINSW F=SSE +NP.0fee RM Pq Qq - - MMX_PMAXSW F=SSE +NP.0fed RM Pq Qq - - MMX_PADDSW F=MMX +NP.0fef RM Pq Qq - - MMX_PXOR F=MMX +NP.0ff1 RM Pq Qq - - MMX_PSLLW F=MMX +NP.0ff2 RM Pq Qq - - MMX_PSLLD F=MMX +NP.0ff3 RM Pq Qq - - MMX_PSLLQ F=MMX +NP.0ff4 RM Pq Qq - - MMX_PMULUDQ F=MMX +NP.0ff5 RM Pq Qq - - MMX_PMADDWD F=MMX +NP.0ff6 RM Pq Qq - - MMX_PSADBW F=SSE +NP.0ff7/r RM Pq Nq - - MMX_MASKMOVQ+as F=SSE +NP.0ff8 RM Pq Qq - - MMX_PSUBB F=MMX +NP.0ff9 RM Pq Qq - - MMX_PSUBW F=MMX +NP.0ffa RM Pq Qq - - MMX_PSUBD F=MMX +NP.0ffb RM Pq Qq - - MMX_PSUBQ F=MMX +NP.0ffc RM Pq Qq - - MMX_PADDB F=MMX +NP.0ffd RM Pq Qq - - MMX_PADDW F=MMX +NP.0ffe RM Pq Qq - - MMX_PADDD F=MMX +NP.0f3800 RM Pq Qq - - MMX_PSHUFB F=SSSE3 +NP.0f3801 RM Pq Qq - - MMX_PHADDW F=SSSE3 +NP.0f3802 RM Pq Qq - - MMX_PHADDD F=SSSE3 +NP.0f3803 RM Pq Qq - - MMX_PHADDSW F=SSSE3 +NP.0f3804 RM Pq Qq - - MMX_PMADDUBSW F=SSSE3 +NP.0f3805 RM Pq Qq - - MMX_PHSUBW F=SSSE3 +NP.0f3806 RM Pq Qq - - MMX_PHSUBD F=SSSE3 +NP.0f3807 RM Pq Qq - - MMX_PHSUBSW F=SSSE3 +NP.0f3808 RM Pq Qq - - MMX_PSIGNB F=SSSE3 +NP.0f3809 RM Pq Qq - - MMX_PSIGNW F=SSSE3 +NP.0f380a RM Pq Qq - - MMX_PSIGND F=SSSE3 +NP.0f380b RM Pq Qq - - MMX_PMULHRSW F=SSSE3 +NP.0f381c RM Pq Qq - - MMX_PABSB F=SSSE3 +NP.0f381d RM Pq Qq - - MMX_PABSW F=SSSE3 +NP.0f381e RM Pq Qq - - MMX_PABSD F=SSSE3 +NP.0f3a0f RMI Pq Qq Ib - MMX_PALIGNR F=SSSE3 +# +# SSE +NP.0f10 RM Vps Wps - - SSE_MOVUPS F=SSE +66.0f10 RM Vpd Wpd - - SSE_MOVUPD F=SSE2 +# MOVSS/MOVSD reg,mem set the full XMM register +F3.0f10 RM Vx Wss - - SSE_MOVSS F=SSE +F2.0f10 RM Vx Wsd - - SSE_MOVSD F=SSE2 +NP.0f11 MR Wps Vps - - SSE_MOVUPS F=SSE +66.0f11 MR Wpd Vpd - - SSE_MOVUPD F=SSE2 +F3.0f11 MR Wss Vss - - SSE_MOVSS F=SSE +F2.0f11 MR Wsd Vsd - - SSE_MOVSD F=SSE2 +NP.0f12/m RM Vx Mq - - SSE_MOVLPS F=SSE +NP.0f12/r RM Vx Ux - - SSE_MOVHLPS F=SSE +66.0f12/m RM Vx Mq - - SSE_MOVLPD F=SSE2 +F3.0f12 RM Vx Wx - - SSE_MOVSLDUP F=SSE3 +F2.0f12 RM Vx Wq - - SSE_MOVDDUP F=SSE3 +NP.0f13/m MR Mq Vq - - SSE_MOVLPS F=SSE +66.0f13/m MR Mq Vq - - SSE_MOVLPD F=SSE2 +NP.0f14 RM Vps Wps - - SSE_UNPCKLPS F=SSE +66.0f14 RM Vpd Wpd - - SSE_UNPCKLPD F=SSE2 +NP.0f15 RM Vps Wps - - SSE_UNPCKHPS F=SSE +66.0f15 RM Vpd Wpd - - SSE_UNPCKHPD F=SSE2 +NP.0f16/m RM Vx Mq - - SSE_MOVHPS F=SSE +NP.0f16/r RM Vx Uq - - SSE_MOVLHPS F=SSE +66.0f16/m RM Vdq Mq - - SSE_MOVHPD F=SSE2 +F3.0f16 RM Vx Wx - - SSE_MOVSHDUP F=SSE3 +NP.0f17/m MR Mq Vx - - SSE_MOVHPS F=SSE +66.0f17/m MR Mq Vx - - SSE_MOVHPD F=SSE2 +NP.0f28 RM Vps Wps - - SSE_MOVAPS F=SSE +66.0f28 RM Vpd Wpd - - SSE_MOVAPD F=SSE2 +NP.0f29 MR Wps Vps - - SSE_MOVAPS F=SSE +66.0f29 MR Wpd Vpd - - SSE_MOVAPD F=SSE2 +F3.0f2a RM Vss Ey - - SSE_CVTSI2SS F=SSE +F2.0f2a RM Vsd Ey - - SSE_CVTSI2SD F=SSE2 +NP.0f2b/m MR Mps Vps - - SSE_MOVNTPS F=SSE +66.0f2b/m MR Mpd Vpd - - SSE_MOVNTPD F=SSE2 +F3.0f2b/m MR Mss Vss - - SSE_MOVNTSS F=SSE ONLYAMD +F2.0f2b/m MR Msd Vsd - - SSE_MOVNTSD F=SSE2 ONLYAMD +F3.0f2c RM Gy Wss - - SSE_CVTTSS2SI F=SSE +F2.0f2c RM Gy Wsd - - SSE_CVTTSD2SI F=SSE2 +F3.0f2d RM Gy Wss - - SSE_CVTSS2SI F=SSE +F2.0f2d RM Gy Wsd - - SSE_CVTSD2SI F=SSE2 +NP.0f2e RM Vss Wss - - SSE_UCOMISS F=SSE EFL=0--0m0mm +66.0f2e RM Vsd Wsd - - SSE_UCOMISD F=SSE2 EFL=0--0m0mm +NP.0f2f RM Vss Wss - - SSE_COMISS F=SSE EFL=0--0m0mm +66.0f2f RM Vsd Wsd - - SSE_COMISD F=SSE2 EFL=0--0m0mm +NP.0f50/r RM Gy Udq - - SSE_MOVMSKPS D64 F=SSE +66.0f50/r RM Gy Udq - - SSE_MOVMSKPD D64 F=SSE2 +NP.0f51 RM Vps Wps - - SSE_SQRTPS F=SSE +66.0f51 RM Vpd Wpd - - SSE_SQRTPD F=SSE2 +F3.0f51 RM Vss Wss - - SSE_SQRTSS F=SSE +F2.0f51 RM Vsd Wsd - - SSE_SQRTSD F=SSE2 +NP.0f52 RM Vps Wps - - SSE_RSQRTPS F=SSE +F3.0f52 RM Vss Wss - - SSE_RSQRTSS F=SSE +NP.0f53 RM Vps Wps - - SSE_RCPPS F=SSE +F3.0f53 RM Vss Wss - - SSE_RCPSS F=SSE +NP.0f54 RM Vps Wps - - SSE_ANDPS F=SSE +66.0f54 RM Vpd Wpd - - SSE_ANDPD F=SSE2 +NP.0f55 RM Vps Wps - - SSE_ANDNPS F=SSE +66.0f55 RM Vpd Wpd - - SSE_ANDNPD F=SSE2 +NP.0f56 RM Vps Wps - - SSE_ORPS F=SSE +66.0f56 RM Vpd Wpd - - SSE_ORPD F=SSE2 +NP.0f57 RM Vps Wps - - SSE_XORPS F=SSE +66.0f57 RM Vpd Wpd - - SSE_XORPD F=SSE2 +NP.0f58 RM Vps Wps - - SSE_ADDPS F=SSE +66.0f58 RM Vpd Wpd - - SSE_ADDPD F=SSE2 +F3.0f58 RM Vss Wss - - SSE_ADDSS F=SSE +F2.0f58 RM Vsd Wsd - - SSE_ADDSD F=SSE2 +NP.0f59 RM Vps Wps - - SSE_MULPS F=SSE +66.0f59 RM Vpd Wpd - - SSE_MULPD F=SSE2 +F3.0f59 RM Vss Wss - - SSE_MULSS F=SSE +F2.0f59 RM Vsd Wsd - - SSE_MULSD F=SSE2 +NP.0f5a RM Vpd Wq - - SSE_CVTPS2PD F=SSE2 +66.0f5a RM Vps Wpd - - SSE_CVTPD2PS F=SSE2 +F3.0f5a RM Vsd Wss - - SSE_CVTSS2SD F=SSE2 +F2.0f5a RM Vss Wsd - - SSE_CVTSD2SS F=SSE2 +NP.0f5b RM Vps Wdq - - SSE_CVTDQ2PS F=SSE2 +66.0f5b RM Vdq Wps - - SSE_CVTPS2DQ F=SSE2 +F3.0f5b RM Vdq Wps - - SSE_CVTTPS2DQ F=SSE2 +NP.0f5c RM Vps Wps - - SSE_SUBPS F=SSE +66.0f5c RM Vpd Wpd - - SSE_SUBPD F=SSE2 +F3.0f5c RM Vss Wss - - SSE_SUBSS F=SSE +F2.0f5c RM Vsd Wsd - - SSE_SUBSD F=SSE2 +NP.0f5d RM Vps Wps - - SSE_MINPS F=SSE +66.0f5d RM Vpd Wpd - - SSE_MINPD F=SSE2 +F3.0f5d RM Vss Wss - - SSE_MINSS F=SSE +F2.0f5d RM Vsd Wsd - - SSE_MINSD F=SSE2 +NP.0f5e RM Vps Wps - - SSE_DIVPS F=SSE +66.0f5e RM Vpd Wpd - - SSE_DIVPD F=SSE2 +F3.0f5e RM Vss Wss - - SSE_DIVSS F=SSE +F2.0f5e RM Vsd Wsd - - SSE_DIVSD F=SSE2 +NP.0f5f RM Vps Wps - - SSE_MAXPS F=SSE +66.0f5f RM Vpd Wpd - - SSE_MAXPD F=SSE2 +F3.0f5f RM Vss Wss - - SSE_MAXSS F=SSE +F2.0f5f RM Vsd Wsd - - SSE_MAXSD F=SSE2 +66.0f60 RM Vx Wx - - SSE_PUNPCKLBW F=SSE2 +66.0f61 RM Vx Wx - - SSE_PUNPCKLWD F=SSE2 +66.0f62 RM Vx Wx - - SSE_PUNPCKLDQ F=SSE2 +66.0f63 RM Vx Wx - - SSE_PACKSSWB F=SSE2 +66.0f64 RM Vx Wx - - SSE_PCMPGTB F=SSE2 +66.0f65 RM Vx Wx - - SSE_PCMPGTW F=SSE2 +66.0f66 RM Vx Wx - - SSE_PCMPGTD F=SSE2 +66.0f67 RM Vx Wx - - SSE_PACKUSWB F=SSE2 +66.0f68 RM Vx Wx - - SSE_PUNPCKHBW F=SSE2 +66.0f69 RM Vx Wx - - SSE_PUNPCKHWD F=SSE2 +66.0f6a RM Vx Wx - - SSE_PUNPCKHDQ F=SSE2 +66.0f6b RM Vx Wx - - SSE_PACKSSDW F=SSE2 +66.0f6c RM Vx Wx - - SSE_PUNPCKLQDQ F=SSE2 +66.0f6d RM Vx Wx - - SSE_PUNPCKHQDQ F=SSE2 +66.W0.0f6e RM Vx Ed - - SSE_MOVD_G2X F=SSE2 ENC_NOSZ +66.W1.0f6e RM Vx Eq - - SSE_MOVQ_G2X F=SSE2 ENC_NOSZ +66.0f6f RM Vx Wx - - SSE_MOVDQA F=SSE2 +F3.0f6f RM Vx Wx - - SSE_MOVDQU F=SSE2 +66.0f70 RMI Vx Wx Ib - SSE_PSHUFD F=SSE2 +F3.0f70 RMI Vx Wx Ib - SSE_PSHUFHW F=SSE2 +F2.0f70 RMI Vx Wx Ib - SSE_PSHUFLW F=SSE2 +66.0f71/2r MI Ux Ib - - SSE_PSRLW F=SSE2 +66.0f71/4r MI Ux Ib - - SSE_PSRAW F=SSE2 +66.0f71/6r MI Ux Ib - - SSE_PSLLW F=SSE2 +66.0f72/2r MI Ux Ib - - SSE_PSRLD F=SSE2 +66.0f72/4r MI Ux Ib - - SSE_PSRAD F=SSE2 +66.0f72/6r MI Ux Ib - - SSE_PSLLD F=SSE2 +66.0f73/2r MI Ux Ib - - SSE_PSRLQ F=SSE2 +66.0f73/3r MI Ux Ib - - SSE_PSRLDQ F=SSE2 +66.0f73/6r MI Ux Ib - - SSE_PSLLQ F=SSE2 +66.0f73/7r MI Ux Ib - - SSE_PSLLDQ F=SSE2 +66.0f74 RM Vx Wx - - SSE_PCMPEQB F=SSE2 +66.0f75 RM Vx Wx - - SSE_PCMPEQW F=SSE2 +66.0f76 RM Vx Wx - - SSE_PCMPEQD F=SSE2 +# EXTRQ/INSERTQ immediate size handled in code. +66.0f78/0r MI Ux Iw - - SSE_EXTRQ F=SSE4A ONLYAMD +F2.0f78/r RMI Vx Ux Iw - SSE_INSERTQ F=SSE4A ONLYAMD +66.0f79/r RM Vx Ux - - SSE_EXTRQ F=SSE4A ONLYAMD +F2.0f79/r RM Vx Ux - - SSE_INSERTQ F=SSE4A ONLYAMD +66.0f7c RM Vx Wx - - SSE_HADDPD F=SSE3 +F2.0f7c RM Vx Wx - - SSE_HADDPS F=SSE3 +66.0f7d RM Vx Wx - - SSE_HSUBPD F=SSE3 +F2.0f7d RM Vx Wx - - SSE_HSUBPS F=SSE3 +66.W0.0f7e MR Ey Vy - - SSE_MOVD_X2G F=SSE2 ENC_NOSZ +66.W1.0f7e MR Ey Vy - - SSE_MOVQ_X2G F=SSE2 ENC_NOSZ +F3.0f7e RM Vx Wq - - SSE_MOVQ F=SSE2 +66.0f7f MR Wx Vx - - SSE_MOVDQA F=SSE2 +F3.0f7f MR Wx Vx - - SSE_MOVDQU F=SSE2 +NP.0fae/0m M M - - - FXSAVE+w F=FXSR +NP.0fae/1m M M - - - FXRSTOR+w F=FXSR +NP.0fae/2m M Md - - - LDMXCSR F=SSE +NP.0fae/3m M Md - - - STMXCSR F=SSE +NP.0faee8+ NP - - - - LFENCE F=SSE2 +NP.0faef0+ NP - - - - MFENCE F=SSE2 +NP.0faef8+ NP - - - - SFENCE F=SSE +NP.0fc2 RMI Vps Wps Ib - SSE_CMPPS F=SSE +66.0fc2 RMI Vpd Wpd Ib - SSE_CMPPD F=SSE2 +F3.0fc2 RMI Vss Wss Ib - SSE_CMPSS F=SSE +F2.0fc2 RMI Vsd Wsd Ib - SSE_CMPSD F=SSE2 +66.0fc4 RMI Vx Ew Ib - SSE_PINSRW F=SSE2 ENC_NOSZ +66.0fc5/r RMI Gy Udq Ib - SSE_PEXTRW D64 F=SSE2 ENC_NOSZ +NP.0fc6 RMI Vps Wps Ib - SSE_SHUFPS F=SSE +66.0fc6 RMI Vpd Wpd Ib - SSE_SHUFPD F=SSE2 +66.0fd0 RM Vps Wps - - SSE_ADDSUBPD F=SSE3 +F2.0fd0 RM Vpd Wpd - - SSE_ADDSUBPS F=SSE3 +66.0fd1 RM Vx Wx - - SSE_PSRLW F=SSE2 +66.0fd2 RM Vx Wx - - SSE_PSRLD F=SSE2 +66.0fd3 RM Vx Wx - - SSE_PSRLQ F=SSE2 +66.0fd4 RM Vx Wx - - SSE_PADDQ F=SSE2 +66.0fd5 RM Vx Wx - - SSE_PMULLW F=SSE2 +# This is tricky, MOVQ to mem writes 64 bits, MOVQ to reg writes 128 bits +66.0fd6 MR Wq Vq - - SSE_MOVQ F=SSE2 +66.0fd7/r RM Gy Udq - - SSE_PMOVMSKB D64 F=SSE2 +66.0fd8 RM Vx Wx - - SSE_PSUBUSB F=SSE2 +66.0fd9 RM Vx Wx - - SSE_PSUBUSW F=SSE2 +66.0fda RM Vx Wx - - SSE_PMINUB F=SSE2 +66.0fdb RM Vx Wx - - SSE_PAND F=SSE2 +66.0fdc RM Vx Wx - - SSE_PADDUSB F=SSE2 +66.0fdd RM Vx Wx - - SSE_PADDUSW F=SSE2 +66.0fde RM Vx Wx - - SSE_PMAXUB F=SSE2 +66.0fdf RM Vx Wx - - SSE_PANDN F=SSE2 +66.0fe0 RM Vx Wx - - SSE_PAVGB F=SSE2 +66.0fe1 RM Vx Wx - - SSE_PSRAW F=SSE2 +66.0fe2 RM Vx Wx - - SSE_PSRAD F=SSE2 +66.0fe3 RM Vx Wx - - SSE_PAVGW F=SSE2 +66.0fe4 RM Vx Wx - - SSE_PMULHUW F=SSE2 +66.0fe5 RM Vx Wx - - SSE_PMULHW F=SSE2 +66.0fe6 RM Vx Wpd - - SSE_CVTTPD2DQ F=SSE2 +F3.0fe6 RM Vpd Wq - - SSE_CVTDQ2PD F=SSE2 +F2.0fe6 RM Vx Wpd - - SSE_CVTPD2DQ F=SSE2 +66.0fe7/m MR Mx Vx - - SSE_MOVNTDQ F=SSE2 +66.0fe8 RM Vx Wx - - SSE_PSUBSB F=SSE2 +66.0fe9 RM Vx Wx - - SSE_PSUBSW F=SSE2 +66.0feb RM Vx Wx - - SSE_POR F=SSE2 +66.0fec RM Vx Wx - - SSE_PADDSB F=SSE2 +66.0fea RM Vx Wx - - SSE_PMINSW F=SSE2 +66.0fee RM Vx Wx - - SSE_PMAXSW F=SSE2 +66.0fed RM Vx Wx - - SSE_PADDSW F=SSE2 +66.0fef RM Vx Wx - - SSE_PXOR F=SSE2 +F2.0ff0/m RM Vx Mx - - SSE_LDDQU F=SSE3 +66.0ff1 RM Vx Wx - - SSE_PSLLW F=SSE2 +66.0ff2 RM Vx Wx - - SSE_PSLLD F=SSE2 +66.0ff3 RM Vx Wx - - SSE_PSLLQ F=SSE2 +66.0ff4 RM Vx Wx - - SSE_PMULUDQ F=SSE2 +66.0ff5 RM Vx Wx - - SSE_PMADDWD F=SSE2 +66.0ff6 RM Vx Wx - - SSE_PSADBW F=SSE2 +66.0ff7/r RM Vx Ux - - SSE_MASKMOVDQU+as F=SSE2 +66.0ff8 RM Vx Wx - - SSE_PSUBB F=SSE2 +66.0ff9 RM Vx Wx - - SSE_PSUBW F=SSE2 +66.0ffa RM Vx Wx - - SSE_PSUBD F=SSE2 +66.0ffb RM Vx Wx - - SSE_PSUBQ F=SSE2 +66.0ffc RM Vx Wx - - SSE_PADDB F=SSE2 +66.0ffd RM Vx Wx - - SSE_PADDW F=SSE2 +66.0ffe RM Vx Wx - - SSE_PADDD F=SSE2 +# +66.0f3800 RM Vx Wx - - SSE_PSHUFB F=SSSE3 +66.0f3801 RM Vx Wx - - SSE_PHADDW F=SSSE3 +66.0f3802 RM Vx Wx - - SSE_PHADDD F=SSSE3 +66.0f3803 RM Vx Wx - - SSE_PHADDSW F=SSSE3 +66.0f3804 RM Vx Wx - - SSE_PMADDUBSW F=SSSE3 +66.0f3805 RM Vx Wx - - SSE_PHSUBW F=SSSE3 +66.0f3806 RM Vx Wx - - SSE_PHSUBD F=SSSE3 +66.0f3807 RM Vx Wx - - SSE_PHSUBSW F=SSSE3 +66.0f3808 RM Vx Wx - - SSE_PSIGNB F=SSSE3 +66.0f3809 RM Vx Wx - - SSE_PSIGNW F=SSSE3 +66.0f380a RM Vx Wx - - SSE_PSIGND F=SSSE3 +66.0f380b RM Vx Wx - - SSE_PMULHRSW F=SSSE3 +66.0f3810 RM Vdq Wdq - - SSE_PBLENDVB F=SSE41 +66.0f3814 RMA Vdq Wdq Hdq - SSE_BLENDVPS F=SSE41 +66.0f3815 RMA Vdq Wdq Hdq - SSE_BLENDVPD F=SSE41 +66.0f3817 RM Vx Wx - - SSE_PTEST F=SSE41 EFL=0--0m00m +66.0f381c RM Vx Wx - - SSE_PABSB F=SSSE3 +66.0f381d RM Vx Wx - - SSE_PABSW F=SSSE3 +66.0f381e RM Vx Wx - - SSE_PABSD F=SSSE3 +66.0f3820 RM Vx Wh - - SSE_PMOVSXBW F=SSE41 +66.0f3821 RM Vx Wf - - SSE_PMOVSXBD F=SSE41 +66.0f3822 RM Vx We - - SSE_PMOVSXBQ F=SSE41 +66.0f3823 RM Vx Wh - - SSE_PMOVSXWD F=SSE41 +66.0f3824 RM Vx Wf - - SSE_PMOVSXWQ F=SSE41 +66.0f3825 RM Vx Wh - - SSE_PMOVSXDQ F=SSE41 +66.0f3828 RM Vx Wx - - SSE_PMULDQ F=SSE41 +66.0f3829 RM Vx Wx - - SSE_PCMPEQQ F=SSE41 +66.0f382a/m RM Vx Mx - - SSE_MOVNTDQA F=SSE41 +66.0f382b RM Vx Wx - - SSE_PACKUSDW F=SSE41 +66.0f3830 RM Vx Wh - - SSE_PMOVZXBW F=SSE41 +66.0f3831 RM Vx Wf - - SSE_PMOVZXBD F=SSE41 +66.0f3832 RM Vx We - - SSE_PMOVZXBQ F=SSE41 +66.0f3833 RM Vx Wh - - SSE_PMOVZXWD F=SSE41 +66.0f3834 RM Vx Wf - - SSE_PMOVZXWQ F=SSE41 +66.0f3835 RM Vx Wh - - SSE_PMOVZXDQ F=SSE41 +66.0f3837 RM Vx Wx - - SSE_PCMPGTQ F=SSE41 +66.0f3838 RM Vx Wx - - SSE_PMINSB F=SSE41 +66.0f3839 RM Vx Wx - - SSE_PMINSD F=SSE41 +66.0f383a RM Vx Wx - - SSE_PMINUW F=SSE41 +66.0f383b RM Vx Wx - - SSE_PMINUD F=SSE41 +66.0f383c RM Vx Wx - - SSE_PMAXSB F=SSE41 +66.0f383d RM Vx Wx - - SSE_PMAXSD F=SSE41 +66.0f383e RM Vx Wx - - SSE_PMAXUW F=SSE41 +66.0f383f RM Vx Wx - - SSE_PMAXUD F=SSE41 +66.0f3840 RM Vx Wx - - SSE_PMULLD F=SSE41 +66.0f3841 RM Vx Wx - - SSE_PHMINPOSUW F=SSE41 +# TODO: GP operand has address size +66.0f38f8/m RM Gy Moq - - MOVDIR64B D64 F=MOVDIR64B +NP.0f38f9/m MR My Gy - - MOVDIRI F=MOVDIRI +# +66.0f3a08 RMI Vps Wps Ib - SSE_ROUNDPS F=SSE41 +66.0f3a09 RMI Vpd Wpd Ib - SSE_ROUNDPD F=SSE41 +66.0f3a0a RMI Vss Wss Ib - SSE_ROUNDSS F=SSE41 +66.0f3a0b RMI Vsd Wsd Ib - SSE_ROUNDSD F=SSE41 +66.0f3a0c RMI Vps Wps Ib - SSE_BLENDPS F=SSE41 +66.0f3a0d RMI Vpd Wpd Ib - SSE_BLENDPD F=SSE41 +66.0f3a0e RMI Vx Wx Ib - SSE_PBLENDW F=SSE41 +66.0f3a0f RMI Vx Wx Ib - SSE_PALIGNR F=SSSE3 +66.0f3a14/m MRI Mb Vx Ib - SSE_PEXTRB F=SSE41 +66.0f3a14/r MRI Rd Vx Ib - SSE_PEXTRB F=SSE41 ENC_NOSZ +66.0f3a15/m MRI Mw Vx Ib - SSE_PEXTRW F=SSE41 +66.0f3a15/r MRI Rd Vx Ib - SSE_PEXTRW F=SSE41 ENC_NOSZ +66.W0.0f3a16 MRI Ed Vx Ib - SSE_PEXTRD F=SSE41 ENC_NOSZ +66.W1.0f3a16 MRI Eq Vx Ib - SSE_PEXTRQ F=SSE41 ENC_NOSZ +66.0f3a17 MRI Ed Vx Ib - SSE_EXTRACTPS F=SSE41 +66.0f3a20 RMI Vx Eb Ib - SSE_PINSRB F=SSE41 +66.0f3a21 RMI Vps Wss Ib - SSE_INSERTPS F=SSE41 +66.W0.0f3a22 RMI Vx Ed Ib - SSE_PINSRD F=SSE41 ENC_NOSZ +66.W1.0f3a22 RMI Vx Eq Ib - SSE_PINSRQ F=SSE41 ENC_NOSZ +66.0f3a40 RMI Vps Wps Ib - SSE_DPPS F=SSE41 +66.0f3a41 RMI Vpd Wpd Ib - SSE_DPPD F=SSE41 +66.0f3a42 RMI Vx Wx Ib - SSE_MPSADBW F=SSE41 +66.0f3a44 RMI Vdq Wdq Ib - SSE_PCLMULQDQ F=PCLMULQDQ +66.0f3a60 RMI Vdq Wdq Ib - SSE_PCMPESTRM F=SSE42 EFL=m--mm00m +66.0f3a61 RMI Vdq Wdq Ib - SSE_PCMPESTRI F=SSE42 EFL=m--mm00m +66.0f3a62 RMI Vdq Wdq Ib - SSE_PCMPISTRM F=SSE42 EFL=m--mm00m +66.0f3a63 RMI Vdq Wdq Ib - SSE_PCMPISTRI F=SSE42 EFL=m--mm00m +# +66.0f38db RM Vdq Wdq - - AESIMC F=AESNI +66.0f38dc RM Vdq Wdq - - AESENC F=AESNI +66.0f38dd RM Vdq Wdq - - AESENCLAST F=AESNI +66.0f38de RM Vdq Wdq - - AESDEC F=AESNI +66.0f38df RM Vdq Wdq - - AESDECLAST F=AESNI +66.0f3adf RMI Vdq Wdq Ib - AESKEYGENASSIST F=AESNI +VEX.66.L0.0f38db RM Vdq Wdq - - VAESIMC F=AESNI,AVX +# 256-bit encodings require VAES. +VEX.66.0f38dc RVM Vx Hx Wx - VAESENC F=AESNI,AVX +VEX.66.0f38dd RVM Vx Hx Wx - VAESENCLAST F=AESNI,AVX +VEX.66.0f38de RVM Vx Hx Wx - VAESDEC F=AESNI,AVX +VEX.66.0f38df RVM Vx Hx Wx - VAESDECLAST F=AESNI,AVX +VEX.66.L0.0f3adf RMI Vdq Wdq Ib - VAESKEYGENASSIST F=AESNI,AVX +# +# AVX +VEX.NP.0f10 RM Vps Wps - - VMOVUPS F=AVX +VEX.66.0f10 RM Vpd Wpd - - VMOVUPD F=AVX +VEX.F3.LIG.0f10/m RM Vdq Mss - - VMOVSS F=AVX +VEX.F3.LIG.0f10/r RVM Vdq Hdq Uss - VMOVSS F=AVX +VEX.F2.LIG.0f10/m RM Vdq Msd - - VMOVSD F=AVX +VEX.F2.LIG.0f10/r RVM Vdq Hdq Usd - VMOVSD F=AVX +VEX.NP.0f11 MR Wps Vps - - VMOVUPS F=AVX +VEX.66.0f11 MR Wpd Vpd - - VMOVUPD F=AVX +VEX.F3.LIG.0f11/m MR Mss Vss - - VMOVSS F=AVX +VEX.F3.LIG.0f11/r MVR Udq Hdq Vss - VMOVSS F=AVX +VEX.F2.LIG.0f11/m MR Msd Vsd - - VMOVSD F=AVX +VEX.F2.LIG.0f11/r MVR Udq Hdq Vsd - VMOVSD F=AVX +VEX.NP.L0.0f12/m RVM Vdq Hdq Mq - VMOVLPS F=AVX +VEX.NP.L0.0f12/r RVM Vdq Hdq Udq - VMOVHLPS F=AVX +VEX.66.L0.0f12/m RVM Vdq Hdq Mq - VMOVLPD F=AVX +VEX.F2.L0.0f12 RM Vx Wq - - VMOVDDUP F=AVX +VEX.F2.L1.0f12 RM Vx Wx - - VMOVDDUP F=AVX +VEX.F3.0f12 RM Vx Wx - - VMOVSLDUP F=AVX +VEX.NP.L0.0f13/m MR Mq Vq - - VMOVLPS F=AVX +VEX.66.L0.0f13/m MR Mq Vq - - VMOVLPD F=AVX +VEX.NP.0f14 RVM Vx Hx Wx - VUNPCKLPS F=AVX +VEX.66.0f14 RVM Vx Hx Wx - VUNPCKLPD F=AVX +VEX.NP.0f15 RVM Vx Hx Wx - VUNPCKHPS F=AVX +VEX.66.0f15 RVM Vx Hx Wx - VUNPCKHPD F=AVX +VEX.NP.L0.0f16/m RVM Vdq Hq Mq - VMOVHPS F=AVX +VEX.NP.L0.0f16/r RVM Vdq Hq Uq - VMOVLHPS F=AVX +VEX.66.L0.0f16/m RVM Vdq Hq Mq - VMOVHPD F=AVX +VEX.F3.0f16 RM Vx Wx - - VMOVSHDUP F=AVX +VEX.NP.L0.0f17/m MR Mq Vq - - VMOVHPS F=AVX +VEX.66.L0.0f17/m MR Mq Vq - - VMOVHPD F=AVX +VEX.NP.0f28 RM Vps Wps - - VMOVAPS F=AVX +VEX.66.0f28 RM Vpd Wpd - - VMOVAPD F=AVX +VEX.NP.0f29 MR Wps Vps - - VMOVAPS F=AVX +VEX.66.0f29 MR Wpd Vpd - - VMOVAPD F=AVX +VEX.F3.LIG.0f2a RVM Vdq Hdq Ey - VCVTSI2SS F=AVX +VEX.F2.LIG.0f2a RVM Vdq Hdq Ey - VCVTSI2SD F=AVX +VEX.NP.0f2b/m MR Mps Vps - - VMOVNTPS F=AVX +VEX.66.0f2b/m MR Mpd Vpd - - VMOVNTPD F=AVX +VEX.F3.LIG.0f2c RM Gy Wss - - VCVTTSS2SI F=AVX +VEX.F2.LIG.0f2c RM Gy Wsd - - VCVTTSD2SI F=AVX +VEX.F3.LIG.0f2d RM Gy Wss - - VCVTSS2SI F=AVX +VEX.F2.LIG.0f2d RM Gy Wsd - - VCVTSD2SI F=AVX +VEX.NP.LIG.0f2e RM Vss Wss - - VUCOMISS F=AVX EFL=0--0m0mm +VEX.66.LIG.0f2e RM Vsd Wsd - - VUCOMISD F=AVX EFL=0--0m0mm +VEX.NP.LIG.0f2f RM Vss Wss - - VCOMISS F=AVX EFL=0--0m0mm +VEX.66.LIG.0f2f RM Vsd Wsd - - VCOMISD F=AVX EFL=0--0m0mm +VEX.NP.0f50/r RM Gd Ups - - VMOVMSKPS F=AVX +VEX.66.0f50/r RM Gd Upd - - VMOVMSKPD F=AVX +VEX.NP.0f51 RM Vps Wps - - VSQRTPS F=AVX +VEX.66.0f51 RM Vpd Wpd - - VSQRTPD F=AVX +VEX.F3.LIG.0f51 RVM Vdq Hdq Wss - VSQRTSS F=AVX +VEX.F2.LIG.0f51 RVM Vdq Hdq Wsd - VSQRTSD F=AVX +VEX.NP.0f52 RM Vps Wps - - VRSQRTPS F=AVX +VEX.F3.LIG.0f52 RVM Vdq Hdq Wss - VRSQRTSS F=AVX +VEX.NP.0f53 RM Vps Wps - - VRCPPS F=AVX +VEX.F3.LIG.0f53 RVM Vdq Hdq Wss - VRCPSS F=AVX +VEX.NP.0f54 RVM Vps Hps Wps - VANDPS F=AVX +VEX.66.0f54 RVM Vpd Hpd Wpd - VANDPD F=AVX +VEX.NP.0f55 RVM Vps Hps Wps - VANDNPS F=AVX +VEX.66.0f55 RVM Vpd Hpd Wpd - VANDNPD F=AVX +VEX.NP.0f56 RVM Vps Hps Wps - VORPS F=AVX +VEX.66.0f56 RVM Vpd Hpd Wpd - VORPD F=AVX +VEX.NP.0f57 RVM Vps Hps Wps - VXORPS F=AVX +VEX.66.0f57 RVM Vpd Hpd Wpd - VXORPD F=AVX +VEX.NP.0f58 RVM Vps Hps Wps - VADDPS F=AVX +VEX.66.0f58 RVM Vpd Hpd Wpd - VADDPD F=AVX +VEX.F3.LIG.0f58 RVM Vdq Hdq Wss - VADDSS F=AVX +VEX.F2.LIG.0f58 RVM Vdq Hdq Wsd - VADDSD F=AVX +VEX.NP.0f59 RVM Vps Hps Wps - VMULPS F=AVX +VEX.66.0f59 RVM Vpd Hpd Wpd - VMULPD F=AVX +VEX.F3.LIG.0f59 RVM Vdq Hdq Wss - VMULSS F=AVX +VEX.F2.LIG.0f59 RVM Vdq Hdq Wsd - VMULSD F=AVX +VEX.NP.0f5a RM Vpd Wh - - VCVTPS2PD F=AVX +VEX.66.0f5a RM Vh Wpd - - VCVTPD2PS F=AVX +VEX.F3.LIG.0f5a RVM Vdq Hdq Wss - VCVTSS2SD F=AVX +VEX.F2.LIG.0f5a RVM Vdq Hdq Wsd - VCVTSD2SS F=AVX +VEX.NP.0f5b RM Vps Wx - - VCVTDQ2PS F=AVX +VEX.66.0f5b RM Vx Wps - - VCVTPS2DQ F=AVX +VEX.F3.0f5b RM Vx Wps - - VCVTTPS2DQ F=AVX +VEX.NP.0f5c RVM Vps Hps Wps - VSUBPS F=AVX +VEX.66.0f5c RVM Vpd Hpd Wpd - VSUBPD F=AVX +VEX.F3.LIG.0f5c RVM Vdq Hdq Wss - VSUBSS F=AVX +VEX.F2.LIG.0f5c RVM Vdq Hdq Wsd - VSUBSD F=AVX +VEX.NP.0f5d RVM Vps Hps Wps - VMINPS F=AVX +VEX.66.0f5d RVM Vpd Hpd Wpd - VMINPD F=AVX +VEX.F3.LIG.0f5d RVM Vdq Hdq Wss - VMINSS F=AVX +VEX.F2.LIG.0f5d RVM Vdq Hdq Wsd - VMINSD F=AVX +VEX.NP.0f5e RVM Vps Hps Wps - VDIVPS F=AVX +VEX.66.0f5e RVM Vpd Hpd Wpd - VDIVPD F=AVX +VEX.F3.LIG.0f5e RVM Vdq Hdq Wss - VDIVSS F=AVX +VEX.F2.LIG.0f5e RVM Vdq Hdq Wsd - VDIVSD F=AVX +VEX.NP.0f5f RVM Vps Hps Wps - VMAXPS F=AVX +VEX.66.0f5f RVM Vpd Hpd Wpd - VMAXPD F=AVX +VEX.F3.LIG.0f5f RVM Vdq Hdq Wss - VMAXSS F=AVX +VEX.F2.LIG.0f5f RVM Vdq Hdq Wsd - VMAXSD F=AVX +VEX.66.0f60 RVM Vx Hx Wx - VPUNPCKLBW F=AVX +VEX.66.0f61 RVM Vx Hx Wx - VPUNPCKLWD F=AVX +VEX.66.0f62 RVM Vx Hx Wx - VPUNPCKLDQ F=AVX +VEX.66.0f63 RVM Vx Hx Wx - VPACKSSWB F=AVX +VEX.66.0f64 RVM Vx Hx Wx - VPCMPGTB F=AVX +VEX.66.0f65 RVM Vx Hx Wx - VPCMPGTW F=AVX +VEX.66.0f66 RVM Vx Hx Wx - VPCMPGTD F=AVX +VEX.66.0f67 RVM Vx Hx Wx - VPACKUSWB F=AVX +VEX.66.0f68 RVM Vx Hx Wx - VPUNPCKHBW F=AVX +VEX.66.0f69 RVM Vx Hx Wx - VPUNPCKHWD F=AVX +VEX.66.0f6a RVM Vx Hx Wx - VPUNPCKHDQ F=AVX +VEX.66.0f6b RVM Vx Hx Wx - VPACKSSDW F=AVX +VEX.66.0f6c RVM Vx Hx Wx - VPUNPCKLQDQ F=AVX +VEX.66.0f6d RVM Vx Hx Wx - VPUNPCKHQDQ F=AVX +VEX.66.W0.L0.0f6e RM Vy Ey - - VMOVD_G2X F=AVX ENC_NOSZ +VEX.66.W1.L0.0f6e RM Vy Ey - - VMOVD_G2X I64 F=AVX ENC_NOSZ +VEX.66.W1.L0.0f6e RM Vy Ey - - VMOVQ_G2X O64 F=AVX ENC_NOSZ +VEX.66.0f6f RM Vx Wx - - VMOVDQA F=AVX +VEX.F3.0f6f RM Vx Wx - - VMOVDQU F=AVX +VEX.66.0f70 RMI Vx Wx Ib - VPSHUFD F=AVX +VEX.F3.0f70 RMI Vx Wx Ib - VPSHUFHW F=AVX +VEX.F2.0f70 RMI Vx Wx Ib - VPSHUFLW F=AVX +VEX.66.0f71/2r VMI Hx Ux Ib - VPSRLW F=AVX +VEX.66.0f71/4r VMI Hx Ux Ib - VPSRAW F=AVX +VEX.66.0f71/6r VMI Hx Ux Ib - VPSLLW F=AVX +VEX.66.0f72/2r VMI Hx Ux Ib - VPSRLD F=AVX +VEX.66.0f72/4r VMI Hx Ux Ib - VPSRAD F=AVX +VEX.66.0f72/6r VMI Hx Ux Ib - VPSLLD F=AVX +VEX.66.0f73/2r VMI Hx Ux Ib - VPSRLQ F=AVX +VEX.66.0f73/3r VMI Hx Ux Ib - VPSRLDQ F=AVX +VEX.66.0f73/6r VMI Hx Ux Ib - VPSLLQ F=AVX +VEX.66.0f73/7r VMI Hx Ux Ib - VPSLLDQ F=AVX +VEX.66.0f74 RVM Vx Hx Wx - VPCMPEQB F=AVX +VEX.66.0f75 RVM Vx Hx Wx - VPCMPEQW F=AVX +VEX.66.0f76 RVM Vx Hx Wx - VPCMPEQD F=AVX +VEX.NP.L0.0f77 NP - - - - VZEROUPPER F=AVX +VEX.NP.L1.0f77 NP - - - - VZEROALL F=AVX +VEX.66.0f7c RVM Vx Hx Wx - VHADDPD F=AVX +VEX.F2.0f7c RVM Vx Hx Wx - VHADDPS F=AVX +VEX.66.0f7d RVM Vx Hx Wx - VHSUBPD F=AVX +VEX.F2.0f7d RVM Vx Hx Wx - VHSUBPS F=AVX +VEX.66.W0.L0.0f7e MR Ey Vy - - VMOVD_X2G F=AVX ENC_NOSZ +VEX.66.W1.L0.0f7e MR Ey Vy - - VMOVD_X2G I64 F=AVX ENC_NOSZ +VEX.66.W1.L0.0f7e MR Ey Vy - - VMOVQ_X2G O64 F=AVX ENC_NOSZ +VEX.F3.L0.0f7e RM Vq Wq - - VMOVQ F=AVX +VEX.66.0f7f MR Wx Vx - - VMOVDQA F=AVX +VEX.F3.0f7f MR Wx Vx - - VMOVDQU F=AVX +VEX.NP.L0.0fae/2m M Md - - - VLDMXCSR F=AVX +VEX.NP.L0.0fae/3m M Md - - - VSTMXCSR F=AVX +VEX.NP.0fc2 RVMI Vx Hx Wx Ib VCMPPS F=AVX +VEX.66.0fc2 RVMI Vx Hx Wx Ib VCMPPD F=AVX +VEX.F3.LIG.0fc2 RVMI Vdq Hdq Wss Ib VCMPSS F=AVX +VEX.F2.LIG.0fc2 RVMI Vdq Hdq Wsd Ib VCMPSD F=AVX +VEX.66.L0.0fc4 RVMI Vdq Hdq Ew Ib VPINSRW F=AVX +VEX.66.L0.0fc5/r RMI Gd Udq Ib - VPEXTRW F=AVX +VEX.NP.0fc6 RVMI Vx Hx Wx Ib VSHUFPS F=AVX +VEX.66.0fc6 RVMI Vx Hx Wx Ib VSHUFPD F=AVX +VEX.66.0fd0 RVM Vx Hx Wx - VADDSUBPD F=AVX +VEX.F2.0fd0 RVM Vx Hx Wx - VADDSUBPS F=AVX +VEX.66.0fd1 RVM Vx Hx Wdq - VPSRLW F=AVX +VEX.66.0fd2 RVM Vx Hx Wdq - VPSRLD F=AVX +VEX.66.0fd3 RVM Vx Hx Wdq - VPSRLQ F=AVX +VEX.66.0fd4 RVM Vx Hx Wx - VPADDQ F=AVX +VEX.66.0fd5 RVM Vx Hx Wx - VPMULLW F=AVX +VEX.66.L0.0fd6 MR Wq Vq - - VMOVQ F=AVX +VEX.66.0fd7/r RM Gd Ux - - VPMOVMSKB F=AVX +VEX.66.0fd8 RVM Vx Hx Wx - VPSUBUSB F=AVX +VEX.66.0fd9 RVM Vx Hx Wx - VPSUBUSW F=AVX +VEX.66.0fda RVM Vx Hx Wx - VPMINUB F=AVX +VEX.66.0fdb RVM Vx Hx Wx - VPAND F=AVX +VEX.66.0fdc RVM Vx Hx Wx - VPADDUSB F=AVX +VEX.66.0fdd RVM Vx Hx Wx - VPADDUSW F=AVX +VEX.66.0fde RVM Vx Hx Wx - VPMAXUB F=AVX +VEX.66.0fdf RVM Vx Hx Wx - VPANDN F=AVX +VEX.66.0fe0 RVM Vx Hx Wx - VPAVGB F=AVX +VEX.66.0fe1 RVM Vx Hx Wdq - VPSRAW F=AVX +VEX.66.0fe2 RVM Vx Hx Wdq - VPSRAD F=AVX +VEX.66.0fe3 RVM Vx Hx Wx - VPAVGW F=AVX +VEX.66.0fe4 RVM Vx Hx Wx - VPMULHUW F=AVX +VEX.66.0fe5 RVM Vx Hx Wx - VPMULHW F=AVX +VEX.66.0fe6 RM Vh Wx - - VCVTTPD2DQ F=AVX +VEX.F3.0fe6 RM Vx Wh - - VCVTDQ2PD F=AVX +VEX.F2.0fe6 RM Vh Wx - - VCVTPD2DQ F=AVX +VEX.66.0fe7/m MR Mx Vx - - VMOVNTDQ F=AVX +VEX.66.0fe8 RVM Vx Hx Wx - VPSUBSB F=AVX +VEX.66.0fe9 RVM Vx Hx Wx - VPSUBSW F=AVX +VEX.66.0feb RVM Vx Hx Wx - VPOR F=AVX +VEX.66.0fec RVM Vx Hx Wx - VPADDSB F=AVX +VEX.66.0fea RVM Vx Hx Wx - VPMINSW F=AVX +VEX.66.0fed RVM Vx Hx Wx - VPADDSW F=AVX +VEX.66.0fee RVM Vx Hx Wx - VPMAXSW F=AVX +VEX.66.0fef RVM Vx Hx Wx - VPXOR F=AVX +VEX.F2.0ff0/m RM Vx Mx - - VLDDQU F=AVX +VEX.66.0ff1 RVM Vx Hx Wdq - VPSLLW F=AVX +VEX.66.0ff2 RVM Vx Hx Wdq - VPSLLD F=AVX +VEX.66.0ff3 RVM Vx Hx Wdq - VPSLLQ F=AVX +VEX.66.0ff4 RVM Vx Hx Wx - VPMULUDQ F=AVX +VEX.66.0ff5 RVM Vx Hx Wx - VPMADDWD F=AVX +VEX.66.0ff6 RVM Vx Hx Wx - VPSADBW F=AVX +VEX.66.L0.0ff7/r RM Vx Ux - - VMASKMOVDQU+as F=AVX +VEX.66.0ff8 RVM Vx Hx Wx - VPSUBB F=AVX +VEX.66.0ff9 RVM Vx Hx Wx - VPSUBW F=AVX +VEX.66.0ffa RVM Vx Hx Wx - VPSUBD F=AVX +VEX.66.0ffb RVM Vx Hx Wx - VPSUBQ F=AVX +VEX.66.0ffc RVM Vx Hx Wx - VPADDB F=AVX +VEX.66.0ffd RVM Vx Hx Wx - VPADDW F=AVX +VEX.66.0ffe RVM Vx Hx Wx - VPADDD F=AVX +VEX.66.0f3800 RVM Vx Hx Wx - VPSHUFB F=AVX +VEX.66.0f3801 RVM Vx Hx Wx - VPHADDW F=AVX +VEX.66.0f3802 RVM Vx Hx Wx - VPHADDD F=AVX +VEX.66.0f3803 RVM Vx Hx Wx - VPHADDSW F=AVX +VEX.66.0f3804 RVM Vx Hx Wx - VPMADDUBSW F=AVX +VEX.66.0f3805 RVM Vx Hx Wx - VPHSUBW F=AVX +VEX.66.0f3806 RVM Vx Hx Wx - VPHSUBD F=AVX +VEX.66.0f3807 RVM Vx Hx Wx - VPHSUBSW F=AVX +VEX.66.0f3808 RVM Vx Hx Wx - VPSIGNB F=AVX +VEX.66.0f3809 RVM Vx Hx Wx - VPSIGNW F=AVX +VEX.66.0f380a RVM Vx Hx Wx - VPSIGND F=AVX +VEX.66.0f380b RVM Vx Hx Wx - VPMULHRSW F=AVX +VEX.66.W0.0f380c RVM Vx Hx Wx - VPERMILPS F=AVX +VEX.66.W0.0f380d RVM Vx Hx Wx - VPERMILPD F=AVX +VEX.66.W0.0f380e RM Vx Wx - - VTESTPS F=AVX +VEX.66.W0.0f380f RM Vx Wx - - VTESTPD F=AVX +VEX.66.W0.0f3813 RM Vx Wh - - VCVTPH2PS F=F16C +VEX.66.W0.L1.0f3816 RVM Vx Hx Wx - VPERMPS F=AVX2 +VEX.66.0f3817 RM Vx Wx - - VPTEST F=AVX EFL=0--0m00m +VEX.66.W0.0f3818 RM Vx Wd - - VBROADCASTSS F=AVX +VEX.66.W0.L1.0f3819 RM Vx Wq - - VBROADCASTSD F=AVX +VEX.66.W0.L1.0f381a RM Vx Wdq - - VBROADCASTF128 F=AVX +VEX.66.0f381c RM Vx Wx - - VPABSB F=AVX +VEX.66.0f381d RM Vx Wx - - VPABSW F=AVX +VEX.66.0f381e RM Vx Wx - - VPABSD F=AVX +VEX.66.0f3820 RM Vx Wh - - VPMOVSXBW F=AVX +VEX.66.0f3821 RM Vx Wf - - VPMOVSXBD F=AVX +VEX.66.0f3822 RM Vx We - - VPMOVSXBQ F=AVX +VEX.66.0f3823 RM Vx Wh - - VPMOVSXWD F=AVX +VEX.66.0f3824 RM Vx Wf - - VPMOVSXWQ F=AVX +VEX.66.0f3825 RM Vx Wh - - VPMOVSXDQ F=AVX +VEX.66.0f3828 RVM Vx Hx Wx - VPMULDQ F=AVX +VEX.66.0f3829 RVM Vx Hx Wx - VPCMPEQQ F=AVX +VEX.66.0f382a/m RM Vx Mx - - VMOVNTDQA F=AVX +VEX.66.0f382b RVM Vx Hx Wx - VPACKUSDW F=AVX +VEX.66.W0.0f382c/m RVM Vx Hx Mx - VMASKMOVPS F=AVX +VEX.66.W0.0f382d/m RVM Vx Hx Mx - VMASKMOVPD F=AVX +VEX.66.W0.0f382e/m MVR Mx Hx Vx - VMASKMOVPS F=AVX +VEX.66.W0.0f382f/m MVR Mx Hx Vx - VMASKMOVPD F=AVX +VEX.66.0f3830 RM Vx Wh - - VPMOVZXBW F=AVX +VEX.66.0f3831 RM Vx Wf - - VPMOVZXBD F=AVX +VEX.66.0f3832 RM Vx We - - VPMOVZXBQ F=AVX +VEX.66.0f3833 RM Vx Wh - - VPMOVZXWD F=AVX +VEX.66.0f3834 RM Vx Wf - - VPMOVZXWQ F=AVX +VEX.66.0f3835 RM Vx Wh - - VPMOVZXDQ F=AVX +VEX.66.W0.L1.0f3836 RVM Vx Hx Wx - VPERMD F=AVX2 +VEX.66.0f3837 RVM Vx Hx Wx - VPCMPGTQ F=AVX +VEX.66.0f3838 RVM Vx Hx Wx - VPMINSB F=AVX +VEX.66.0f3839 RVM Vx Hx Wx - VPMINSD F=AVX +VEX.66.0f383a RVM Vx Hx Wx - VPMINUW F=AVX +VEX.66.0f383b RVM Vx Hx Wx - VPMINUD F=AVX +VEX.66.0f383c RVM Vx Hx Wx - VPMAXSB F=AVX +VEX.66.0f383d RVM Vx Hx Wx - VPMAXSD F=AVX +VEX.66.0f383e RVM Vx Hx Wx - VPMAXUW F=AVX +VEX.66.0f383f RVM Vx Hx Wx - VPMAXUD F=AVX +VEX.66.0f3840 RVM Vx Hx Wx - VPMULLD F=AVX +VEX.66.L0.0f3841 RM Vx Wx - - VPHMINPOSUW F=AVX +VEX.66.W0.0f3845 RVM Vx Hx Wx - VPSRLVD F=AVX2 +VEX.66.W1.0f3845 RVM Vx Hx Wx - VPSRLVQ F=AVX2 +VEX.66.W0.0f3846 RVM Vx Hx Wx - VPSRAVD F=AVX2 +VEX.66.W0.0f3847 RVM Vx Hx Wx - VPSLLVD F=AVX2 +VEX.66.W1.0f3847 RVM Vx Hx Wx - VPSLLVQ F=AVX2 +VEX.66.W0.0f3858 RM Vx Wd - - VPBROADCASTD F=AVX2 +VEX.66.W0.0f3859 RM Vx Wq - - VPBROADCASTQ F=AVX2 +VEX.66.W0.L1.0f385a/m RM Vx Mdq - - VBROADCASTI128 F=AVX2 ENC_NOSZ +VEX.66.W0.0f3878 RM Vx Wb - - VPBROADCASTB F=AVX2 +VEX.66.W0.0f3879 RM Vx Ww - - VPBROADCASTW F=AVX2 +VEX.66.W0.0f388c/m RVM Vx Hx Mx - VPMASKMOVD F=AVX2 +VEX.66.W1.0f388c/m RVM Vx Hx Mx - VPMASKMOVQ F=AVX2 +VEX.66.W0.0f388e/m MVR Mx Hx Vx - VPMASKMOVD F=AVX2 +VEX.66.W1.0f388e/m MVR Mx Hx Vx - VPMASKMOVQ F=AVX2 +VEX.66.W0.0f3890/m RMV Vx Md Hx - VPGATHERDD VSIB F=AVX2 +VEX.66.W1.0f3890/m RMV Vx Mq Hx - VPGATHERDQ VSIB F=AVX2 +VEX.66.W0.0f3891/m RMV Vh Md Hh - VPGATHERQD VSIB F=AVX2 +VEX.66.W1.0f3891/m RMV Vx Mq Hx - VPGATHERQQ VSIB F=AVX2 +VEX.66.W0.0f3892/m RMV Vx Md Hx - VGATHERDPS VSIB F=AVX2 +VEX.66.W1.0f3892/m RMV Vx Mq Hx - VGATHERDPD VSIB F=AVX2 +VEX.66.W0.0f3893/m RMV Vh Md Hh - VGATHERQPS VSIB F=AVX2 +VEX.66.W1.0f3893/m RMV Vx Mq Hx - VGATHERQPD VSIB F=AVX2 +VEX.66.W0.0f3896 RVM Vx Hx Wx - VFMADDSUB132PS F=FMA +VEX.66.W1.0f3896 RVM Vx Hx Wx - VFMADDSUB132PD F=FMA +VEX.66.W0.0f3897 RVM Vx Hx Wx - VFMSUBADD132PS F=FMA +VEX.66.W1.0f3897 RVM Vx Hx Wx - VFMSUBADD132PD F=FMA +VEX.66.W0.0f3898 RVM Vx Hx Wx - VFMADD132PS F=FMA +VEX.66.W1.0f3898 RVM Vx Hx Wx - VFMADD132PD F=FMA +VEX.66.W0.LIG.0f3899 RVM Vdq Hdq Wss - VFMADD132SS F=FMA +VEX.66.W1.LIG.0f3899 RVM Vdq Hdq Wsd - VFMADD132SD F=FMA +VEX.66.W0.0f389a RVM Vx Hx Wx - VFMSUB132PS F=FMA +VEX.66.W1.0f389a RVM Vx Hx Wx - VFMSUB132PD F=FMA +VEX.66.W0.LIG.0f389b RVM Vdq Hdq Wss - VFMSUB132SS F=FMA +VEX.66.W1.LIG.0f389b RVM Vdq Hdq Wsd - VFMSUB132SD F=FMA +VEX.66.W0.0f389c RVM Vx Hx Wx - VFNMADD132PS F=FMA +VEX.66.W1.0f389c RVM Vx Hx Wx - VFNMADD132PD F=FMA +VEX.66.W0.LIG.0f389d RVM Vdq Hdq Wss - VFNMADD132SS F=FMA +VEX.66.W1.LIG.0f389d RVM Vdq Hdq Wsd - VFNMADD132SD F=FMA +VEX.66.W0.0f389e RVM Vx Hx Wx - VFNMSUB132PS F=FMA +VEX.66.W1.0f389e RVM Vx Hx Wx - VFNMSUB132PD F=FMA +VEX.66.W0.LIG.0f389f RVM Vdq Hdq Wss - VFNMSUB132SS F=FMA +VEX.66.W1.LIG.0f389f RVM Vdq Hdq Wsd - VFNMSUB132SD F=FMA +VEX.66.W0.0f38a6 RVM Vx Hx Wx - VFMADDSUB213PS F=FMA +VEX.66.W1.0f38a6 RVM Vx Hx Wx - VFMADDSUB213PD F=FMA +VEX.66.W0.0f38a7 RVM Vx Hx Wx - VFMSUBADD213PS F=FMA +VEX.66.W1.0f38a7 RVM Vx Hx Wx - VFMSUBADD213PD F=FMA +VEX.66.W0.0f38a8 RVM Vx Hx Wx - VFMADD213PS F=FMA +VEX.66.W1.0f38a8 RVM Vx Hx Wx - VFMADD213PD F=FMA +VEX.66.W0.LIG.0f38a9 RVM Vdq Hdq Wss - VFMADD213SS F=FMA +VEX.66.W1.LIG.0f38a9 RVM Vdq Hdq Wsd - VFMADD213SD F=FMA +VEX.66.W0.0f38aa RVM Vx Hx Wx - VFMSUB213PS F=FMA +VEX.66.W1.0f38aa RVM Vx Hx Wx - VFMSUB213PD F=FMA +VEX.66.W0.LIG.0f38ab RVM Vdq Hdq Wss - VFMSUB213SS F=FMA +VEX.66.W1.LIG.0f38ab RVM Vdq Hdq Wsd - VFMSUB213SD F=FMA +VEX.66.W0.0f38ac RVM Vx Hx Wx - VFNMADD213PS F=FMA +VEX.66.W1.0f38ac RVM Vx Hx Wx - VFNMADD213PD F=FMA +VEX.66.W0.LIG.0f38ad RVM Vdq Hdq Wss - VFNMADD213SS F=FMA +VEX.66.W1.LIG.0f38ad RVM Vdq Hdq Wsd - VFNMADD213SD F=FMA +VEX.66.W0.0f38ae RVM Vx Hx Wx - VFNMSUB213PS F=FMA +VEX.66.W1.0f38ae RVM Vx Hx Wx - VFNMSUB213PD F=FMA +VEX.66.W0.LIG.0f38af RVM Vdq Hdq Wss - VFNMSUB213SS F=FMA +VEX.66.W1.LIG.0f38af RVM Vdq Hdq Wsd - VFNMSUB213SD F=FMA +VEX.66.W0.0f38b6 RVM Vx Hx Wx - VFMADDSUB231PS F=FMA +VEX.66.W1.0f38b6 RVM Vx Hx Wx - VFMADDSUB231PD F=FMA +VEX.66.W0.0f38b7 RVM Vx Hx Wx - VFMSUBADD231PS F=FMA +VEX.66.W1.0f38b7 RVM Vx Hx Wx - VFMSUBADD231PD F=FMA +VEX.66.W0.0f38b8 RVM Vx Hx Wx - VFMADD231PS F=FMA +VEX.66.W1.0f38b8 RVM Vx Hx Wx - VFMADD231PD F=FMA +VEX.66.W0.LIG.0f38b9 RVM Vdq Hdq Wss - VFMADD231SS F=FMA +VEX.66.W1.LIG.0f38b9 RVM Vdq Hdq Wsd - VFMADD231SD F=FMA +VEX.66.W0.0f38ba RVM Vx Hx Wx - VFMSUB231PS F=FMA +VEX.66.W1.0f38ba RVM Vx Hx Wx - VFMSUB231PD F=FMA +VEX.66.W0.LIG.0f38bb RVM Vdq Hdq Wss - VFMSUB231SS F=FMA +VEX.66.W1.LIG.0f38bb RVM Vdq Hdq Wsd - VFMSUB231SD F=FMA +VEX.66.W0.0f38bc RVM Vx Hx Wx - VFNMADD231PS F=FMA +VEX.66.W1.0f38bc RVM Vx Hx Wx - VFNMADD231PD F=FMA +VEX.66.W0.LIG.0f38bd RVM Vdq Hdq Wss - VFNMADD231SS F=FMA +VEX.66.W1.LIG.0f38bd RVM Vdq Hdq Wsd - VFNMADD231SD F=FMA +VEX.66.W0.0f38be RVM Vx Hx Wx - VFNMSUB231PS F=FMA +VEX.66.W1.0f38be RVM Vx Hx Wx - VFNMSUB231PD F=FMA +VEX.66.W0.LIG.0f38bf RVM Vdq Hdq Wss - VFNMSUB231SS F=FMA +VEX.66.W1.LIG.0f38bf RVM Vdq Hdq Wsd - VFNMSUB231SD F=FMA +VEX.66.W1.L1.0f3a00 RMI Vx Wx Ib - VPERMQ F=AVX2 +VEX.66.W1.L1.0f3a01 RMI Vx Wx Ib - VPERMPD F=AVX2 +VEX.66.W0.0f3a02 RVMI Vx Hx Wx Ib VPBLENDD F=AVX2 +VEX.66.W0.0f3a04 RMI Vx Wx Ib - VPERMILPS F=AVX +VEX.66.W0.0f3a05 RMI Vx Wx Ib - VPERMILPD F=AVX +VEX.66.W0.L1.0f3a06 RVMI Vx Hx Wx Ib VPERM2F128 F=AVX +VEX.66.0f3a08 RMI Vps Wps Ib - VROUNDPS F=AVX +VEX.66.0f3a09 RMI Vpd Wpd Ib - VROUNDPD F=AVX +VEX.66.LIG.0f3a0a RVMI Vdq Hdq Wss Ib VROUNDSS F=AVX +VEX.66.LIG.0f3a0b RVMI Vdq Hdq Wsd Ib VROUNDSD F=AVX +VEX.66.0f3a0c RVMI Vx Hx Wx Ib VBLENDPS F=AVX +VEX.66.0f3a0d RVMI Vx Hx Wx Ib VBLENDPD F=AVX +VEX.66.0f3a0e RVMI Vx Hx Wx Ib VPBLENDW F=AVX +VEX.66.0f3a0f RVMI Vx Hx Wx Ib VPALIGNR F=AVX +VEX.66.L0.0f3a14/m MRI Mb Vdq Ib - VPEXTRB F=AVX +VEX.66.L0.0f3a14/r MRI Rd Vdq Ib - VPEXTRB F=AVX +VEX.66.L0.0f3a15/m MRI Mw Vdq Ib - VPEXTRW F=AVX +VEX.66.L0.0f3a15/r MRI Rd Vdq Ib - VPEXTRW F=AVX +VEX.66.W0.L0.0f3a16 MRI Ey Vdq Ib - VPEXTRD F=AVX ENC_NOSZ +VEX.66.W1.L0.0f3a16 MRI Ey Vdq Ib - VPEXTRD I64 F=AVX ENC_NOSZ +VEX.66.W1.L0.0f3a16 MRI Ey Vdq Ib - VPEXTRQ O64 F=AVX ENC_NOSZ +VEX.66.L0.0f3a17 MRI Ed Vdq Ib - VEXTRACTPS F=AVX +VEX.66.W0.L1.0f3a18 RVMI Vx Hx Wdq Ib VINSERTF128 F=AVX ENC_NOSZ +VEX.66.W0.L1.0f3a19 MRI Wdq Vx Ib - VEXTRACTF128 F=AVX ENC_NOSZ +VEX.66.W0.0f3a1d MRI Wh Vx Ib - VCVTPS2PH F=F16C +VEX.66.L0.0f3a20 RVMI Vdq Hdq Eb Ib VPINSRB F=AVX +VEX.66.L0.0f3a21 RVMI Vdq Hdq Wd Ib VINSERTPS F=AVX +VEX.66.W0.L0.0f3a22 RVMI Vdq Hdq Ey Ib VPINSRD F=AVX ENC_NOSZ +VEX.66.W1.L0.0f3a22 RVMI Vdq Hdq Ey Ib VPINSRD I64 F=AVX ENC_NOSZ +VEX.66.W1.L0.0f3a22 RVMI Vdq Hdq Ey Ib VPINSRQ O64 F=AVX ENC_NOSZ +VEX.66.W0.L1.0f3a38 RVMI Vx Hx Wdq Ib VINSERTI128 F=AVX2 ENC_NOSZ +VEX.66.W0.L1.0f3a39 MRI Wdq Vx Ib - VEXTRACTI128 F=AVX2 ENC_NOSZ +VEX.66.0f3a40 RVMI Vx Hx Wx Ib VDPPS F=AVX +VEX.66.L0.0f3a41 RVMI Vx Hx Wx Ib VDPPD F=AVX +VEX.66.0f3a42 RVMI Vx Hx Wx Ib VMPSADBW F=AVX +VEX.66.0f3a44 RVMI Vx Hx Wx Ib VPCLMULQDQ F=PCLMULQDQ,AVX +VEX.66.W0.L1.0f3a46 RVMI Vx Hx Wx Ib VPERM2I128 F=AVX2 +VEX.66.W0.0f3a4a RVMR Vx Hx Wx Lx VBLENDVPS F=AVX +VEX.66.W0.0f3a4b RVMR Vx Hx Wx Lx VBLENDVPD F=AVX +VEX.66.W0.0f3a4c RVMR Vx Hx Wx Lx VPBLENDVB F=AVX +VEX.66.L0.0f3a60 RMI Vx Wx Ib - VPCMPESTRM F=AVX ENC_NOSZ +VEX.66.L0.0f3a61 RMI Vx Wx Ib - VPCMPESTRI F=AVX ENC_NOSZ +VEX.66.L0.0f3a62 RMI Vx Wx Ib - VPCMPISTRM F=AVX ENC_NOSZ +VEX.66.L0.0f3a63 RMI Vx Wx Ib - VPCMPISTRI F=AVX ENC_NOSZ +# +# BMI1 +VEX.NP.L0.0f38f2 RVM Gy By Ey - ANDN F=BMI1 EFL=0--mmuu0 +VEX.NP.L0.0f38f3/1 VM By Ey - - BLSR F=BMI1 EFL=0--mmuum +VEX.NP.L0.0f38f3/2 VM By Ey - - BLSMSK F=BMI1 EFL=0--m0uum +VEX.NP.L0.0f38f3/3 VM By Ey - - BLSI F=BMI1 EFL=0--mmuum +VEX.NP.L0.0f38f7 RMV Gy Ey By - BEXTR F=BMI1 EFL=0--umuu0 +# BMI2 +VEX.F2.L0.0f3af0 RMI Gy Ey Ib - RORX F=BMI2 +VEX.NP.L0.0f38f5 RMV Gy Ey By - BZHI F=BMI2 EFL=0--mmuum +VEX.F2.L0.0f38f5 RVM Gy By Ey - PDEP F=BMI2 +VEX.F3.L0.0f38f5 RVM Gy By Ey - PEXT F=BMI2 +VEX.F2.L0.0f38f6 RVM Gy By Ey - MULX F=BMI2 +VEX.66.L0.0f38f7 RMV Gy Ey By - SHLX F=BMI2 +VEX.F2.L0.0f38f7 RMV Gy Ey By - SHRX F=BMI2 +VEX.F3.L0.0f38f7 RMV Gy Ey By - SARX F=BMI2 +# ADX +66.0f38f6 RM Gy Ey - - ADCX F=ADX EFL=-------M +F3.0f38f6 RM Gy Ey - - ADOX F=ADX EFL=M------- +# +# FPU +# Source for UNDOC opcodes: https://www.sandpile.org/x86/opc_fpu.htm +d8/0m M Md - - - FADD F=387 ENC_SEPSZ +d8/1m M Md - - - FMUL F=387 ENC_SEPSZ +d8/2m M Md - - - FCOM F=387 ENC_SEPSZ +d8/3m M Md - - - FCOMP F=387 ENC_SEPSZ +d8/4m M Md - - - FSUB F=387 ENC_SEPSZ +d8/5m M Md - - - FSUBR F=387 ENC_SEPSZ +d8/6m M Md - - - FDIV F=387 ENC_SEPSZ +d8/7m M Md - - - FDIVR F=387 ENC_SEPSZ +d8/0r AM Ft Ft - - FADD F=387 +d8/1r AM Ft Ft - - FMUL F=387 +d8/2r AM Ft Ft - - FCOM F=387 +d8/3r AM Ft Ft - - FCOMP F=387 +d8/4r AM Ft Ft - - FSUB F=387 +d8/5r AM Ft Ft - - FSUBR F=387 +d8/6r AM Ft Ft - - FDIV F=387 +d8/7r AM Ft Ft - - FDIVR F=387 +d9/0m M Md - - - FLD F=387 ENC_SEPSZ +d9/2m M Md - - - FST F=387 ENC_SEPSZ +d9/3m M Md - - - FSTP F=387 ENC_SEPSZ +d9/4m M M - - - FLDENV F=387 +d9/5m M Mw - - - FLDCW F=387 +d9/6m M M - - - FSTENV F=387 +d9/7m M Mw - - - FSTCW F=387 +d9/0r M Ft - - - FLD F=387 +d9/1r M Ft - - - FXCH F=387 +d9d0 NP - - - - FNOP F=387 +d9/3r MA Ft Ft - - FSTPNCE F=387 UNDOC +d9e0 NP - - - - FCHS F=387 +d9e1 NP - - - - FABS F=387 +d9e4 NP - - - - FTST F=387 +d9e5 NP - - - - FXAM F=387 +d9e8 NP - - - - FLD1 F=387 +d9e9 NP - - - - FLDL2T F=387 +d9ea NP - - - - FLDL2E F=387 +d9eb NP - - - - FLDPI F=387 +d9ec NP - - - - FLDLG2 F=387 +d9ed NP - - - - FLDLN2 F=387 +d9ee NP - - - - FLDZ F=387 +d9f0 NP - - - - F2XM1 F=387 +d9f1 NP - - - - FYL2X F=387 +d9f2 NP - - - - FPTAN F=387 +d9f3 NP - - - - FPATAN F=387 +d9f4 NP - - - - FXTRACT F=387 +d9f5 NP - - - - FPREM1 F=387 +d9f6 NP - - - - FDECSTP F=387 +d9f7 NP - - - - FINCSTP F=387 +d9f8 NP - - - - FPREM F=387 +d9f9 NP - - - - FYL2XP1 F=387 +d9fa NP - - - - FSQRT F=387 +d9fb NP - - - - FSINCOS F=387 +d9fc NP - - - - FRNDINT F=387 +d9fd NP - - - - FSCALE F=387 +d9fe NP - - - - FSIN F=387 +d9ff NP - - - - FCOS F=387 +da/0m M Md - - - FIADD F=387 ENC_SEPSZ +da/1m M Md - - - FIMUL F=387 ENC_SEPSZ +da/2m M Md - - - FICOM F=387 ENC_SEPSZ +da/3m M Md - - - FICOMP F=387 ENC_SEPSZ +da/4m M Md - - - FISUB F=387 ENC_SEPSZ +da/5m M Md - - - FISUBR F=387 ENC_SEPSZ +da/6m M Md - - - FIDIV F=387 ENC_SEPSZ +da/7m M Md - - - FIDIVR F=387 ENC_SEPSZ +da/0r M Ft - - - FCMOVB F=686 EFL=-------t +da/1r M Ft - - - FCMOVE F=686 EFL=----t--- +da/2r M Ft - - - FCMOVBE F=686 EFL=----t--t +da/3r M Ft - - - FCMOVU F=686 EFL=------t- +dae9 NP - - - - FUCOMPP F=387 +db/0m M Md - - - FILD F=387 ENC_SEPSZ +db/1m M Md - - - FISTTP F=SSE3 ENC_SEPSZ +db/2m M Md - - - FIST F=387 ENC_SEPSZ +db/3m M Md - - - FISTP F=387 ENC_SEPSZ +db/5m M Mt - - - FLD F=387 ENC_SEPSZ +db/7m M Mt - - - FSTP F=387 ENC_SEPSZ +db/0r M Ft - - - FCMOVNB F=686 EFL=-------t +db/1r M Ft - - - FCMOVNE F=686 EFL=----t--- +db/2r M Ft - - - FCMOVNBE F=686 EFL=----t--t +db/3r M Ft - - - FCMOVNU F=686 EFL=------t- +dbe0 NP - - - - FENI8087_NOP F=387 UNDOC +dbe1 NP - - - - FDISI8087_NOP F=387 UNDOC +dbe2 NP - - - - FCLEX F=387 +dbe3 NP - - - - FINIT F=387 +dbe4 NP - - - - FSETPM287_NOP F=387 UNDOC +dbe5 NP - - - - FSETPM287_NOP F=387 UNDOC +db/5r M Ft - - - FUCOMI F=686 EFL=0--0m0mm +db/6r M Ft - - - FCOMI F=686 EFL=0--0m0mm +dc/0m M Mq - - - FADD F=387 ENC_SEPSZ +dc/1m M Mq - - - FMUL F=387 ENC_SEPSZ +dc/2m M Mq - - - FCOM F=387 ENC_SEPSZ +dc/3m M Mq - - - FCOMP F=387 ENC_SEPSZ +dc/4m M Mq - - - FSUB F=387 ENC_SEPSZ +dc/5m M Mq - - - FSUBR F=387 ENC_SEPSZ +dc/6m M Mq - - - FDIV F=387 ENC_SEPSZ +dc/7m M Mq - - - FDIVR F=387 ENC_SEPSZ +dc/0r MA Ft Ft - - FADD F=387 +dc/1r MA Ft Ft - - FMUL F=387 +dc/2r MA Ft Ft - - FCOM F=387 UNDOC +dc/3r MA Ft Ft - - FCOMP F=387 UNDOC +dc/4r MA Ft Ft - - FSUBR F=387 +dc/5r MA Ft Ft - - FSUB F=387 +dc/6r MA Ft Ft - - FDIVR F=387 +dc/7r MA Ft Ft - - FDIV F=387 +dd/0m M Mq - - - FLD F=387 ENC_SEPSZ +dd/1m M Mq - - - FISTTP F=387 ENC_SEPSZ +dd/2m M Mq - - - FST F=387 ENC_SEPSZ +dd/3m M Mq - - - FSTP F=387 ENC_SEPSZ +dd/4m M M - - - FRSTOR F=387 +dd/6m M M - - - FSAVE F=387 +dd/7m M Mw - - - FSTSW F=387 +dd/0r M Ft - - - FFREE F=387 +dd/1r AM Ft Ft - - FXCH F=387 UNDOC +dd/2r M Ft - - - FST F=387 +dd/3r M Ft - - - FSTP F=387 +dd/4r M Ft - - - FUCOM F=387 +dd/5r M Ft - - - FUCOMP F=387 +de/0m M Mw - - - FIADD F=387 ENC_SEPSZ +de/1m M Mw - - - FIMUL F=387 ENC_SEPSZ +de/2m M Mw - - - FICOM F=387 ENC_SEPSZ +de/3m M Mw - - - FICOMP F=387 ENC_SEPSZ +de/4m M Mw - - - FISUB F=387 ENC_SEPSZ +de/5m M Mw - - - FISUBR F=387 ENC_SEPSZ +de/6m M Mw - - - FIDIV F=387 ENC_SEPSZ +de/7m M Mw - - - FIDIVR F=387 ENC_SEPSZ +de/0r MA Ft Ft - - FADDP F=387 +de/1r MA Ft Ft - - FMULP F=387 +de/2r AM Ft Ft - - FCOMP F=387 UNDOC +ded9 NP - - - - FCOMPP F=387 +de/4r MA Ft Ft - - FSUBRP F=387 +de/5r MA Ft Ft - - FSUBP F=387 +de/6r MA Ft Ft - - FDIVRP F=387 +de/7r MA Ft Ft - - FDIVP F=387 +df/0m M Mw - - - FILD F=387 ENC_SEPSZ +df/1m M Mw - - - FISTTP F=387 ENC_SEPSZ +df/2m M Mw - - - FIST F=387 ENC_SEPSZ +df/3m M Mw - - - FISTP F=387 ENC_SEPSZ +df/4m M Mt - - - FBLD F=387 +df/5m M Mq - - - FILD F=387 ENC_SEPSZ +df/6m M Mt - - - FBSTP F=387 +df/7m M Mq - - - FISTP F=387 ENC_SEPSZ +df/0r M Ft - - - FFREEP F=387 UNDOC +df/1r AM Ft Ft - - FXCH F=387 UNDOC +df/2r MA Ft Ft - - FSTP F=387 UNDOC +df/3r MA Ft Ft - - FSTP F=387 UNDOC +# FSTSW AX +dfe0 A Rw - - - FSTSW F=387 +df/5r AM Ft Ft - - FUCOMIP F=686 EFL=0--0m0mm +df/6r AM Ft Ft - - FCOMIP F=686 EFL=0--0m0mm +# +# Control Flow Enforcement +F3.0f01/5m M Mq - - - RSTORSSP F=CET +F3.0f01e8 NP - - - - SETSSBSY F=CET CPL0 +F3.0f01ea NP - - - - SAVEPREVSSP F=CET +F3.0f1e/1r M Ry - - - RDSSP F=CET +F3.0f1efa NP - - - - ENDBR64 F=CET +F3.0f1efb NP - - - - ENDBR32 F=CET +66.0f38f5/m MR My Gy - - WRUSS F=CET +NP.0f38f6/m MR My Gy - - WRSS F=CET +F3.0fae/6m M Mq - - - CLRSSBSY F=CET CPL0 +F3.0fae/5r M Ry - - - INCSSP F=CET +# +# CLDEMOTE +NP.0f1c/0m M Mb - - - CLDEMOTE F=CLDEMOTE + +# VIA PadLock +F3.0fa6c0 NP - - - - REP_MONTMUL F=PADLOCK ONLYVIA +F3.0fa6c8 NP - - - - REP_XSHA1 F=PADLOCK ONLYVIA +F3.0fa6d0 NP - - - - REP_XSHA256 F=PADLOCK ONLYVIA +NFx.0fa7c0 NP - - - - XSTORE F=PADLOCK ONLYVIA +F3.0fa7c0 NP - - - - REP_XSTORE F=PADLOCK ONLYVIA +F3.0fa7c8 NP - - - - REP_XCRYPTECB F=PADLOCK ONLYVIA +F3.0fa7d0 NP - - - - REP_XCRYPTCBC F=PADLOCK ONLYVIA +F3.0fa7d8 NP - - - - REP_XCRYPTCTR F=PADLOCK ONLYVIA +F3.0fa7e0 NP - - - - REP_XCRYPTCFB F=PADLOCK ONLYVIA +F3.0fa7e8 NP - - - - REP_XCRYPTOFB F=PADLOCK ONLYVIA + +# VMX +66.0f3880/m RM Gy Mdq - - INVEPT D64 F=VMX EFL=0--0m00m CPL0 +66.0f3881/m RM Gy Mdq - - INVVPID D64 F=VMX EFL=0--0m00m CPL0 +NP.0f01c1 NP - - - - VMCALL F=VMX EFL=0--0m00m CPL0 +66.0fc7/6m M Mq - - - VMCLEAR F=VMX EFL=0--0m00m CPL0 +NP.0f01d4 NP - - - - VMFUNC F=VMX EFL=0--0m00m +NP.0f01c2 NP - - - - VMLAUNCH F=VMX EFL=0--0m00m CPL0 +NP.0f01c3 NP - - - - VMRESUME F=VMX EFL=0--0m00m CPL0 +NP.0fc7/6m M Mq - - - VMPTRLD F=VMX EFL=0--0m00m CPL0 +NP.0fc7/7m M Mq - - - VMPTRST F=VMX EFL=0--0m00m CPL0 +NP.0f78 MR Ey Gy - - VMREAD D64 F=VMX EFL=0--0m00m CPL0 +NP.0f79 RM Gy Ey - - VMWRITE D64 F=VMX EFL=0--0m00m CPL0 +NP.0f01c4 NP - - - - VMXOFF F=VMX EFL=0--0m00m CPL0 +F3.0fc7/6m M Mq - - - VMXON F=VMX EFL=0--0m00m CPL0 +# SEAM/TDX +66.0f01cc NP - - - - TDCALL F=SEAM +66.0f01cd NP - - - - SEAMRET F=SEAM +66.0f01ce NP - - - - SEAMOPS F=SEAM +66.0f01cf NP - - - - SEAMCALL F=SEAM + +# AMD CLZERO +0f01fc A Rv - - - CLZERO F=CLZERO ONLYAMD + +# AMD RDPRU +# Tested on hardware, 66 prefix also accepted. F2/F3 trigger UD. +NFx.0f01fd NP - - - - RDPRU F=RDPRU ONLYAMD + +# AMD SVM +0f01d8 NP - - - - VMRUN F=SVM ONLYAMD CPL0 +NFx.0f01d9 NP - - - - VMMCALL F=SVM ONLYAMD +F3.0f01d9 NP - - - - VMGEXIT F=SEVES ONLYAMD +F2.0f01d9 NP - - - - VMGEXIT F=SEVES ONLYAMD +0f01da NP - - - - VMLOAD F=SVM ONLYAMD CPL0 +0f01db NP - - - - VMSAVE F=SVM ONLYAMD CPL0 +0f01dc NP - - - - STGI F=SKINIT ONLYAMD CPL0 +0f01dd NP - - - - CLGI F=SKINIT ONLYAMD CPL0 +0f01de NP - - - - SKINIT EFL=00000000 F=SKINIT ONLYAMD CPL0 +0f01df NP - - - - INVLPGA F=SVM ONLYAMD CPL0 +NP.0f01fa NP - - - - MONITORX F=MONITORX ONLYAMD +F3.0f01fa NP - - - - MCOMMIT F=MCOMMIT ONLYAMD +NP.0f01fb NP - - - - MWAITX F=MONITORX ONLYAMD +NP.0f01fe NP - - - - INVLPGB F=INVLPGB ONLYAMD CPL0 +NP.0f01ff NP - - - - TLBSYNC F=INVLPGB ONLYAMD CPL0 + +# AMD SNP +F3.0f01fd NP - - - - RMPQUERY O64 EFL=m--mmmm- F=RMPQUERY ONLYAMD CPL0 +F2.0f01fd NP - - - - RMPREAD O64 EFL=m--mmmm- F=RMPREAD ONLYAMD CPL0 +F3.0f01fe NP - - - - RMPADJUST O64 EFL=m--mmmm- F=SNP ONLYAMD CPL0 +F2.0f01fe NP - - - - RMPUPDATE O64 EFL=m--mmmm- F=SNP ONLYAMD CPL0 +F3.0f01ff NP - - - - PSMASH O64 EFL=m--mmmm- F=SNP ONLYAMD +F2.0f01ff NP - - - - PVALIDATE O64 EFL=m--mmmmm F=SNP ONLYAMD + +# WAITPKG +66.0fae/6r M Rd - - - TPAUSE F=WAITPKG EFL=0--0000m +# TODO: Ry operand is address-sized +F3.0fae/6r M Ry - - - UMONITOR F=WAITPKG +F2.0fae/6r M Rd - - - UMWAIT F=WAITPKG EFL=0--0000m + +# PRWRITE +F3.0fae/4 M Ey - - - PTWRITE F=PTWRITE + +# GFNI +66.0f38cf RM Vx Wx - - GF2P8MULB F=GFNI +66.0f3ace RMI Vx Wx Ib - GF2P8AFFINEQB F=GFNI +66.0f3acf RMI Vx Wx Ib - GF2P8AFFINEINVQB F=GFNI +VEX.66.W0.0f38cf RVM Vx Hx Wx - VGF2P8MULB F=AVX,GFNI +VEX.66.W1.0f3ace RVMI Vx Hx Wx Ib VGF2P8AFFINEQB F=AVX,GFNI +VEX.66.W1.0f3acf RVMI Vx Hx Wx Ib VGF2P8AFFINEINVQB F=AVX,GFNI +EVEX.66.W0.0f38cf RVM Vx Hx Wx - EVX_GF2P8MULB+k F=AVX,GFNI TUPLE_FULL_MEM +EVEX.66.W1.0f3ace RVMI Vx Hx Wx Ib EVX_GF2P8AFFINEQB+kb F=AVX512F,GFNI TUPLE_FULL_64 +EVEX.66.W1.0f3acf RVMI Vx Hx Wx Ib EVX_GF2P8AFFINEINVQB+kb F=AVX512F,GFNI TUPLE_FULL_64 + +# ENQCMD +# TODO: Gy operands are address-sized +F2.0f38f8/m RM Gy Moq - - ENQCMD F=ENQCMD +F3.0f38f8/m RM Gy Moq - - ENQCMDS F=ENQCMD + +# PCONFIG +NP.0f01c5 NP - - - - PCONFIG F=PCONFIG + +# WBNOINVD +F3.0f09 NP - - - - WBNOINVD F=WBNOINVD CPL0 + +NP.0f01ee NP - - - - RDPKRU F=OSPKE +NP.0f01ef NP - - - - WRPKRU F=OSPKE +F3.0fae/0r M Ry - - - RDFSBASE O64 F=FSGSBASE +F3.0fae/1r M Ry - - - RDGSBASE O64 F=FSGSBASE +F3.0fae/2r M Ry - - - WRFSBASE O64 F=FSGSBASE +F3.0fae/3r M Ry - - - WRGSBASE O64 F=FSGSBASE +NP.0fae/4m M M - - - XSAVE+w F=XSAVE +NP.0fae/5m M M - - - XRSTOR+w F=XSAVE +NP.0fae/6m M M - - - XSAVEOPT+w F=XSAVEOPT +66.0fae/6m M Mb - - - CLWB F=CLWB +NP.0fae/7m M Mb - - - CLFLUSH F=CLFLSH +66.0fae/7m M Mb - - - CLFLUSHOPT F=CLFLUSHOPT +NP.0fc7/3m M M - - - XRSTORS+w F=XSS +NP.0fc7/4m M M - - - XSAVEC+w F=XSAVEC +NP.0fc7/5m M M - - - XSAVES+w F=XSS +NFx.0fc7/6r M Rv - - - RDRAND F=RDRAND EFL=0--0000m +NFx.0fc7/7r M Rv - - - RDSEED F=RDSEED EFL=0--0000m +F3.0fc7/7r M Ry - - - RDPID D64 F=RDPID +66.0f3882/m RM Gy Mdq - - INVPCID D64 F=INVPCID CPL0 +NP.0f38c8 RM Vdq Wdq - - SHA1NEXTE F=SHA +NP.0f38c9 RM Vdq Wdq - - SHA1MSG1 F=SHA +NP.0f38ca RM Vdq Wdq - - SHA1MSG2 F=SHA +NP.0f38cb RMA Vdq Wdq Hdq - SHA256RNDS2 F=SHA +NP.0f38cc RM Vdq Wdq - - SHA256MSG1 F=SHA +NP.0f38cd RM Vdq Wdq - - SHA256MSG2 F=SHA +NP.0f3acc RMI Vdq Wdq Ib - SHA1RNDS4 F=SHA + +#NP.0f1a/m RM Z M - - BNDLDX F=MPX +#66.0f1a RM Z Z - - BNDMOV D64 F=MPX +#F2.0f1a RM Z Ey - - BNDCU D64 F=MPX +#F3.0f1a RM Z Ey - - BNDCL D64 F=MPX +#NP.0f1b/m MR M Z - - BNDSTX F=MPX +#66.0f1b MR Z Z - - BNDMOV D64 F=MPX +#F2.0f1b RM Z Ey - - BNDCN D64 F=MPX +#F3.0f1b/m RM Z M - - BNDMK F=MPX + +# TSXLDTRK +F2.0f01e8 NP - - - - XSUSLDTRK F=TSXLDTRK +F2.0f01e9 NP - - - - XRESLDTRK F=TSXLDTRK + +# AVX_VNNI +VEX.NP.W0.0f3850 RVM Vx Hx Wx - VPDPBUUD F=VNNI-INT8 +VEX.66.W0.0f3850 RVM Vx Hx Wx - VPDPBUSD F=VNNI +VEX.F3.W0.0f3850 RVM Vx Hx Wx - VPDPBSUD F=VNNI-INT8 +VEX.F2.W0.0f3850 RVM Vx Hx Wx - VPDPBSSD F=VNNI-INT8 +VEX.NP.W0.0f3851 RVM Vx Hx Wx - VPDPBUUDS F=VNNI-INT8 +VEX.66.W0.0f3851 RVM Vx Hx Wx - VPDPBUSDS F=VNNI +VEX.F3.W0.0f3851 RVM Vx Hx Wx - VPDPBSUDS F=VNNI-INT8 +VEX.F2.W0.0f3851 RVM Vx Hx Wx - VPDPBSSDS F=VNNI-INT8 +VEX.66.W0.0f3852 RVM Vx Hx Wx - VPDPWSSD F=VNNI +VEX.66.W0.0f3853 RVM Vx Hx Wx - VPDPWSSDS F=VNNI + +# AVX-NE-CONVERT +VEX.NP.W0.0f38b0/m RM Vx Mx - - VCVTNEOPH2PS F=AVX-NE-CONVERT +VEX.66.W0.0f38b0/m RM Vx Mx - - VCVTNEEPH2PS F=AVX-NE-CONVERT +VEX.F3.W0.0f38b0/m RM Vx Mx - - VCVTNEEBF162PS F=AVX-NE-CONVERT +VEX.F2.W0.0f38b0/m RM Vx Mx - - VCVTNEOBF162PS F=AVX-NE-CONVERT +VEX.66.W0.0f38b1/m RM Vx Mw - - VBCSTNESH2PS F=AVX-NE-CONVERT +VEX.F3.W0.0f38b1/m RM Vx Mw - - VBCSTNEBF162PS F=AVX-NE-CONVERT +VEX.F3.W0.0f3872 RM Vh Wps - - VCVTNEPS2BF16 F=AVX-NE-CONVERT + +# AVX-IFMA +VEX.66.W1.0f38b4 RVM Vx Hx Wx - VPMADD52LUQ F=AVX-IFMA +VEX.66.W1.0f38b5 RVM Vx Hx Wx - VPMADD52HUQ F=AVX-IFMA + +# HRESET +F3.0f3af0c0 I Ib - - - HRESET F=HRESET + +# SERIALIZE +NP.0f01e8 NP - - - - SERIALIZE F=SERIALIZE + +# UINTR +F3.0f01ec NP - - - - UIRET O64 F=UINTR +F3.0f01ed NP - - - - TESTUI O64 F=UINTR +F3.0f01ee NP - - - - CLUI O64 F=UINTR +F3.0f01ef NP - - - - STUI O64 F=UINTR +F3.0fc7/6r M Ry - - - SENDUIPI O64 D64 F=UINTR + +# WRMSRNS +NP.0f01c6 NP - - - - WRMSRNS F=WRMSRNS CPL0 + +# MSRLIST +F2.0f01c6 NP - - - - RDMSRLIST O64 F=MSRLIST CPL0 +F3.0f01c6 NP - - - - WRMSRLIST O64 F=MSRLIST CPL0 + +# RAO-INT +NP.0f38fc/m MR My Gy - - AADD F=RAO-INT +66.0f38fc/m MR My Gy - - AAND F=RAO-INT +F3.0f38fc/m MR My Gy - - AXOR F=RAO-INT +F2.0f38fc/m MR My Gy - - AOR F=RAO-INT + +# CMPCCXADD +VEX.66.L0.0f38e0/m MRV My Gy By - CMPOXADD O64 F=CMPCCXADD EFL=m--mmmmm ENC_CC_BEGIN +VEX.66.L0.0f38e1/m MRV My Gy By - CMPNOXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38e2/m MRV My Gy By - CMPBXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38e3/m MRV My Gy By - CMPNBXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38e4/m MRV My Gy By - CMPZXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38e5/m MRV My Gy By - CMPNZXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38e6/m MRV My Gy By - CMPBEXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38e7/m MRV My Gy By - CMPNBEXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38e8/m MRV My Gy By - CMPSXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38e9/m MRV My Gy By - CMPNSXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38ea/m MRV My Gy By - CMPPXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38eb/m MRV My Gy By - CMPNPXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38ec/m MRV My Gy By - CMPLXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38ed/m MRV My Gy By - CMPNLXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38ee/m MRV My Gy By - CMPLEXADD O64 F=CMPCCXADD EFL=m--mmmmm +VEX.66.L0.0f38ef/m MRV My Gy By - CMPNLEXADD O64 F=CMPCCXADD EFL=m--mmmmm + +# AESKLE/KL (Key Locker) +F3.0f38d8/0m M M - - - AESENCWIDE128KL F=AESKLE +F3.0f38d8/1m M M - - - AESDECWIDE128KL F=AESKLE +F3.0f38d8/2m M M - - - AESENCWIDE256KL F=AESKLE +F3.0f38d8/3m M M - - - AESDECWIDE256KL F=AESKLE +F3.0f38dc/m RM Vx M - - AESENC128KL F=AESKLE +F3.0f38dc/r RM Vx Ux - - LOADIWKEY F=AESKLE +F3.0f38dd/m RM Vx M - - AESDEC128KL F=AESKLE +F3.0f38de/m RM Vx M - - AESENC256KL F=AESKLE +F3.0f38df/m RM Vx M - - AESDEC256KL F=AESKLE +F3.0f38fa/r RM Gd Rd - - ENCODEKEY128 F=AESKLE +F3.0f38fb/r RM Gd Rd - - ENCODEKEY256 F=AESKLE + +# FRED +F2.0f00/6 M Ew - - - LKGS F=FRED +F3.0f01ca NP - - - - ERETU F=FRED +F2.0f01ca NP - - - - ERETS F=FRED + +# AMX +VEX.NP.W0.L0.0f3849/0m M M - - - LDTILECFG O64 F=AMX-TILE +VEX.66.W0.L0.0f3849/0m M M - - - STTILECFG O64 F=AMX-TILE +VEX.NP.W0.L0.0f3849c0 NP - - - - TILERELEASE O64 F=AMX-TILE +VEX.F2.W0.L0.0f3849/r0 R T - - - TILEZERO O64 F=AMX-TILE +VEX.66.W0.L0.0f384b/m4 RM T M - - TILELOADDT1 O64 F=AMX-TILE +VEX.F3.W0.L0.0f384b/m4 MR M T - - TILESTORED O64 F=AMX-TILE +VEX.F2.W0.L0.0f384b/m4 RM T M - - TILELOADD O64 F=AMX-TILE +VEX.F3.W0.L0.0f385c/r RMV T T T - TDPBF16PS O64 F=AMX-BF16 +VEX.F2.W0.L0.0f385c/r RMV T T T - TDPFP16PS O64 F=AMX-FP16 +VEX.NP.W0.L0.0f385e/r RMV T T T - TDPBUUD O64 F=AMX-INT8 +VEX.66.W0.L0.0f385e/r RMV T T T - TDPBUSD O64 F=AMX-INT8 +VEX.F3.W0.L0.0f385e/r RMV T T T - TDPBSUD O64 F=AMX-INT8 +VEX.F2.W0.L0.0f385e/r RMV T T T - TDPBSSD O64 F=AMX-INT8 +VEX.NP.W0.L0.0f386c/r RMV T T T - TCMMRLFP16PS O64 F=AMX-COMPLEX +VEX.66.W0.L0.0f386c/r RMV T T T - TCMMIMFP16PS O64 F=AMX-COMPLEX + +# PBNDKB +NP.0f01c7 NP - - - - PBNDKB O64 F=PBNDKB CPL0 + +# MSR_IMM +VEX.F2.W0.L0.M7.f6/0r MI Rq Id - - RDMSR O64 F=MSR_IMM CPL0 +VEX.F3.W0.L0.M7.f6/0r IM Id Rq - - WRMSRNS O64 F=MSR_IMM CPL0 + +# USER_MSR +F2.0f38f8/r MR Rq Gq - - URDMSR O64 F=USER_MSR +F3.0f38f8/r MR Rq Gq - - UWRMSR O64 F=USER_MSR +VEX.F2.W0.L0.M7.f8/0r MI Rq Id - - URDMSR O64 F=USER_MSR +VEX.F3.W0.L0.M7.f8/0r IM Id Rq - - UWRMSR O64 F=USER_MSR + +# SM4 +VEX.F3.W0.0f38da RVM Vx Hx Wx - VSM4KEY4 F=AVX,SM4 +VEX.F2.W0.0f38da RVM Vx Hx Wx - VSM4RNDS4 F=AVX,SM4 +EVEX.F3.W0.0f38da RVM Vx Hx Wx - VSM4KEY4 F=AVX10.2,SM4 TUPLE_FULL_MEM +EVEX.F2.W0.0f38da RVM Vx Hx Wx - VSM4RNDS4 F=AVX10.2,SM4 TUPLE_FULL_MEM + +# AVX512 +EVEX.NP.W0.0f58 RVM Vps Hps Wps - EVX_ADDPS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f58 RVM Vpd Hpd Wpd - EVX_ADDPD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.LIG.0f58 RVM Vdq Hdq Wss - EVX_ADDSS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.F2.W1.LIG.0f58 RVM Vdq Hdq Wsd - EVX_ADDSD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.0f38dc RVM Vx Hx Wx - EVX_AESENC F=AVX512F,VAES TUPLE_FULL_MEM +EVEX.66.0f38dd RVM Vx Hx Wx - EVX_AESENCLAST F=AVX512F,VAES TUPLE_FULL_MEM +EVEX.66.0f38de RVM Vx Hx Wx - EVX_AESDEC F=AVX512F,VAES TUPLE_FULL_MEM +EVEX.66.0f38df RVM Vx Hx Wx - EVX_AESDECLAST F=AVX512F,VAES TUPLE_FULL_MEM +EVEX.NP.W0.0f54 RVM Vps Hps Wps - EVX_ANDPS+kb F=AVX512DQ TUPLE_FULL_32 +EVEX.66.W1.0f54 RVM Vpd Hpd Wpd - EVX_ANDPD+kb F=AVX512DQ TUPLE_FULL_64 +EVEX.NP.W0.0f55 RVM Vps Hps Wps - EVX_ANDNPS+kb F=AVX512DQ TUPLE_FULL_32 +EVEX.66.W1.0f55 RVM Vpd Hpd Wpd - EVX_ANDNPD+kb F=AVX512DQ TUPLE_FULL_64 +EVEX.NP.W0.0fc2 RVMI Kb Hps Wps Ib EVX_CMPPS+kbe F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0fc2 RVMI Kb Hpd Wpd Ib EVX_CMPPD+kbe F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.LIG.0fc2 RVMI Kb Hss Wss Ib EVX_CMPSS+ke F=AVX512F TUPLE1_SCALAR_32 +EVEX.F2.W1.LIG.0fc2 RVMI Kb Hsd Wsd Ib EVX_CMPSD+ke F=AVX512F TUPLE1_SCALAR_64 +EVEX.NP.W0.LIG.0f2f RM Vss Wss - - EVX_COMISS+e F=AVX512F TUPLE1_SCALAR_32 EFL=0--0m0mm +EVEX.66.W1.LIG.0f2f RM Vsd Wsd - - EVX_COMISD+e F=AVX512F TUPLE1_SCALAR_64 EFL=0--0m0mm +# Note: SAE is ignored +EVEX.F3.W0.0fe6 RM Vpd Wh - - EVX_CVTDQ2PD+kbe F=AVX512F TUPLE_HALF_32 +EVEX.F2.W1.0fe6 RM Vh Wpd - - EVX_CVTPD2DQ+kbr F=AVX512F TUPLE_FULL_64 +EVEX.NP.W0.0f5b RM Vps Wps - - EVX_CVTDQ2PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W0.0f5b RM Vps Wps - - EVX_CVTPS2DQ+kbr F=AVX512F TUPLE_FULL_32 +EVEX.NP.W0.0f5a RM Vpd Wh - - EVX_CVTPS2PD+kbe F=AVX512F TUPLE_HALF_32 +EVEX.66.W1.0f5a RM Vh Wpd - - EVX_CVTPD2PS+kbr F=AVX512F TUPLE_FULL_64 +EVEX.F3.LIG.0f2d RM Gy Wss - - EVX_CVTSS2SI+r F=AVX512F TUPLE1_FIXED_32 +EVEX.F2.LIG.0f2d RM Gy Wsd - - EVX_CVTSD2SI+r F=AVX512F TUPLE1_FIXED_64 +EVEX.F3.W0.LIG.0f5a RVM Vdq Hdq Wss - EVX_CVTSS2SD+ke F=AVX512F TUPLE1_SCALAR_32 +EVEX.F2.W1.LIG.0f5a RVM Vdq Hdq Wsd - EVX_CVTSD2SS+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.F3.LIG.0f2a RVM Vdq Hdq Ey - EVX_CVTSI2SS+r F=AVX512F TUPLE1_SCALAR_OPSZ +# Note: for W0, ER is ignored (i.e., will not UD, according to Intel SDM) +EVEX.F2.LIG.0f2a RVM Vdq Hdq Ey - EVX_CVTSI2SD+r F=AVX512F TUPLE1_SCALAR_OPSZ +EVEX.66.W1.0fe6 RM Vh Wpd - - EVX_CVTTPD2DQ+kbe F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.0f5b RM Vps Wps - - EVX_CVTTPS2DQ+kbe F=AVX512F TUPLE_FULL_32 +EVEX.F2.LIG.0f2c RM Gy Wsd - - EVX_CVTTSD2SI+e F=AVX512F TUPLE1_FIXED_64 +EVEX.F3.LIG.0f2c RM Gy Wss - - EVX_CVTTSS2SI+e F=AVX512F TUPLE1_FIXED_32 +EVEX.NP.W0.0f5e RVM Vps Hps Wps - EVX_DIVPS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f5e RVM Vpd Hpd Wpd - EVX_DIVPD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.LIG.0f5e RVM Vdq Hdq Wss - EVX_DIVSS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.F2.W1.LIG.0f5e RVM Vdq Hdq Wsd - EVX_DIVSD+kr F=AVX512F TUPLE1_SCALAR_64 +# Note: tuple size is actually fixed at 32 bits, regardless of EVEX.W +EVEX.66.L0.0f3a17 MRI Ess Vdq Ib - EVX_EXTRACTPS F=AVX512F TUPLE1_FIXED_32 +EVEX.66.W0.L0.0f3a21 RVMI Vdq Hdq Wss Ib EVX_INSERTPS F=AVX512F TUPLE1_SCALAR_32 +EVEX.NP.W0.0f5f RVM Vps Hps Wps - EVX_MAXPS+kbe F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f5f RVM Vpd Hpd Wpd - EVX_MAXPD+kbe F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.LIG.0f5f RVM Vdq Hdq Wss - EVX_MAXSS+ke F=AVX512F TUPLE1_SCALAR_32 +EVEX.F2.W1.LIG.0f5f RVM Vdq Hdq Wsd - EVX_MAXSD+ke F=AVX512F TUPLE1_SCALAR_64 +EVEX.NP.W0.0f5d RVM Vps Hps Wps - EVX_MINPS+kbe F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f5d RVM Vpd Hpd Wpd - EVX_MINPD+kbe F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.LIG.0f5d RVM Vdq Hdq Wss - EVX_MINSS+ke F=AVX512F TUPLE1_SCALAR_32 +EVEX.F2.W1.LIG.0f5d RVM Vdq Hdq Wsd - EVX_MINSD+ke F=AVX512F TUPLE1_SCALAR_64 +EVEX.NP.W0.0f28 RM Vps Wps - - EVX_MOVAPS+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.W1.0f28 RM Vpd Wpd - - EVX_MOVAPD+k F=AVX512F TUPLE_FULL_MEM +EVEX.NP.W0.0f29 MR Wps Vps - - EVX_MOVAPS+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.W1.0f29 MR Wpd Vpd - - EVX_MOVAPD+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.L0.0f7e MR Ey Vy - - EVX_MOV_X2G F=AVX512F TUPLE1_SCALAR_OPSZ +EVEX.66.L0.0f6e RM Vy Ey - - EVX_MOV_G2X F=AVX512F TUPLE1_SCALAR_OPSZ +EVEX.F2.W1.L0.0f12 RM Vpd Wq - - EVX_MOVDDUP+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.F2.W1.L12.0f12 RM Vpd Wpd - - EVX_MOVDDUP+k F=AVX512F TUPLE_MOVDDUP +EVEX.66.W0.0f6f RM Vx Wx - - EVX_MOVDQA32+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.W1.0f6f RM Vx Wx - - EVX_MOVDQA64+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.W0.0f7f MR Wx Vx - - EVX_MOVDQA32+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.W1.0f7f MR Wx Vx - - EVX_MOVDQA64+k F=AVX512F TUPLE_FULL_MEM +EVEX.F3.W0.0f6f RM Vx Wx - - EVX_MOVDQU32+k F=AVX512F TUPLE_FULL_MEM +EVEX.F3.W1.0f6f RM Vx Wx - - EVX_MOVDQU64+k F=AVX512F TUPLE_FULL_MEM +EVEX.F3.W0.0f7f MR Wx Vx - - EVX_MOVDQU32+k F=AVX512F TUPLE_FULL_MEM +EVEX.F3.W1.0f7f MR Wx Vx - - EVX_MOVDQU64+k F=AVX512F TUPLE_FULL_MEM +EVEX.F2.W0.0f6f RM Vx Wx - - EVX_MOVDQU8+k F=AVX512BW TUPLE_FULL_MEM +EVEX.F2.W1.0f6f RM Vx Wx - - EVX_MOVDQU16+k F=AVX512BW TUPLE_FULL_MEM +EVEX.F2.W0.0f7f MR Wx Vx - - EVX_MOVDQU8+k F=AVX512BW TUPLE_FULL_MEM +EVEX.F2.W1.0f7f MR Wx Vx - - EVX_MOVDQU16+k F=AVX512BW TUPLE_FULL_MEM +EVEX.NP.W0.L0.0f12/m RVM Vdq Hdq Mq - EVX_MOVLPS F=AVX512F TUPLE2_32 +EVEX.NP.W0.L0.0f12/r RVM Vdq Hdq Udq - EVX_MOVHLPS F=AVX512F +EVEX.66.W1.L0.0f12/m RVM Vdq Hdq Msd - EVX_MOVLPD F=AVX512F TUPLE1_SCALAR_64 +EVEX.NP.W0.L0.0f13/m MR Mq Vq - - EVX_MOVLPS F=AVX512F TUPLE2_32 +EVEX.66.W1.L0.0f13/m MR Msd Vsd - - EVX_MOVLPD F=AVX512F TUPLE1_SCALAR_64 +EVEX.NP.W0.L0.0f16/m RVM Vdq Hq Mq - EVX_MOVHPS F=AVX512F TUPLE2_32 +EVEX.NP.W0.L0.0f16/r RVM Vdq Hq Uq - EVX_MOVLHPS F=AVX512F +EVEX.66.W1.L0.0f16/m RVM Vdq Hsd Msd - EVX_MOVHPD F=AVX512F TUPLE1_SCALAR_64 +EVEX.NP.W0.L0.0f17/m MR Mq Vq - - EVX_MOVHPS F=AVX512F TUPLE2_32 +EVEX.66.W1.L0.0f17/m MR Msd Vsd - - EVX_MOVHPD F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f382a/m RM Vx Mx - - EVX_MOVNTDQA F=AVX512F TUPLE_FULL_MEM +EVEX.66.W0.0fe7/m MR Mx Vx - - EVX_MOVNTDQ F=AVX512F TUPLE_FULL_MEM +EVEX.NP.W0.0f2b/m MR Mps Vps - - EVX_MOVNTPS F=AVX512F TUPLE_FULL_MEM +EVEX.66.W1.0f2b/m MR Mpd Vpd - - EVX_MOVNTPD F=AVX512F TUPLE_FULL_MEM +EVEX.F3.W1.L0.0f7e RM Vq Wq - - EVX_MOVQ F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W1.L0.0fd6 MR Wq Vq - - EVX_MOVQ F=AVX512F TUPLE1_SCALAR_64 +EVEX.F3.W0.LIG.0f10/m RM Vdq Mss - - EVX_MOVSS+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.F3.W0.LIG.0f10/r RVM Vdq Hdq Uss - EVX_MOVSS+k F=AVX512F +EVEX.F2.W1.LIG.0f10/m RM Vdq Msd - - EVX_MOVSD+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.F2.W1.LIG.0f10/r RVM Vdq Hdq Usd - EVX_MOVSD+k F=AVX512F +EVEX.F3.W0.LIG.0f11/m MR Mss Vss - - EVX_MOVSS+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.F3.W0.LIG.0f11/r MVR Udq Hdq Vss - EVX_MOVSS+k F=AVX512F +EVEX.F2.W1.LIG.0f11/m MR Msd Vsd - - EVX_MOVSD+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.F2.W1.LIG.0f11/r MVR Udq Hdq Vsd - EVX_MOVSD+k F=AVX512F +EVEX.F3.W0.0f12 RM Vps Wps - - EVX_MOVSLDUP+k F=AVX512F TUPLE_FULL_MEM +EVEX.F3.W0.0f16 RM Vps Wps - - EVX_MOVSHDUP+k F=AVX512F TUPLE_FULL_MEM +EVEX.NP.W0.0f10 RM Vps Wps - - EVX_MOVUPS+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.W1.0f10 RM Vpd Wpd - - EVX_MOVUPD+k F=AVX512F TUPLE_FULL_MEM +EVEX.NP.W0.0f11 MR Wps Vps - - EVX_MOVUPS+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.W1.0f11 MR Wpd Vpd - - EVX_MOVUPD+k F=AVX512F TUPLE_FULL_MEM +EVEX.NP.W0.0f59 RVM Vps Hps Wps - EVX_MULPS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f59 RVM Vpd Hpd Wpd - EVX_MULPD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.LIG.0f59 RVM Vdq Hdq Wss - EVX_MULSS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.F2.W1.LIG.0f59 RVM Vdq Hdq Wsd - EVX_MULSD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.NP.W0.0f56 RVM Vps Hps Wps - EVX_ORPS+kb F=AVX512DQ TUPLE_FULL_32 +EVEX.66.W1.0f56 RVM Vpd Hpd Wpd - EVX_ORPD+kb F=AVX512DQ TUPLE_FULL_64 +EVEX.66.0f381c RM Vx Wx - - EVX_PABSB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f381d RM Vx Wx - - EVX_PABSW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f381e RM Vx Wx - - EVX_PABSD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f381f RM Vx Wx - - EVX_PABSQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0f63 RVM Vx Hx Wx - EVX_PACKSSWB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f67 RVM Vx Hx Wx - EVX_PACKUSWB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f6b RVM Vx Hx Wx - EVX_PACKSSDW+kb F=AVX512BW TUPLE_FULL_32 +EVEX.66.W0.0f382b RVM Vx Hx Wx - EVX_PACKUSDW+kb F=AVX512BW TUPLE_FULL_32 +EVEX.66.0ffc RVM Vx Hx Wx - EVX_PADDB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0ffd RVM Vx Hx Wx - EVX_PADDW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0ffe RVM Vx Hx Wx - EVX_PADDD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0fd4 RVM Vx Hx Wx - EVX_PADDQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0fec RVM Vx Hx Wx - EVX_PADDSB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fed RVM Vx Hx Wx - EVX_PADDSW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fdc RVM Vx Hx Wx - EVX_PADDUSB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fdd RVM Vx Hx Wx - EVX_PADDUSW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f3a0f RVMI Vx Hx Wx Ib EVX_PALIGNR+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0fdb RVM Vx Hx Wx - EVX_PANDD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0fdb RVM Vx Hx Wx - EVX_PANDQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0fdf RVM Vx Hx Wx - EVX_PANDND+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0fdf RVM Vx Hx Wx - EVX_PANDNQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0fe0 RVM Vx Hx Wx - EVX_PAVGB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fe3 RVM Vx Hx Wx - EVX_PAVGW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f3a44 RVMI Vx Hx Wx Ib EVX_PCLMULQDQ F=AVX512F,VPCLMULQDQ TUPLE_FULL_MEM +EVEX.66.0f74 RVM K Hx Wx - EVX_PCMPEQB+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.0f75 RVM K Hx Wx - EVX_PCMPEQW+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.W0.0f76 RVM K Hx Wx - EVX_PCMPEQD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3829 RVM K Hx Wx - EVX_PCMPEQQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0f64 RVM K Hx Wx - EVX_PCMPGTB+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.0f65 RVM K Hx Wx - EVX_PCMPGTW+k F=AVX512F TUPLE_FULL_MEM +EVEX.66.W0.0f66 RVM K Hx Wx - EVX_PCMPGTD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3837 RVM K Hx Wx - EVX_PCMPGTQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.L0.0f3a14/m MRI Mb Vdq Ib - EVX_PEXTRB F=AVX512BW TUPLE1_SCALAR_8 +EVEX.66.L0.0f3a14/r MRI Rd Vdq Ib - EVX_PEXTRB F=AVX512BW +EVEX.66.L0.0fc5/r RMI Gd Udq Ib - EVX_PEXTRW F=AVX512BW +EVEX.66.L0.0f3a15/m MRI Mw Vdq Ib - EVX_PEXTRW F=AVX512BW TUPLE1_SCALAR_16 +EVEX.66.L0.0f3a15/r MRI Rd Vdq Ib - EVX_PEXTRW F=AVX512BW +EVEX.66.L0.0f3a16 MRI Ey Vdq Ib - EVX_PEXTR F=AVX512DQ TUPLE1_SCALAR_OPSZ +EVEX.66.L0.0f3a20 RVMI Vdq Hdq Eb Ib EVX_PINSR F=AVX512BW TUPLE1_SCALAR_8 +EVEX.66.L0.0fc4 RVMI Vdq Hdq Ew Ib EVX_PINSR F=AVX512BW TUPLE1_SCALAR_16 +EVEX.66.L0.0f3a22 RVMI Vdq Hdq Ey Ib EVX_PINSR F=AVX512DQ TUPLE1_SCALAR_OPSZ +EVEX.66.0f3804 RVM Vx Hx Wx - EVX_PMADDUBSW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0ff5 RVM Vx Hx Wx - EVX_PMADDWD+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fda RVM Vx Hx Wx - EVX_PMINUB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fde RVM Vx Hx Wx - EVX_PMAXUB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fea RVM Vx Hx Wx - EVX_PMINSW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fee RVM Vx Hx Wx - EVX_PMAXSW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f3838 RVM Vx Hx Wx - EVX_PMINSB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f3839 RVM Vx Hx Wx - EVX_PMINSD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3839 RVM Vx Hx Wx - EVX_PMINSQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0f383a RVM Vx Hx Wx - EVX_PMINUW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f383b RVM Vx Hx Wx - EVX_PMINUD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f383b RVM Vx Hx Wx - EVX_PMINUQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0f383c RVM Vx Hx Wx - EVX_PMAXSB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f383d RVM Vx Hx Wx - EVX_PMAXSD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f383d RVM Vx Hx Wx - EVX_PMAXSQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0f383e RVM Vx Hx Wx - EVX_PMAXUW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f383f RVM Vx Hx Wx - EVX_PMAXUD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f383f RVM Vx Hx Wx - EVX_PMAXUQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0f3820 RM Vx Wh - - EVX_PMOVSXBW+k F=AVX512F TUPLE_HALF_MEM +EVEX.66.0f3821 RM Vx Wf - - EVX_PMOVSXBD+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.66.0f3822 RM Vx We - - EVX_PMOVSXBQ+k F=AVX512F TUPLE_EIGHTH_MEM +EVEX.66.0f3823 RM Vx Wh - - EVX_PMOVSXWD+k F=AVX512F TUPLE_HALF_MEM +EVEX.66.0f3824 RM Vx Wf - - EVX_PMOVSXWQ+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.66.W0.0f3825 RM Vx Wh - - EVX_PMOVSXDQ+k F=AVX512F TUPLE_HALF_MEM +EVEX.66.0f3830 RM Vx Wh - - EVX_PMOVZXBW+k F=AVX512F TUPLE_HALF_MEM +EVEX.66.0f3831 RM Vx Wf - - EVX_PMOVZXBD+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.66.0f3832 RM Vx We - - EVX_PMOVZXBQ+k F=AVX512F TUPLE_EIGHTH_MEM +EVEX.66.0f3833 RM Vx Wh - - EVX_PMOVZXWD+k F=AVX512F TUPLE_HALF_MEM +EVEX.66.0f3834 RM Vx Wf - - EVX_PMOVZXWQ+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.66.W0.0f3835 RM Vx Wh - - EVX_PMOVZXDQ+k F=AVX512F TUPLE_HALF_MEM +EVEX.66.W1.0f3828 RVM Vx Hx Wx - EVX_PMULDQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0f380b RVM Vx Hx Wx - EVX_PMULHRSW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fe4 RVM Vx Hx Wx - EVX_PMULHUW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fe5 RVM Vx Hx Wx - EVX_PMULHW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fd5 RVM Vx Hx Wx - EVX_PMULLW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f3840 RVM Vx Hx Wx - EVX_PMULLD+kb F=AVX512DQ TUPLE_FULL_32 +EVEX.66.W1.0f3840 RVM Vx Hx Wx - EVX_PMULLQ+kb F=AVX512DQ TUPLE_FULL_64 +EVEX.66.W1.0ff4 RVM Vx Hx Wx - EVX_PMULUDQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0feb RVM Vx Hx Wx - EVX_PORD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0feb RVM Vx Hx Wx - EVX_PORQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0ff6 RVM Vx Hx Wx - EVX_PSADBW F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f3800 RVM Vx Hx Wx - EVX_PSHUFB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f70 RMI Vx Wx Ib - EVX_PSHUFD+kb F=AVX512F TUPLE_FULL_32 +EVEX.F3.0f70 RMI Vx Wx Ib - EVX_PSHUFHW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.F2.0f70 RMI Vx Wx Ib - EVX_PSHUFLW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f71/2 VMI Hx Wx Ib - EVX_PSRLW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f71/4 VMI Hx Wx Ib - EVX_PSRAW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f71/6 VMI Hx Wx Ib - EVX_PSLLW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f72/2 VMI Hx Wx Ib - EVX_PSRLD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W0.0f72/4 VMI Hx Wx Ib - EVX_PSRAD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W0.0f72/6 VMI Hx Wx Ib - EVX_PSLLD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f73/2 VMI Hx Wx Ib - EVX_PSRLQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W1.0f72/4 VMI Hx Wx Ib - EVX_PSRAQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W1.0f73/6 VMI Hx Wx Ib - EVX_PSLLQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0fd1 RVM Vx Hx Wdq - EVX_PSRLW+k F=AVX512BW TUPLE_MEM128 +EVEX.66.W0.0fd2 RVM Vx Hx Wdq - EVX_PSRLD+k F=AVX512F TUPLE_MEM128 +EVEX.66.W1.0fd3 RVM Vx Hx Wdq - EVX_PSRLQ+k F=AVX512F TUPLE_MEM128 +EVEX.66.0fe1 RVM Vx Hx Wdq - EVX_PSRAW+k F=AVX512BW TUPLE_MEM128 +EVEX.66.W0.0fe2 RVM Vx Hx Wdq - EVX_PSRAD+k F=AVX512F TUPLE_MEM128 +EVEX.66.W1.0fe2 RVM Vx Hx Wdq - EVX_PSRAQ+k F=AVX512F TUPLE_MEM128 +EVEX.66.0ff1 RVM Vx Hx Wdq - EVX_PSLLW+k F=AVX512BW TUPLE_MEM128 +EVEX.66.W0.0ff2 RVM Vx Hx Wdq - EVX_PSLLD+k F=AVX512F TUPLE_MEM128 +EVEX.66.W1.0ff3 RVM Vx Hx Wdq - EVX_PSLLQ+k F=AVX512F TUPLE_MEM128 +EVEX.66.0f73/3 VMI Hx Wx Ib - EVX_PSRLDQ F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f73/7 VMI Hx Wx Ib - EVX_PSLLDQ F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0ff8 RVM Vx Hx Wx - EVX_PSUBB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0ff9 RVM Vx Hx Wx - EVX_PSUBW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0ffa RVM Vx Hx Wx - EVX_PSUBD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0ffb RVM Vx Hx Wx - EVX_PSUBQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0fe8 RVM Vx Hx Wx - EVX_PSUBSB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fe9 RVM Vx Hx Wx - EVX_PSUBSW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fd8 RVM Vx Hx Wx - EVX_PSUBUSB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0fd9 RVM Vx Hx Wx - EVX_PSUBUSW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f60 RVM Vx Hx Wx - EVX_PUNPCKLBW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f61 RVM Vx Hx Wx - EVX_PUNPCKLWD+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f62 RVM Vx Hx Wx - EVX_PUNPCKLDQ+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f6c RVM Vx Hx Wx - EVX_PUNPCKLQDQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.0f68 RVM Vx Hx Wx - EVX_PUNPCKHBW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.0f69 RVM Vx Hx Wx - EVX_PUNPCKHWD+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f6a RVM Vx Hx Wx - EVX_PUNPCKHDQ+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f6d RVM Vx Hx Wx - EVX_PUNPCKHQDQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0fef RVM Vx Hx Wx - EVX_PXORD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0fef RVM Vx Hx Wx - EVX_PXORQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.NP.W0.0fc6 RVMI Vx Hx Wx Ib EVX_SHUFPS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0fc6 RVMI Vx Hx Wx Ib EVX_SHUFPD+kb F=AVX512F TUPLE_FULL_64 +EVEX.NP.W0.0f51 RM Vps Wps - - EVX_SQRTPS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f51 RM Vpd Wpd - - EVX_SQRTPD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.LIG.0f51 RVM Vdq Hdq Wss - EVX_SQRTSS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.F2.W1.LIG.0f51 RVM Vdq Hdq Wsd - EVX_SQRTSD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.NP.W0.0f5c RVM Vps Hps Wps - EVX_SUBPS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f5c RVM Vpd Hpd Wpd - EVX_SUBPD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.LIG.0f5c RVM Vdq Hdq Wss - EVX_SUBSS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.F2.W1.LIG.0f5c RVM Vdq Hdq Wsd - EVX_SUBSD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.NP.W0.LIG.0f2e RM Vss Wss - - EVX_UCOMISS+e F=AVX512F TUPLE1_SCALAR_32 EFL=0--0m0mm +EVEX.66.W1.LIG.0f2e RM Vsd Wsd - - EVX_UCOMISD+e F=AVX512F TUPLE1_SCALAR_64 EFL=0--0m0mm +EVEX.NP.W0.0f14 RVM Vps Hps Wps - EVX_UNPCKLPS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f14 RVM Vpd Hpd Wpd - EVX_UNPCKLPD+kb F=AVX512F TUPLE_FULL_64 +EVEX.NP.W0.0f15 RVM Vps Hps Wps - EVX_UNPCKHPS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f15 RVM Vpd Hpd Wpd - EVX_UNPCKHPD+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3a03 RVMI Vx Hx Wx Ib EVX_ALIGND+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3a03 RVMI Vx Hx Wx Ib EVX_ALIGNQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3865 RVM Vx Hx Wx - EVX_BLENDMPS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3865 RVM Vx Hx Wx - EVX_BLENDMPD+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3818 RM Vx Wd - - EVX_BROADCASTSS+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W0.L12.0f3819 RM Vx Wq - - EVX_BROADCASTF32X2+k F=AVX512DQ TUPLE2_32 +EVEX.66.W1.L12.0f3819 RM Vx Wq - - EVX_BROADCASTSD+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.L12.0f381a/m RM Vx Mdq - - EVX_BROADCASTF32X4+k F=AVX512F TUPLE4_32 +EVEX.66.W1.L12.0f381a/m RM Vx Mdq - - EVX_BROADCASTF64X2+k F=AVX512DQ TUPLE2_64 +EVEX.66.W0.L2.0f381b/m RM Vx Mqq - - EVX_BROADCASTF32X8+k F=AVX512DQ TUPLE8_32 +EVEX.66.W1.L2.0f381b/m RM Vx Mqq - - EVX_BROADCASTF64X4+k F=AVX512F TUPLE4_64 +# Note tuple type, scale is not memory size but element size +EVEX.66.W0.0f388a/m MR Md Vx - - EVX_COMPRESSPS+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W0.0f388a/r MR Ux Vx - - EVX_COMPRESSPS+k F=AVX512F +EVEX.66.W1.0f388a/m MR Mq Vx - - EVX_COMPRESSPD+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W1.0f388a/r MR Ux Vx - - EVX_COMPRESSPD+k F=AVX512F +EVEX.F2.W0.0f3872 RVM Vx Hx Wx - EVX_CVTNE2PS2BF16+kb F=AVX512_BF16 TUPLE_FULL_32 +EVEX.F3.W0.0f3872 RM Vh Wx - - EVX_CVTNEPS2BF16+kb F=AVX512_BF16 TUPLE_FULL_32 +EVEX.66.W0.0f7b RM Vx Wh - - EVX_CVTPS2QQ+kbr F=AVX512DQ TUPLE_HALF_32 +EVEX.66.W1.0f7b RM Vx Wx - - EVX_CVTPD2QQ+kbr F=AVX512DQ TUPLE_FULL_64 +EVEX.NP.W0.0f79 RM Vx Wx - - EVX_CVTPS2UDQ+kbr F=AVX512F TUPLE_FULL_32 +EVEX.NP.W1.0f79 RM Vh Wx - - EVX_CVTPD2UDQ+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f79 RM Vx Wh - - EVX_CVTPS2UQQ+kbr F=AVX512F TUPLE_HALF_32 +EVEX.66.W1.0f79 RM Vx Wx - - EVX_CVTPD2UQQ+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3813 RM Vx Wh - - EVX_CVTPH2PS+ke F=AVX512F TUPLE_HALF_MEM +EVEX.66.W0.0f3a1d MRI Wh Vx Ib - EVX_CVTPS2PH+ke F=AVX512F TUPLE_HALF_MEM +EVEX.F3.W1.0fe6 RM Vx Wx - - EVX_CVTQQ2PD+kbr F=AVX512DQ TUPLE_FULL_64 +EVEX.NP.W1.0f5b RM Vh Wx - - EVX_CVTQQ2PS+kbr F=AVX512DQ TUPLE_FULL_64 +EVEX.F2.LIG.0f79 RM Gy Wsd - - EVX_CVTSD2USI+r F=AVX512F TUPLE1_FIXED_64 +EVEX.F3.LIG.0f79 RM Gy Wss - - EVX_CVTSS2USI+r F=AVX512F TUPLE1_FIXED_32 +# Note: for W0, ER is ignored (i.e., will not UD, according to Intel SDM) +EVEX.F2.LIG.0f7b RVM Vdq Hdq Ey - EVX_CVTUSI2SD+r F=AVX512F TUPLE1_SCALAR_OPSZ +EVEX.F3.LIG.0f7b RVM Vdq Hdq Ey - EVX_CVTUSI2SS+r F=AVX512F TUPLE1_SCALAR_OPSZ +EVEX.66.W0.0f7a RM Vx Wh - - EVX_CVTTPS2QQ+kbe F=AVX512DQ TUPLE_HALF_32 +EVEX.66.W1.0f7a RM Vx Wx - - EVX_CVTTPD2QQ+kbe F=AVX512DQ TUPLE_FULL_64 +EVEX.NP.W0.0f78 RM Vx Wx - - EVX_CVTTPS2UDQ+kbe F=AVX512F TUPLE_FULL_32 +EVEX.NP.W1.0f78 RM Vh Wx - - EVX_CVTTPD2UDQ+kbe F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f78 RM Vx Wh - - EVX_CVTTPS2UQQ+kbe F=AVX512F TUPLE_HALF_32 +EVEX.66.W1.0f78 RM Vx Wx - - EVX_CVTTPD2UQQ+kbe F=AVX512F TUPLE_FULL_64 +EVEX.F2.LIG.0f78 RM Gy Wsd - - EVX_CVTTSD2USI+e F=AVX512F TUPLE1_FIXED_64 +EVEX.F3.LIG.0f78 RM Gy Wss - - EVX_CVTTSS2USI+e F=AVX512F TUPLE1_FIXED_32 +# Note: SAE is ignored. +EVEX.F3.W0.0f7a RM Vx Wh - - EVX_CVTUDQ2PD+kbe F=AVX512F TUPLE_HALF_32 +EVEX.F2.W0.0f7a RM Vx Wx - - EVX_CVTUDQ2PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.F3.W1.0f7a RM Vx Wx - - EVX_CVTUQQ2PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.F2.W1.0f7a RM Vh Wx - - EVX_CVTUQQ2PS+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3a42 RVMI Vx Hx Wx Ib EVX_DBPSADBW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.F3.W0.0f3852 RVM Vx Hx Wx - EVX_DPBF16PS+kb F=AVX512_BF16 TUPLE_FULL_32 +# Note tuple type, scale is not memory size but element size +EVEX.66.W0.0f3888/m RM Vx Md - - EVX_EXPANDPS+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W0.0f3888/r RM Vx Ux - - EVX_EXPANDPS+k F=AVX512F +EVEX.66.W1.0f3888/m RM Vx Mq - - EVX_EXPANDPD+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W1.0f3888/r RM Vx Ux - - EVX_EXPANDPD+k F=AVX512F +EVEX.66.W0.L12.0f3a19 MRI Wdq Vx Ib - EVX_EXTRACTF32X4+k F=AVX512F TUPLE4_32 +EVEX.66.W1.L12.0f3a19 MRI Wdq Vx Ib - EVX_EXTRACTF64X2+k F=AVX512F TUPLE2_64 +EVEX.66.W0.L2.0f3a1b MRI Wqq Vx Ib - EVX_EXTRACTF32X8+k F=AVX512F TUPLE8_32 +EVEX.66.W1.L2.0f3a1b MRI Wqq Vx Ib - EVX_EXTRACTF64X4+k F=AVX512F TUPLE4_64 +EVEX.66.W0.L12.0f3a39 MRI Wdq Vx Ib - EVX_EXTRACTI32X4+k F=AVX512F TUPLE4_32 +EVEX.66.W1.L12.0f3a39 MRI Wdq Vx Ib - EVX_EXTRACTI64X2+k F=AVX512F TUPLE2_64 +EVEX.66.W0.L2.0f3a3b MRI Wqq Vx Ib - EVX_EXTRACTI32X8+k F=AVX512F TUPLE8_32 +EVEX.66.W1.L2.0f3a3b MRI Wqq Vx Ib - EVX_EXTRACTI64X4+k F=AVX512F TUPLE4_64 +EVEX.66.W0.0f3a54 RVMI Vps Hps Wps Ib EVX_FIXUPIMMPS+kbe F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3a54 RVMI Vpd Hpd Wpd Ib EVX_FIXUPIMMPD+kbe F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f3a55 RVMI Vdq Hdq Wss Ib EVX_FIXUPIMMSS+ke F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f3a55 RVMI Vdq Hdq Wsd Ib EVX_FIXUPIMMSD+ke F=AVX512F TUPLE1_SCALAR_64 +# TODO: verify these, this is just copied from AVX/FMA. +EVEX.66.W0.0f3896 RVM Vx Hx Wx - EVX_FMADDSUB132PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3896 RVM Vx Hx Wx - EVX_FMADDSUB132PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3897 RVM Vx Hx Wx - EVX_FMSUBADD132PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3897 RVM Vx Hx Wx - EVX_FMSUBADD132PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3898 RVM Vx Hx Wx - EVX_FMADD132PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3898 RVM Vx Hx Wx - EVX_FMADD132PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f3899 RVM Vdq Hdq Wss - EVX_FMADD132SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f3899 RVM Vdq Hdq Wsd - EVX_FMADD132SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f389a RVM Vx Hx Wx - EVX_FMSUB132PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f389a RVM Vx Hx Wx - EVX_FMSUB132PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f389b RVM Vdq Hdq Wss - EVX_FMSUB132SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f389b RVM Vdq Hdq Wsd - EVX_FMSUB132SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f389c RVM Vx Hx Wx - EVX_FNMADD132PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f389c RVM Vx Hx Wx - EVX_FNMADD132PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f389d RVM Vdq Hdq Wss - EVX_FNMADD132SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f389d RVM Vdq Hdq Wsd - EVX_FNMADD132SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f389e RVM Vx Hx Wx - EVX_FNMSUB132PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f389e RVM Vx Hx Wx - EVX_FNMSUB132PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f389f RVM Vdq Hdq Wss - EVX_FNMSUB132SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f389f RVM Vdq Hdq Wsd - EVX_FNMSUB132SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f38a6 RVM Vx Hx Wx - EVX_FMADDSUB213PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38a6 RVM Vx Hx Wx - EVX_FMADDSUB213PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f38a7 RVM Vx Hx Wx - EVX_FMSUBADD213PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38a7 RVM Vx Hx Wx - EVX_FMSUBADD213PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f38a8 RVM Vx Hx Wx - EVX_FMADD213PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38a8 RVM Vx Hx Wx - EVX_FMADD213PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f38a9 RVM Vdq Hdq Wss - EVX_FMADD213SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f38a9 RVM Vdq Hdq Wsd - EVX_FMADD213SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f38aa RVM Vx Hx Wx - EVX_FMSUB213PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38aa RVM Vx Hx Wx - EVX_FMSUB213PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f38ab RVM Vdq Hdq Wss - EVX_FMSUB213SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f38ab RVM Vdq Hdq Wsd - EVX_FMSUB213SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f38ac RVM Vx Hx Wx - EVX_FNMADD213PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38ac RVM Vx Hx Wx - EVX_FNMADD213PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f38ad RVM Vdq Hdq Wss - EVX_FNMADD213SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f38ad RVM Vdq Hdq Wsd - EVX_FNMADD213SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f38ae RVM Vx Hx Wx - EVX_FNMSUB213PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38ae RVM Vx Hx Wx - EVX_FNMSUB213PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f38af RVM Vdq Hdq Wss - EVX_FNMSUB213SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f38af RVM Vdq Hdq Wsd - EVX_FNMSUB213SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f38b6 RVM Vx Hx Wx - EVX_FMADDSUB231PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38b6 RVM Vx Hx Wx - EVX_FMADDSUB231PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f38b7 RVM Vx Hx Wx - EVX_FMSUBADD231PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38b7 RVM Vx Hx Wx - EVX_FMSUBADD231PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f38b8 RVM Vx Hx Wx - EVX_FMADD231PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38b8 RVM Vx Hx Wx - EVX_FMADD231PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f38b9 RVM Vdq Hdq Wss - EVX_FMADD231SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f38b9 RVM Vdq Hdq Wsd - EVX_FMADD231SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f38ba RVM Vx Hx Wx - EVX_FMSUB231PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38ba RVM Vx Hx Wx - EVX_FMSUB231PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f38bb RVM Vdq Hdq Wss - EVX_FMSUB231SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f38bb RVM Vdq Hdq Wsd - EVX_FMSUB231SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f38bc RVM Vx Hx Wx - EVX_FNMADD231PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38bc RVM Vx Hx Wx - EVX_FNMADD231PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f38bd RVM Vdq Hdq Wss - EVX_FNMADD231SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f38bd RVM Vdq Hdq Wsd - EVX_FNMADD231SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f38be RVM Vx Hx Wx - EVX_FNMSUB231PS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f38be RVM Vx Hx Wx - EVX_FNMSUB231PD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f38bf RVM Vdq Hdq Wss - EVX_FNMSUB231SS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f38bf RVM Vdq Hdq Wsd - EVX_FNMSUB231SD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f3a66 RMI Kb Wps Ib - EVX_FPCLASSPS+kb F=AVX512DQ TUPLE_FULL_32 +EVEX.66.W1.0f3a66 RMI Kb Wpd Ib - EVX_FPCLASSPD+kb F=AVX512DQ TUPLE_FULL_64 +EVEX.66.W0.LIG.0f3a67 RMI Kb Wss Ib - EVX_FPCLASSSS+k F=AVX512DQ TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f3a67 RMI Kb Wsd Ib - EVX_FPCLASSSD+k F=AVX512DQ TUPLE1_SCALAR_64 +EVEX.66.W0.0f3892/m RM Vx Md - - EVX_GATHERDPS+k F=AVX512F VSIB TUPLE1_SCALAR_32 +EVEX.66.W1.0f3892/m RM Vx Mq - - EVX_GATHERDPD+k F=AVX512F VSIB TUPLE1_SCALAR_64 +EVEX.66.W0.0f3893/m RM Vh Md - - EVX_GATHERQPS+k F=AVX512F VSIB TUPLE1_SCALAR_32 +EVEX.66.W1.0f3893/m RM Vx Mq - - EVX_GATHERQPD+k F=AVX512F VSIB TUPLE1_SCALAR_64 +EVEX.66.W0.0f3842 RM Vps Wps - - EVX_GETEXPPS+kbe F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3842 RM Vpd Wpd - - EVX_GETEXPPD+kbe F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f3843 RVM Vdq Hdq Wss - EVX_GETEXPSS+ke F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f3843 RVM Vdq Hdq Wsd - EVX_GETEXPSD+ke F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f3a26 RMI Vps Wps Ib - EVX_GETMANTPS+kbe F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3a26 RMI Vpd Wpd Ib - EVX_GETMANTPD+kbe F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f3a27 RVMI Vdq Hdq Wss Ib EVX_GETMANTSS+ke F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f3a27 RVMI Vdq Hdq Wsd Ib EVX_GETMANTSD+ke F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.L12.0f3a18 RVMI Vx Hx Wdq Ib EVX_INSERTF32X4+k F=AVX512F TUPLE4_32 +EVEX.66.W1.L12.0f3a18 RVMI Vx Hx Wdq Ib EVX_INSERTF64X2+k F=AVX512DQ TUPLE2_64 +EVEX.66.W0.L2.0f3a1a RVMI Vx Hx Wqq Ib EVX_INSERTF32X8+k F=AVX512DQ TUPLE8_32 +EVEX.66.W1.L2.0f3a1a RVMI Vx Hx Wqq Ib EVX_INSERTF64X4+k F=AVX512F TUPLE4_64 +EVEX.66.W0.L12.0f3a38 RVMI Vx Hx Wdq Ib EVX_INSERTI32X4+k F=AVX512F TUPLE4_32 +EVEX.66.W1.L12.0f3a38 RVMI Vx Hx Wdq Ib EVX_INSERTI64X2+k F=AVX512DQ TUPLE2_64 +EVEX.66.W0.L2.0f3a3a RVMI Vx Hx Wqq Ib EVX_INSERTI32X8+k F=AVX512DQ TUPLE8_32 +EVEX.66.W1.L2.0f3a3a RVMI Vx Hx Wqq Ib EVX_INSERTI64X4+k F=AVX512F TUPLE4_64 +EVEX.F2.W0.0f3868 RVM K Hx Wx - EVX_P2INTERSECTD+b F=AVX512_VP2INTERSECT TUPLE_FULL_32 +EVEX.F2.W1.0f3868 RVM K Hx Wx - EVX_P2INTERSECTQ+b F=AVX512_VP2INTERSECT TUPLE_FULL_64 +EVEX.66.W0.0f3866 RVM Vx Hx Wx - EVX_PBLENDMB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W1.0f3866 RVM Vx Hx Wx - EVX_PBLENDMW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f3864 RVM Vx Hx Wx - EVX_PBLENDMD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3864 RVM Vx Hx Wx - EVX_PBLENDMQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f387a/r RM Vx Rb - - EVX_PBROADCAST+k F=AVX512BW +EVEX.66.W0.0f387b/r RM Vx Rw - - EVX_PBROADCAST+k F=AVX512BW +EVEX.66.W0.0f387c/r RM Vx Rd - - EVX_PBROADCAST+k F=AVX512F +EVEX.66.W1.0f387c/r RM Vx Rd - - EVX_PBROADCAST+k I64 F=AVX512F +EVEX.66.W1.0f387c/r RM Vx Rq - - EVX_PBROADCAST+k O64 F=AVX512F +EVEX.66.W0.0f3878 RM Vx Wb - - EVX_PBROADCASTB+k F=AVX512BW TUPLE1_SCALAR_8 +EVEX.66.W0.0f3879 RM Vx Ww - - EVX_PBROADCASTW+k F=AVX512BW TUPLE1_SCALAR_16 +EVEX.66.W0.0f3858 RM Vx Wd - - EVX_PBROADCASTD+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.0f3859 RM Vx Wq - - EVX_PBROADCASTQ+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f3859 RM Vx Wq - - EVX_BROADCASTI32X2+k F=AVX512DQ TUPLE2_32 +EVEX.66.W0.L12.0f385a/m RM Vx Mdq - - EVX_BROADCASTI32X4+k F=AVX512DQ TUPLE4_32 +EVEX.66.W1.L12.0f385a/m RM Vx Mdq - - EVX_BROADCASTI64X2+k F=AVX512DQ TUPLE2_64 +EVEX.66.W0.L2.0f385b/m RM Vx Mqq - - EVX_BROADCASTI32X8+k F=AVX512DQ TUPLE8_32 +EVEX.66.W1.L2.0f385b/m RM Vx Mqq - - EVX_BROADCASTI64X4+k F=AVX512F TUPLE4_64 +EVEX.F3.W1.0f382a/r RM Vx K - - EVX_PBROADCASTMB2Q F=AVX512CD +EVEX.F3.W0.0f383a/r RM Vx K - - EVX_PBROADCASTMW2D F=AVX512CD +EVEX.66.W0.0f3a1e RVMI K Hx Wx Ib EVX_PCMPUD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W0.0f3a1f RVMI K Hx Wx Ib EVX_PCMPD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3a1e RVMI K Hx Wx Ib EVX_PCMPUQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W1.0f3a1f RVMI K Hx Wx Ib EVX_PCMPQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3a3e RVMI K Hx Wx Ib EVX_PCMPUB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f3a3f RVMI K Hx Wx Ib EVX_PCMPB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W1.0f3a3e RVMI K Hx Wx Ib EVX_PCMPUW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W1.0f3a3f RVMI K Hx Wx Ib EVX_PCMPW+k F=AVX512BW TUPLE_FULL_MEM +# Note tuple type, scale is not memory size but element size +EVEX.66.W0.0f3863/m MR Mb Vx - - EVX_PCOMPRESSB+k F=AVX512_VBMI2 TUPLE1_SCALAR_8 +EVEX.66.W0.0f3863/r MR Ux Vx - - EVX_PCOMPRESSB+k F=AVX512_VBMI2 +EVEX.66.W1.0f3863/m MR Mw Vx - - EVX_PCOMPRESSW+k F=AVX512_VBMI2 TUPLE1_SCALAR_16 +EVEX.66.W1.0f3863/r MR Ux Vx - - EVX_PCOMPRESSW+k F=AVX512_VBMI2 +EVEX.66.W0.0f388b/m MR Md Vx - - EVX_PCOMPRESSD+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W0.0f388b/r MR Ux Vx - - EVX_PCOMPRESSD+k F=AVX512F +EVEX.66.W1.0f388b/m MR Mq Vx - - EVX_PCOMPRESSQ+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W1.0f388b/r MR Ux Vx - - EVX_PCOMPRESSQ+k F=AVX512F +EVEX.66.W0.0f38c4 RM Vx Wx - - EVX_PCONFLICTD+kb F=AVX512CD TUPLE_FULL_32 +EVEX.66.W1.0f38c4 RM Vx Wx - - EVX_PCONFLICTQ+kb F=AVX512CD TUPLE_FULL_64 +EVEX.66.W0.0f3850 RVM Vx Hx Wx - EVX_PDPBUSD+kb F=AVX512_VNNI TUPLE_FULL_32 +EVEX.66.W0.0f3851 RVM Vx Hx Wx - EVX_PDPBUSDS+kb F=AVX512_VNNI TUPLE_FULL_32 +EVEX.66.W0.0f3852 RVM Vx Hx Wx - EVX_PDPWSSD+kb F=AVX512_VNNI TUPLE_FULL_32 +EVEX.66.W0.0f3853 RVM Vx Hx Wx - EVX_PDPWSSDS+kb F=AVX512_VNNI TUPLE_FULL_32 +EVEX.66.W0.0f388d RVM Vx Hx Wx - EVX_PERMB+k F=AVX512_VBMI TUPLE_FULL_MEM +EVEX.66.W1.0f388d RVM Vx Hx Wx - EVX_PERMW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.L12.0f3836 RVM Vx Hx Wx - EVX_PERMD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W0.0f3875 RVM Vx Hx Wx - EVX_PERMI2B+k F=AVX512_VBMI TUPLE_FULL_MEM +EVEX.66.W1.0f3875 RVM Vx Hx Wx - EVX_PERMI2W+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f3876 RVM Vx Hx Wx - EVX_PERMI2D+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3876 RVM Vx Hx Wx - EVX_PERMI2Q+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3877 RVM Vx Hx Wx - EVX_PERMI2PS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3877 RVM Vx Hx Wx - EVX_PERMI2PD+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f380c RVM Vx Hx Wx - EVX_PERMILPS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f380d RVM Vx Hx Wx - EVX_PERMILPD+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3a04 RMI Vx Wx Ib - EVX_PERMILPS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3a05 RMI Vx Wx Ib - EVX_PERMILPD+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.L12.0f3816 RVM Vx Hx Wx - EVX_PERMPS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.L12.0f3816 RVM Vx Hx Wx - EVX_PERMPD+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W1.L12.0f3836 RVM Vx Hx Wx - EVX_PERMQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W1.L12.0f3a00 RMI Vx Wx Ib - EVX_PERMQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W1.L12.0f3a01 RMI Vx Wx Ib - EVX_PERMPD+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f387d RVM Vx Hx Wx - EVX_PERMT2B+k F=AVX512_VBMI TUPLE_FULL_MEM +EVEX.66.W1.0f387d RVM Vx Hx Wx - EVX_PERMT2W+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f387e RVM Vx Hx Wx - EVX_PERMT2D+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f387e RVM Vx Hx Wx - EVX_PERMT2Q+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f387f RVM Vx Hx Wx - EVX_PERMT2PS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f387f RVM Vx Hx Wx - EVX_PERMT2PD+kb F=AVX512F TUPLE_FULL_64 +# Note tuple type, scale is not memory size but element size +EVEX.66.W0.0f3862/m RM Vx Mb - - EVX_PEXPANDB+k F=AVX512_VBMI2 TUPLE1_SCALAR_8 +EVEX.66.W0.0f3862/r RM Vx Ux - - EVX_PEXPANDB+k F=AVX512_VBMI2 +EVEX.66.W1.0f3862/m RM Vx Mw - - EVX_PEXPANDW+k F=AVX512_VBMI2 TUPLE1_SCALAR_16 +EVEX.66.W1.0f3862/r RM Vx Ux - - EVX_PEXPANDW+k F=AVX512_VBMI2 +EVEX.66.W0.0f3889/m RM Vx Md - - EVX_PEXPANDD+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W0.0f3889/r RM Vx Ux - - EVX_PEXPANDD+k F=AVX512F +EVEX.66.W1.0f3889/m RM Vx Mq - - EVX_PEXPANDQ+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W1.0f3889/r RM Vx Ux - - EVX_PEXPANDQ+k F=AVX512F +EVEX.66.W0.0f3890/m RM Vx Md - - EVX_PGATHERDD+k F=AVX512F VSIB TUPLE1_SCALAR_32 +EVEX.66.W1.0f3890/m RM Vx Mq - - EVX_PGATHERDQ+k F=AVX512F VSIB TUPLE1_SCALAR_64 +EVEX.66.W0.0f3891/m RM Vh Md - - EVX_PGATHERQD+k F=AVX512F VSIB TUPLE1_SCALAR_32 +EVEX.66.W1.0f3891/m RM Vx Mq - - EVX_PGATHERQQ+k F=AVX512F VSIB TUPLE1_SCALAR_64 +EVEX.66.W0.0f3844 RM Vx Wx - - EVX_PLZCNTD+kb F=AVX512CD TUPLE_FULL_32 +EVEX.66.W1.0f3844 RM Vx Wx - - EVX_PLZCNTQ+kb F=AVX512CD TUPLE_FULL_64 +EVEX.66.W1.0f38b4 RVM Vx Hx Wx - EVX_PMADD52LUQ+kb F=AVX512_IFMA TUPLE_FULL_64 +EVEX.66.W1.0f38b5 RVM Vx Hx Wx - EVX_PMADD52HUQ+kb F=AVX512_IFMA TUPLE_FULL_64 +EVEX.F3.W0.0f3829/r RM K Ux - - EVX_PMOVB2M F=AVX512BW +EVEX.F3.W1.0f3829/r RM K Ux - - EVX_PMOVW2M F=AVX512BW +EVEX.F3.W0.0f3839/r RM K Ux - - EVX_PMOVD2M F=AVX512DQ +EVEX.F3.W1.0f3839/r RM K Ux - - EVX_PMOVQ2M F=AVX512DQ +EVEX.F3.W0.0f3828/r RM Vx K - - EVX_PMOVM2B F=AVX512BW +EVEX.F3.W1.0f3828/r RM Vx K - - EVX_PMOVM2W F=AVX512BW +EVEX.F3.W0.0f3838/r RM Vx K - - EVX_PMOVM2D F=AVX512DQ +EVEX.F3.W1.0f3838/r RM Vx K - - EVX_PMOVM2Q F=AVX512DQ +EVEX.F3.W0.0f3830 MR Wh Vx - - EVX_PMOVWB+k F=AVX512BW TUPLE_HALF_MEM +EVEX.F3.W0.0f3820 MR Wh Vx - - EVX_PMOVSWB+k F=AVX512BW TUPLE_HALF_MEM +EVEX.F3.W0.0f3810 MR Wh Vx - - EVX_PMOVUSWB+k F=AVX512BW TUPLE_HALF_MEM +EVEX.F3.W0.0f3831 MR Wf Vx - - EVX_PMOVDB+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.F3.W0.0f3821 MR Wf Vx - - EVX_PMOVSDB+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.F3.W0.0f3811 MR Wf Vx - - EVX_PMOVUSDB+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.F3.W0.0f3832 MR We Vx - - EVX_PMOVQB+k F=AVX512F TUPLE_EIGHTH_MEM +EVEX.F3.W0.0f3822 MR We Vx - - EVX_PMOVSQB+k F=AVX512F TUPLE_EIGHTH_MEM +EVEX.F3.W0.0f3812 MR We Vx - - EVX_PMOVUSQB+k F=AVX512F TUPLE_EIGHTH_MEM +EVEX.F3.W0.0f3833 MR Wh Vx - - EVX_PMOVDW+k F=AVX512F TUPLE_HALF_MEM +EVEX.F3.W0.0f3823 MR Wh Vx - - EVX_PMOVSDW+k F=AVX512F TUPLE_HALF_MEM +EVEX.F3.W0.0f3813 MR Wh Vx - - EVX_PMOVUSDW+k F=AVX512F TUPLE_HALF_MEM +EVEX.F3.W0.0f3834 MR Wf Vx - - EVX_PMOVQW+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.F3.W0.0f3824 MR Wf Vx - - EVX_PMOVSQW+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.F3.W0.0f3814 MR Wf Vx - - EVX_PMOVUSQW+k F=AVX512F TUPLE_QUARTER_MEM +EVEX.F3.W0.0f3835 MR Wh Vx - - EVX_PMOVQD+k F=AVX512F TUPLE_HALF_MEM +EVEX.F3.W0.0f3825 MR Wh Vx - - EVX_PMOVSQD+k F=AVX512F TUPLE_HALF_MEM +EVEX.F3.W0.0f3815 MR Wh Vx - - EVX_PMOVUSQD+k F=AVX512F TUPLE_HALF_MEM +EVEX.66.W1.0f3883 RVM Vx Hx Wx - EVX_PMULTISHIFTQB+kb F=AVX512_VBMI TUPLE_FULL_64 +EVEX.66.W0.0f3854 RM Vx Wx - - EVX_POPCNTB+k F=AVX512_BITALG TUPLE_FULL_MEM +EVEX.66.W1.0f3854 RM Vx Wx - - EVX_POPCNTW+k F=AVX512_BITALG TUPLE_FULL_MEM +EVEX.66.W0.0f3855 RM Vx Wx - - EVX_POPCNTD+kb F=AVX512_VPOPCNTDQ TUPLE_FULL_32 +EVEX.66.W1.0f3855 RM Vx Wx - - EVX_POPCNTQ+kb F=AVX512_VPOPCNTDQ TUPLE_FULL_64 +EVEX.66.W0.0f3814 RVM Vx Hx Wx - EVX_PRORVD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3814 RVM Vx Hx Wx - EVX_PRORVQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f72/0 VMI Hx Wx Ib - EVX_PRORD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f72/0 VMI Hx Wx Ib - EVX_PRORQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3815 RVM Vx Hx Wx - EVX_PROLVD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3815 RVM Vx Hx Wx - EVX_PROLVQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f72/1 VMI Hx Wx Ib - EVX_PROLD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f72/1 VMI Hx Wx Ib - EVX_PROLQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f38a0/m MR Md Vx - - EVX_PSCATTERDD+k F=AVX512F VSIB TUPLE1_SCALAR_32 +EVEX.66.W1.0f38a0/m MR Mq Vx - - EVX_PSCATTERDQ+k F=AVX512F VSIB TUPLE1_SCALAR_64 +EVEX.66.W0.0f38a1/m MR Md Vh - - EVX_PSCATTERQD+k F=AVX512F VSIB TUPLE1_SCALAR_32 +EVEX.66.W1.0f38a1/m MR Mq Vx - - EVX_PSCATTERQQ+k F=AVX512F VSIB TUPLE1_SCALAR_64 +EVEX.66.W1.0f3a70 RVMI Vx Hx Wx Ib EVX_PSHLDW+k F=AVX512_VBMI2 TUPLE_FULL_MEM +EVEX.66.W0.0f3a71 RVMI Vx Hx Wx Ib EVX_PSHLDD+kb F=AVX512_VBMI2 TUPLE_FULL_32 +EVEX.66.W1.0f3a71 RVMI Vx Hx Wx Ib EVX_PSHLDQ+kb F=AVX512_VBMI2 TUPLE_FULL_64 +EVEX.66.W1.0f3870 RVM Vx Hx Wx - EVX_PSHLDVW+k F=AVX512_VBMI2 TUPLE_FULL_MEM +EVEX.66.W0.0f3871 RVM Vx Hx Wx - EVX_PSHLDVD+kb F=AVX512_VBMI2 TUPLE_FULL_32 +EVEX.66.W1.0f3871 RVM Vx Hx Wx - EVX_PSHLDVQ+kb F=AVX512_VBMI2 TUPLE_FULL_64 +EVEX.66.W1.0f3a72 RVMI Vx Hx Wx Ib EVX_PSHRDW+k F=AVX512_VBMI2 TUPLE_FULL_MEM +EVEX.66.W0.0f3a73 RVMI Vx Hx Wx Ib EVX_PSHRDD+kb F=AVX512_VBMI2 TUPLE_FULL_32 +EVEX.66.W1.0f3a73 RVMI Vx Hx Wx Ib EVX_PSHRDQ+kb F=AVX512_VBMI2 TUPLE_FULL_64 +EVEX.66.W1.0f3872 RVM Vx Hx Wx - EVX_PSHRDVW+k F=AVX512_VBMI2 TUPLE_FULL_MEM +EVEX.66.W0.0f3873 RVM Vx Hx Wx - EVX_PSHRDVD+kb F=AVX512_VBMI2 TUPLE_FULL_32 +EVEX.66.W1.0f3873 RVM Vx Hx Wx - EVX_PSHRDVQ+kb F=AVX512_VBMI2 TUPLE_FULL_64 +EVEX.66.W0.0f388f RVM K Hx Wx - EVX_PSHUFBITQMB+k F=AVX512_BITALG TUPLE_FULL_MEM +EVEX.66.W1.0f3812 RVM Vx Hx Wx - EVX_PSLLVW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f3847 RVM Vx Hx Wx - EVX_PSLLVD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3847 RVM Vx Hx Wx - EVX_PSLLVQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W1.0f3811 RVM Vx Hx Wx - EVX_PSRAVW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f3846 RVM Vx Hx Wx - EVX_PSRAVD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3846 RVM Vx Hx Wx - EVX_PSRAVQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W1.0f3810 RVM Vx Hx Wx - EVX_PSRLVW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f3845 RVM Vx Hx Wx - EVX_PSRLVD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3845 RVM Vx Hx Wx - EVX_PSRLVQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3a25 RVMI Vx Hx Wx Ib EVX_PTERNLOGD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3a25 RVMI Vx Hx Wx Ib EVX_PTERNLOGQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3826 RVM K Hx Wx - EVX_PTESTMB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W1.0f3826 RVM K Hx Wx - EVX_PTESTMW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.66.W0.0f3827 RVM K Hx Wx - EVX_PTESTMD+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3827 RVM K Hx Wx - EVX_PTESTMQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.F3.W0.0f3826 RVM K Hx Wx - EVX_PTESTNMB+k F=AVX512BW TUPLE_FULL_MEM +EVEX.F3.W1.0f3826 RVM K Hx Wx - EVX_PTESTNMW+k F=AVX512BW TUPLE_FULL_MEM +EVEX.F3.W0.0f3827 RVM K Hx Wx - EVX_PTESTNMD+kb F=AVX512F TUPLE_FULL_32 +EVEX.F3.W1.0f3827 RVM K Hx Wx - EVX_PTESTNMQ+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.0f3a50 RVMI Vps Hps Wps Ib EVX_RANGEPS+kbe F=AVX512DQ TUPLE_FULL_32 +EVEX.66.W1.0f3a50 RVMI Vpd Hpd Wpd Ib EVX_RANGEPD+kbe F=AVX512DQ TUPLE_FULL_64 +EVEX.66.W0.LIG.0f3a51 RVMI Vdq Hdq Wss Ib EVX_RANGESS+ke F=AVX512DQ TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f3a51 RVMI Vdq Hdq Wsd Ib EVX_RANGESD+ke F=AVX512DQ TUPLE1_SCALAR_64 +EVEX.66.W0.0f384c RM Vps Wps - - EVX_RCP14PS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f384c RM Vpd Wpd - - EVX_RCP14PD+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f384d RVM Vdq Hdq Wss - EVX_RCP14SS+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f384d RVM Vdq Hdq Wsd - EVX_RCP14SD+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f3a56 RMI Vps Wps Ib - EVX_REDUCEPS+kbe F=AVX512DQ TUPLE_FULL_32 +EVEX.66.W1.0f3a56 RMI Vpd Wpd Ib - EVX_REDUCEPD+kbe F=AVX512DQ TUPLE_FULL_64 +EVEX.66.W0.LIG.0f3a57 RVMI Vdq Hdq Wss Ib EVX_REDUCESS+ke F=AVX512DQ TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f3a57 RVMI Vdq Hdq Wsd Ib EVX_REDUCESD+ke F=AVX512DQ TUPLE1_SCALAR_64 +EVEX.66.W0.0f3a08 RMI Vps Wps Ib - EVX_RNDSCALEPS+kbe F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f3a09 RMI Vpd Wpd Ib - EVX_RNDSCALEPD+kbe F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f3a0a RVMI Vdq Hdq Wss Ib EVX_RNDSCALESS+ke F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f3a0b RVMI Vdq Hdq Wsd Ib EVX_RNDSCALESD+ke F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f384e RM Vps Wps - - EVX_RSQRT14PS+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f384e RM Vpd Wpd - - EVX_RSQRT14PD+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f384f RVM Vdq Hdq Wss - EVX_RSQRT14SS+k F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f384f RVM Vdq Hdq Wsd - EVX_RSQRT14SD+k F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f382c RVM Vps Hps Wps - EVX_SCALEFPS+kbr F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.0f382c RVM Vpd Hpd Wpd - EVX_SCALEFPD+kbr F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.LIG.0f382d RVM Vdq Hdq Wss - EVX_SCALEFSS+kr F=AVX512F TUPLE1_SCALAR_32 +EVEX.66.W1.LIG.0f382d RVM Vdq Hdq Wsd - EVX_SCALEFSD+kr F=AVX512F TUPLE1_SCALAR_64 +EVEX.66.W0.0f38a2/m MR Md Vx - - EVX_SCATTERDPS+k F=AVX512F VSIB TUPLE1_SCALAR_32 +EVEX.66.W1.0f38a2/m MR Mq Vx - - EVX_SCATTERDPD+k F=AVX512F VSIB TUPLE1_SCALAR_64 +EVEX.66.W0.0f38a3/m MR Md Vh - - EVX_SCATTERQPS+k F=AVX512F VSIB TUPLE1_SCALAR_32 +EVEX.66.W1.0f38a3/m MR Mq Vx - - EVX_SCATTERQPD+k F=AVX512F VSIB TUPLE1_SCALAR_64 +EVEX.66.W0.L12.0f3a23 RVMI Vps Hps Wps Ib EVX_SHUFF32X4+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.L12.0f3a23 RVMI Vpd Hpd Wpd Ib EVX_SHUFF64X2+kb F=AVX512F TUPLE_FULL_64 +EVEX.66.W0.L12.0f3a43 RVMI Vx Hx Wx Ib EVX_SHUFI32X4+kb F=AVX512F TUPLE_FULL_32 +EVEX.66.W1.L12.0f3a43 RVMI Vx Hx Wx Ib EVX_SHUFI64X2+kb F=AVX512F TUPLE_FULL_64 +EVEX.NP.W0.0f57 RVM Vps Hps Wps - EVX_XORPS+kb F=AVX512DQ TUPLE_FULL_32 +EVEX.66.W1.0f57 RVM Vpd Hpd Wpd - EVX_XORPD+kb F=AVX512DQ TUPLE_FULL_64 + + +# AVX512 Mask instructions +VEX.66.W0.L1.0f41/r RVM Kb Kb Kb - KANDB F=AVX512DQ +VEX.NP.W0.L1.0f41/r RVM Kw Kw Kw - KANDW F=AVX512F +VEX.66.W1.L1.0f41/r RVM Kd Kd Kd - KANDD F=AVX512BW +VEX.NP.W1.L1.0f41/r RVM Kq Kq Kq - KANDQ F=AVX512BW +VEX.66.W0.L1.0f42/r RVM Kb Kb Kb - KANDNB F=AVX512DQ +VEX.NP.W0.L1.0f42/r RVM Kw Kw Kw - KANDNW F=AVX512F +VEX.66.W1.L1.0f42/r RVM Kd Kd Kd - KANDND F=AVX512BW +VEX.NP.W1.L1.0f42/r RVM Kq Kq Kq - KANDNQ F=AVX512BW +VEX.66.W0.L0.0f44/r RM Kb Kb - - KNOTB F=AVX512DQ +VEX.NP.W0.L0.0f44/r RM Kw Kw - - KNOTW F=AVX512F +VEX.66.W1.L0.0f44/r RM Kd Kd - - KNOTD F=AVX512BW +VEX.NP.W1.L0.0f44/r RM Kq Kq - - KNOTQ F=AVX512BW +VEX.66.W0.L1.0f45/r RVM Kb Kb Kb - KORB F=AVX512DQ +VEX.NP.W0.L1.0f45/r RVM Kw Kw Kw - KORW F=AVX512F +VEX.66.W1.L1.0f45/r RVM Kd Kd Kd - KORD F=AVX512BW +VEX.NP.W1.L1.0f45/r RVM Kq Kq Kq - KORQ F=AVX512BW +VEX.66.W0.L1.0f46/r RVM Kb Kb Kb - KXNORB F=AVX512DQ +VEX.NP.W0.L1.0f46/r RVM Kw Kw Kw - KXNORW F=AVX512F +VEX.66.W1.L1.0f46/r RVM Kd Kd Kd - KXNORD F=AVX512BW +VEX.NP.W1.L1.0f46/r RVM Kq Kq Kq - KXNORQ F=AVX512BW +VEX.66.W0.L1.0f47/r RVM Kb Kb Kb - KXORB F=AVX512DQ +VEX.NP.W0.L1.0f47/r RVM Kw Kw Kw - KXORW F=AVX512F +VEX.66.W1.L1.0f47/r RVM Kd Kd Kd - KXORD F=AVX512BW +VEX.NP.W1.L1.0f47/r RVM Kq Kq Kq - KXORQ F=AVX512BW +VEX.66.W0.L1.0f4a/r RVM Kb Kb Kb - KADDB F=AVX512DQ +VEX.NP.W0.L1.0f4a/r RVM Kw Kw Kw - KADDW F=AVX512DQ +VEX.66.W1.L1.0f4a/r RVM Kd Kd Kd - KADDD F=AVX512BW +VEX.NP.W1.L1.0f4a/r RVM Kq Kq Kq - KADDQ F=AVX512BW +VEX.66.W0.L1.0f4b/r RVM Kw Kb Kb - KUNPCKBW F=AVX512F +VEX.NP.W0.L1.0f4b/r RVM Kd Kw Kw - KUNPCKWD F=AVX512BW +VEX.NP.W1.L1.0f4b/r RVM Kq Kd Kd - KUNPCKDQ F=AVX512BW +VEX.66.W0.L0.0f98/r RM Kb Kb - - KORTESTB F=AVX512DQ EFL=0--0m00m +VEX.NP.W0.L0.0f98/r RM Kw Kw - - KORTESTW F=AVX512F EFL=0--0m00m +VEX.66.W1.L0.0f98/r RM Kd Kd - - KORTESTD F=AVX512BW EFL=0--0m00m +VEX.NP.W1.L0.0f98/r RM Kq Kq - - KORTESTQ F=AVX512BW EFL=0--0m00m +VEX.66.W0.L0.0f90 RM Kb Kb - - KMOVB F=AVX512DQ +VEX.NP.W0.L0.0f90 RM Kw Kw - - KMOVW F=AVX512F +VEX.66.W1.L0.0f90 RM Kd Kd - - KMOVD F=AVX512BW +VEX.NP.W1.L0.0f90 RM Kq Kq - - KMOVQ F=AVX512BW +VEX.66.W0.L0.0f91/m MR Mb Kb - - KMOVB F=AVX512DQ +VEX.NP.W0.L0.0f91/m MR Mw Kw - - KMOVW F=AVX512F +VEX.66.W1.L0.0f91/m MR Md Kd - - KMOVD F=AVX512BW +VEX.NP.W1.L0.0f91/m MR Mq Kq - - KMOVQ F=AVX512BW +VEX.66.W0.L0.0f92/r RM Kb Rd - - KMOVB F=AVX512DQ +VEX.NP.W0.L0.0f92/r RM Kw Rd - - KMOVW F=AVX512F +VEX.F2.W0.L0.0f92/r RM Kd Rd - - KMOVD F=AVX512BW +VEX.F2.W1.L0.0f92/r RM Kq Rq - - KMOVQ O64 F=AVX512BW +VEX.66.W0.L0.0f93/r RM Gd Kb - - KMOVB F=AVX512DQ +VEX.NP.W0.L0.0f93/r RM Gd Kw - - KMOVW F=AVX512F +VEX.F2.W0.L0.0f93/r RM Gd Kd - - KMOVD F=AVX512BW +VEX.F2.W1.L0.0f93/r RM Gq Kq - - KMOVQ O64 F=AVX512BW +VEX.66.W0.L0.0f99/r RM Kb Kb - - KTESTB F=AVX512DQ EFL=0--0m00m +VEX.NP.W0.L0.0f99/r RM Kw Kw - - KTESTW F=AVX512DQ EFL=0--0m00m +VEX.66.W1.L0.0f99/r RM Kd Kd - - KTESTD F=AVX512BW EFL=0--0m00m +VEX.NP.W1.L0.0f99/r RM Kq Kq - - KTESTQ F=AVX512BW EFL=0--0m00m +VEX.66.W0.L0.0f3a30/r RMI Kb Kb Ib - KSHIFTRB F=AVX512DQ +VEX.66.W1.L0.0f3a30/r RMI Kw Kw Ib - KSHIFTRW F=AVX512F +VEX.66.W0.L0.0f3a31/r RMI Kd Kd Ib - KSHIFTRD F=AVX512BW +VEX.66.W1.L0.0f3a31/r RMI Kq Kq Ib - KSHIFTRQ F=AVX512BW +VEX.66.W0.L0.0f3a32/r RMI Kb Kb Ib - KSHIFTLB F=AVX512DQ +VEX.66.W1.L0.0f3a32/r RMI Kw Kw Ib - KSHIFTLW F=AVX512F +VEX.66.W0.L0.0f3a33/r RMI Kd Kd Ib - KSHIFTLD F=AVX512BW +VEX.66.W1.L0.0f3a33/r RMI Kq Kq Ib - KSHIFTLQ F=AVX512BW + +# AVX512-FP16 +EVEX.NP.W0.0f3a08 RMI Vx Wx Ib - EVX_RNDSCALEPH+kbe F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.NP.W0.LIG.0f3a0a RVMI Vdq Hdq Ww Ib EVX_RNDSCALESH+ke F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.0f3a26 RMI Vx Wx Ib - EVX_GETMANTPH+kbe F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.NP.W0.LIG.0f3a27 RVMI Vdq Hdq Ww Ib EVX_GETMANTSH+ke F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.0f3a56 RMI Vx Wx Ib - EVX_REDUCEPH+kbe F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.NP.W0.LIG.0f3a57 RVMI Vdq Hdq Ww Ib EVX_REDUCESH+ke F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.0f3a66 RMI K Wx Ib - EVX_FPCLASSPH+kb F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.NP.W0.LIG.0f3a67 RMI Kb Ww Ib - EVX_FPCLASSSH+k F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.0f3ac2 RVMI K Hx Wx Ib EVX_CMPPH+kbe F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F3.W0.LIG.0f3ac2 RVMI Kb Hw Ww Ib EVX_CMPSH+ke F=AVX512-FP16 TUPLE1_SCALAR_16 + +EVEX.F3.W0.LIG.M5.10/m RM Vdq Mw - - EVX_MOVSH+k F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.F3.W0.LIG.M5.10/r RVM Vdq Hdq Uw - EVX_MOVSH+k F=AVX512-FP16 +EVEX.F3.W0.LIG.M5.11/m MR Mw Vw - - EVX_MOVSH+k F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.F3.W0.LIG.M5.11/r MVR Udq Hdq Vw - EVX_MOVSH+k F=AVX512-FP16 +EVEX.NP.W0.LIG.M5.1d RVM Vdq Hdq Wd - EVX_CVTSS2SH+kr F=AVX512-FP16 TUPLE1_SCALAR_32 +EVEX.66.W0.M5.1d RM Vh Wx - - EVX_CVTPS2PHX+kbr F=AVX512-FP16 TUPLE_FULL_32 +EVEX.F3.LIG.M5.2a RVM Vdq Hdq Ey - EVX_CVTSI2SH+r F=AVX512-FP16 TUPLE1_SCALAR_OPSZ +EVEX.F3.LIG.M5.2c RM Gy Ww - - EVX_CVTTSH2SI+e F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.F3.LIG.M5.2d RM Gy Ww - - EVX_CVTSH2SI+r F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.LIG.M5.2e RM Vw Ww - - EVX_UCOMISH+e F=AVX512-FP16 TUPLE1_SCALAR_16 EFL=0--0m0mm +EVEX.NP.W0.LIG.M5.2f RM Vw Ww - - EVX_COMISH+e F=AVX512-FP16 TUPLE1_SCALAR_16 EFL=0--0m0mm +EVEX.NP.W0.M5.51 RM Vx Wx - - EVX_SQRTPH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F3.W0.LIG.M5.51 RVM Vdq Hdq Ww - EVX_SQRTSH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.M5.58 RVM Vx Hx Wx - EVX_ADDPH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F3.W0.LIG.M5.58 RVM Vdq Hdq Ww - EVX_ADDSH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.M5.59 RVM Vx Hx Wx - EVX_MULPH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F3.W0.LIG.M5.59 RVM Vdq Hdq Ww - EVX_MULSH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.M5.5a RM Vx Wf - - EVX_CVTPH2PD+kbe F=AVX512-FP16 TUPLE_QUARTER_16 BCST16 +EVEX.66.W1.M5.5a RM Vf Wx - - EVX_CVTPD2PH+kbr F=AVX512-FP16 TUPLE_FULL_64 +EVEX.F3.W0.LIG.M5.5a RVM Vdq Hdq Ww - EVX_CVTSH2SD+ke F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.F2.W1.LIG.M5.5a RVM Vdq Hdq Wq - EVX_CVTSD2SH+kr F=AVX512-FP16 TUPLE1_SCALAR_64 +EVEX.NP.W0.M5.5b RM Vh Wx - - EVX_CVTDQ2PH+kbr F=AVX512-FP16 TUPLE_FULL_32 +EVEX.NP.W1.M5.5b RM Vf Wx - - EVX_CVTQQ2PH+kbr F=AVX512-FP16 TUPLE_FULL_64 +EVEX.66.W0.M5.5b RM Vx Wh - - EVX_CVTPH2DQ+kbr F=AVX512-FP16 TUPLE_HALF_16 BCST16 +EVEX.F3.W0.M5.5b RM Vx Wh - - EVX_CVTTPH2DQ+kbe F=AVX512-FP16 TUPLE_HALF_16 BCST16 +EVEX.NP.W0.M5.5c RVM Vx Hx Wx - EVX_SUBPH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F3.W0.LIG.M5.5c RVM Vdq Hdq Ww - EVX_SUBSH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.M5.5d RVM Vx Hx Wx - EVX_MINPH+kbe F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F3.W0.LIG.M5.5d RVM Vdq Hdq Ww - EVX_MINSH+ke F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.M5.5e RVM Vx Hx Wx - EVX_DIVPH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F3.W0.LIG.M5.5e RVM Vdq Hdq Ww - EVX_DIVSH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.M5.5f RVM Vx Hx Wx - EVX_MAXPH+kbe F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F3.W0.LIG.M5.5f RVM Vdq Hdq Ww - EVX_MAXSH+ke F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.L0.M5.6e RM Vdq Ew - - EVX_MOVW_G2X F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.M5.78 RM Vx Wh - - EVX_CVTTPH2UDQ+kbe F=AVX512-FP16 TUPLE_HALF_16 BCST16 +EVEX.66.W0.M5.78 RM Vx Wf - - EVX_CVTTPH2UQQ+kbe F=AVX512-FP16 TUPLE_QUARTER_16 BCST16 +EVEX.F3.LIG.M5.78 RM Gy Ww - - EVX_CVTTSH2USI+e F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.NP.W0.M5.79 RM Vx Wh - - EVX_CVTPH2UDQ+kbr F=AVX512-FP16 TUPLE_HALF_16 BCST16 +EVEX.66.W0.M5.79 RM Vx Wf - - EVX_CVTPH2UQQ+kbr F=AVX512-FP16 TUPLE_QUARTER_16 BCST16 +EVEX.F3.LIG.M5.79 RM Gy Ww - - EVX_CVTSH2USI+r F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.M5.7a RM Vx Wf - - EVX_CVTTPH2QQ+kbe F=AVX512-FP16 TUPLE_QUARTER_16 BCST16 +EVEX.F2.W0.M5.7a RM Vh Wx - - EVX_CVTUDQ2PH+kbr F=AVX512-FP16 TUPLE_FULL_32 +EVEX.F2.W1.M5.7a RM Vf Wx - - EVX_CVTUQQ2PH+kbr F=AVX512-FP16 TUPLE_FULL_64 +EVEX.66.W0.M5.7b RM Vx Wf - - EVX_CVTPH2QQ+kbr F=AVX512-FP16 TUPLE_QUARTER_16 BCST16 +EVEX.F3.LIG.M5.7b RVM Vdq Hdq Ey - EVX_CVTUSI2SH+r F=AVX512-FP16 TUPLE1_SCALAR_OPSZ +EVEX.NP.W0.M5.7c RM Vx Wx - - EVX_CVTTPH2UW+kbe F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M5.7c RM Vx Wx - - EVX_CVTTPH2W+kbe F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.NP.W0.M5.7d RM Vx Wx - - EVX_CVTPH2UW+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M5.7d RM Vx Wx - - EVX_CVTPH2W+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F3.W0.M5.7d RM Vx Wx - - EVX_CVTW2PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.F2.W0.M5.7d RM Vx Wx - - EVX_CVTUW2PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.L0.M5.7e MR Ew Vw - - EVX_MOVW_X2G F=AVX512-FP16 TUPLE1_SCALAR_16 + +EVEX.66.W0.M6.13 RM Vx Wh - - EVX_CVTPH2PSX+kbe F=AVX512-FP16 TUPLE_HALF_16 BCST16 +EVEX.NP.W0.LIG.M6.13 RVM Vdq Hdq Ww - EVX_CVTSH2SS+ke F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.M6.2c RVM Vx Hx Wx - EVX_SCALEFPH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.LIG.M6.2d RVM Vdq Hdq Ww - EVX_SCALEFSH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.M6.42 RM Vx Wx - - EVX_GETEXPPH+kbe F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.LIG.M6.43 RVM Vdq Hdq Ww - EVX_GETEXPSH+ke F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.M6.4c RM Vx Wx - - EVX_RCPPH+kb F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.LIG.M6.4d RVM Vdq Hdq Ww - EVX_RCPSH+k F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.M6.4e RM Vx Wx - - EVX_RSQRTPH+kb F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.LIG.M6.4f RVM Vdq Hdq Ww - EVX_RSQRTSH+k F=AVX512-FP16 TUPLE1_SCALAR_16 + +# TODO: for F{,C}M{ADD,UL}C{P,S}H, destreg must be unequal to the source registers +EVEX.F3.W0.M6.56 RVM Vx Hx Wx - EVX_FMADDCPH+kbr F=AVX512-FP16 TUPLE_FULL_32 +EVEX.F2.W0.M6.56 RVM Vx Hx Wx - EVX_FCMADDCPH+kbr F=AVX512-FP16 TUPLE_FULL_32 +EVEX.F3.W0.LIG.M6.57 RVM Vdq Hdq Wd - EVX_FMADDCSH+kr F=AVX512-FP16 TUPLE1_SCALAR_32 +EVEX.F2.W0.LIG.M6.57 RVM Vdq Hdq Wd - EVX_FCMADDCSH+kr F=AVX512-FP16 TUPLE1_SCALAR_32 +EVEX.F3.W0.M6.d6 RVM Vx Hx Wx - EVX_FMULCPH+kbr F=AVX512-FP16 TUPLE_FULL_32 +EVEX.F2.W0.M6.d6 RVM Vx Hx Wx - EVX_FCMULCPH+kbr F=AVX512-FP16 TUPLE_FULL_32 +EVEX.F3.W0.LIG.M6.d7 RVM Vdq Hdq Wd - EVX_FMULCSH+kr F=AVX512-FP16 TUPLE1_SCALAR_32 +EVEX.F2.W0.LIG.M6.d7 RVM Vdq Hdq Wd - EVX_FCMULCSH+kr F=AVX512-FP16 TUPLE1_SCALAR_32 + +EVEX.66.W0.M6.96 RVM Vx Hx Wx - EVX_FMADDSUB132PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.a6 RVM Vx Hx Wx - EVX_FMADDSUB213PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.b6 RVM Vx Hx Wx - EVX_FMADDSUB231PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.97 RVM Vx Hx Wx - EVX_FMSUBADD132PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.a7 RVM Vx Hx Wx - EVX_FMSUBADD213PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.b7 RVM Vx Hx Wx - EVX_FMSUBADD231PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.98 RVM Vx Hx Wx - EVX_FMADD132PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.a8 RVM Vx Hx Wx - EVX_FMADD213PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.b8 RVM Vx Hx Wx - EVX_FMADD231PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.LIG.M6.99 RVM Vdq Hdq Ww - EVX_FMADD132SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.LIG.M6.a9 RVM Vdq Hdq Ww - EVX_FMADD213SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.LIG.M6.b9 RVM Vdq Hdq Ww - EVX_FMADD231SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.M6.9a RVM Vx Hx Wx - EVX_FMSUB132PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.aa RVM Vx Hx Wx - EVX_FMSUB213PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.ba RVM Vx Hx Wx - EVX_FMSUB231PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.LIG.M6.9b RVM Vdq Hdq Ww - EVX_FMSUB132SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.LIG.M6.ab RVM Vdq Hdq Ww - EVX_FMSUB213SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.LIG.M6.bb RVM Vdq Hdq Ww - EVX_FMSUB231SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.M6.9c RVM Vx Hx Wx - EVX_FNMADD132PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.ac RVM Vx Hx Wx - EVX_FNMADD213PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.bc RVM Vx Hx Wx - EVX_FNMADD231PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.LIG.M6.9d RVM Vdq Hdq Ww - EVX_FNMADD132SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.LIG.M6.ad RVM Vdq Hdq Ww - EVX_FNMADD213SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.LIG.M6.bd RVM Vdq Hdq Ww - EVX_FNMADD231SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.M6.9e RVM Vx Hx Wx - EVX_FNMSUB132PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.ae RVM Vx Hx Wx - EVX_FNMSUB213PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.M6.be RVM Vx Hx Wx - EVX_FNMSUB231PH+kbr F=AVX512-FP16 TUPLE_FULL_16 BCST16 +EVEX.66.W0.LIG.M6.9f RVM Vdq Hdq Ww - EVX_FNMSUB132SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.LIG.M6.af RVM Vdq Hdq Ww - EVX_FNMSUB213SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 +EVEX.66.W0.LIG.M6.bf RVM Vdq Hdq Ww - EVX_FNMSUB231SH+kr F=AVX512-FP16 TUPLE1_SCALAR_16 diff --git a/third_party/fadec/meson.build b/third_party/fadec/meson.build new file mode 100644 index 0000000..b5dafd4 --- /dev/null +++ b/third_party/fadec/meson.build @@ -0,0 +1,126 @@ +project('fadec', ['c'], default_options: ['warning_level=3', 'c_std=c11'], + meson_version: '>=0.49') + +python3 = find_program('python3') + +# Check Python version +py_version_res = run_command(python3, ['--version'], check: true) +py_version = py_version_res.stdout().split(' ')[1] +if not py_version.version_compare('>=3.9') + error('Python 3.9 required, got @0@'.format(py_version)) +endif + +has_cpp = add_languages('cpp', required: false) + +cc = meson.get_compiler('c') +if cc.has_argument('-fstrict-aliasing') + add_project_arguments('-fstrict-aliasing', language: 'c') +endif +if get_option('warning_level').to_int() >= 3 + extra_warnings = [ + '-Wmissing-prototypes', '-Wshadow', '-Wwrite-strings', '-Wswitch-default', + '-Winline', '-Wstrict-prototypes', '-Wundef', + # We have strings longer than 4095 characters + '-Wno-overlength-strings', + # GCC 8 requires an extra option for strict cast alignment checks, Clang + # always warns, even on architectures without alignment requirements. + '-Wcast-align', '-Wcast-align=strict', + ] + add_project_arguments(cc.get_supported_arguments(extra_warnings), language: 'c') +endif +if cc.get_argument_syntax() == 'msvc' + # Disable some warnings to align warnings with GCC and Clang: + add_project_arguments('-D_CRT_SECURE_NO_WARNINGS', + '/wd4018', # - Signed/unsigned comparison + '/wd4146', # - Unary minus operator applied to unsigned + # type, result still unsigned + '/wd4244', # - Possible loss of data in conversion + # from integer type to smaller integer type + '/wd4245', # - Signed/unsigned assignment + '/wd4267', # - Possible loss of data in conversion + # from size_t to smaller type + '/wd4310', # - Possible loss of data in conversion + # of constant value to smaller type + language: 'c') +endif +if cc.get_id() == 'msvc' and has_cpp + cxx = meson.get_compiler('cpp') + if cxx.get_id() == 'msvc' + # Enable standard conformant preprocessor + add_project_arguments(cxx.get_supported_arguments(['-Zc:preprocessor']), language: 'cpp') + endif +endif + +sources = [] +headers = [] +components = [] + +if get_option('with_decode') + components += 'decode' + headers += files('fadec.h') + sources += files('decode.c', 'format.c') +endif +if get_option('with_encode') + components += 'encode' + headers += files('fadec-enc.h') + sources += files('encode.c') +endif +if get_option('with_encode2') + components += 'encode2' + headers += files('fadec-enc2.h') + sources += files('encode2.c') +endif + +generate_args = [] +if get_option('archmode') != 'only64' + generate_args += ['--32'] +endif +if get_option('archmode') != 'only32' + generate_args += ['--64'] +endif +if get_option('with_undoc') + generate_args += ['--with-undoc'] +endif +if not meson.is_subproject() + generate_args += ['--stats'] +endif + +tables = [] +foreach component : components + tables += custom_target('@0@_table'.format(component), + command: [python3, '@INPUT0@', component, + '@INPUT1@', '@OUTPUT@'] + generate_args, + input: files('parseinstrs.py', 'instrs.txt'), + output: ['fadec-@0@-public.inc'.format(component), + 'fadec-@0@-private.inc'.format(component)], + install: true, + install_dir: [get_option('includedir'), false]) +endforeach + +libfadec = static_library('fadec', sources, tables, install: true) +fadec = declare_dependency(link_with: libfadec, + include_directories: include_directories('.'), + sources: tables) +install_headers(headers) + +foreach component : components + test(component, executable('@0@-test'.format(component), + '@0@-test.c'.format(component), + dependencies: fadec)) + if component == 'encode2' and has_cpp + test(component + '-cpp', executable('@0@-test-cpp'.format(component), + '@0@-test.cc'.format(component), + dependencies: fadec)) + endif +endforeach + +if meson.version().version_compare('>=0.54.0') + meson.override_dependency('fadec', fadec) +endif + +pkg = import('pkgconfig') +pkg.generate(libraries: libfadec, + version: '0.1', + name: 'fadec', + filebase: 'fadec', + description: 'Fast Decoder for x86-32 and x86-64') diff --git a/third_party/fadec/meson_options.txt b/third_party/fadec/meson_options.txt new file mode 100644 index 0000000..3e8dd68 --- /dev/null +++ b/third_party/fadec/meson_options.txt @@ -0,0 +1,6 @@ +option('archmode', type: 'combo', choices: ['both', 'only32', 'only64']) +option('with_undoc', type: 'boolean', value: false) +option('with_decode', type: 'boolean', value: true) +option('with_encode', type: 'boolean', value: true) +# encode2 is off-by-default to reduce size and compile-time +option('with_encode2', type: 'boolean', value: false) diff --git a/third_party/fadec/parseinstrs.py b/third_party/fadec/parseinstrs.py new file mode 100644 index 0000000..435e277 --- /dev/null +++ b/third_party/fadec/parseinstrs.py @@ -0,0 +1,1403 @@ +#!/usr/bin/python3 + +import argparse +import bisect +from collections import OrderedDict, defaultdict, namedtuple +from enum import Enum +from itertools import product +import re +from typing import NamedTuple, FrozenSet, List, Tuple, Union + +INSTR_FLAGS_FIELDS, INSTR_FLAGS_SIZES = zip(*[ + ("modrm_idx", 2), + ("modreg_idx", 2), + ("vexreg_idx", 2), # note: vexreg w/o vex prefix is zeroreg_val + ("imm_idx", 2), + ("evex_bcst", 1), + ("evex_mask", 1), + ("zeroreg_val", 1), + ("lock", 1), + ("imm_control", 3), + ("vsib", 1), + ("modrm_size", 2), + ("modreg_size", 2), + ("vexreg_size", 2), + ("imm_size", 2), + ("legacy", 1), + ("unused2", 1), + ("size_fix1", 3), + ("size_fix2", 2), + ("instr_width", 1), + ("modrm_ty", 3), + ("modreg_ty", 3), + ("vexreg_ty", 2), + ("imm_ty", 0), + ("evex_rc", 2), + ("evex_bcst16", 1), + ("opsize", 3), + ("modrm", 1), + ("ign66", 1), +][::-1]) +class InstrFlags(namedtuple("InstrFlags", INSTR_FLAGS_FIELDS)): + def __new__(cls, **kwargs): + init = {**{f: 0 for f in cls._fields}, **kwargs} + return super(InstrFlags, cls).__new__(cls, **init) + def _encode(self): + enc = 0 + for value, size in zip(self, INSTR_FLAGS_SIZES): + enc = enc << size | (value & ((1 << size) - 1)) + return enc + +ENCODINGS = { + "NP": InstrFlags(), + "M": InstrFlags(modrm=1, modrm_idx=0^3), + "R": InstrFlags(modrm=1, modreg_idx=0^3), # AMX TILEZERO + "M1": InstrFlags(modrm=1, modrm_idx=0^3, imm_idx=1^3, imm_control=1), + "MI": InstrFlags(modrm=1, modrm_idx=0^3, imm_idx=1^3, imm_control=4), + "IM": InstrFlags(modrm=1, modrm_idx=1^3, imm_idx=0^3, imm_control=4), + "MC": InstrFlags(modrm=1, modrm_idx=0^3, vexreg_idx=1^3, zeroreg_val=1), + "MR": InstrFlags(modrm=1, modrm_idx=0^3, modreg_idx=1^3), + "RM": InstrFlags(modrm=1, modrm_idx=1^3, modreg_idx=0^3), + "RMA": InstrFlags(modrm=1, modrm_idx=1^3, modreg_idx=0^3, vexreg_idx=2^3), + "MRI": InstrFlags(modrm=1, modrm_idx=0^3, modreg_idx=1^3, imm_idx=2^3, imm_control=4), + "RMI": InstrFlags(modrm=1, modrm_idx=1^3, modreg_idx=0^3, imm_idx=2^3, imm_control=4), + "MRC": InstrFlags(modrm=1, modrm_idx=0^3, modreg_idx=1^3, vexreg_idx=2^3, zeroreg_val=1), + "AM": InstrFlags(modrm=1, modrm_idx=1^3, vexreg_idx=0^3), + "MA": InstrFlags(modrm=1, modrm_idx=0^3, vexreg_idx=1^3), + "I": InstrFlags(imm_idx=0^3, imm_control=4), + "IA": InstrFlags(vexreg_idx=0^3, imm_idx=1^3, imm_control=4), + "O": InstrFlags(modrm_idx=0^3), + "OI": InstrFlags(modrm_idx=0^3, imm_idx=1^3, imm_control=4), + "OA": InstrFlags(modrm_idx=0^3, vexreg_idx=1^3), + "S": InstrFlags(modreg_idx=0^3), # segment register in bits 3,4,5 + "A": InstrFlags(vexreg_idx=0^3), + "D": InstrFlags(imm_idx=0^3, imm_control=6), + "FD": InstrFlags(vexreg_idx=0^3, imm_idx=1^3, imm_control=2), + "TD": InstrFlags(vexreg_idx=1^3, imm_idx=0^3, imm_control=2), + + "RVM": InstrFlags(modrm=1, modrm_idx=2^3, modreg_idx=0^3, vexreg_idx=1^3), + "RVMI": InstrFlags(modrm=1, modrm_idx=2^3, modreg_idx=0^3, vexreg_idx=1^3, imm_idx=3^3, imm_control=4), + "RVMR": InstrFlags(modrm=1, modrm_idx=2^3, modreg_idx=0^3, vexreg_idx=1^3, imm_idx=3^3, imm_control=3), + "RMV": InstrFlags(modrm=1, modrm_idx=1^3, modreg_idx=0^3, vexreg_idx=2^3), + "VM": InstrFlags(modrm=1, modrm_idx=1^3, vexreg_idx=0^3), + "VMI": InstrFlags(modrm=1, modrm_idx=1^3, vexreg_idx=0^3, imm_idx=2^3, imm_control=4), + "MVR": InstrFlags(modrm=1, modrm_idx=0^3, modreg_idx=2^3, vexreg_idx=1^3), + "MRV": InstrFlags(modrm=1, modrm_idx=0^3, modreg_idx=1^3, vexreg_idx=2^3), +} +ENCODING_OPTYS = ["modrm", "modreg", "vexreg", "imm"] +ENCODING_OPORDER = { enc: sorted(ENCODING_OPTYS, key=lambda ty: getattr(ENCODINGS[enc], ty+"_idx")^3) for enc in ENCODINGS} + +OPKIND_CANONICALIZE = { + "I": "IMM", # immediate + "A": "IMM", # Direct address, far jmp + "J": "IMM", # RIP-relative address + "M": "MEM", # ModRM.r/m selects memory only + "O": "MEM", # Direct address, FD/TD encoding + "R": "GP", # ModRM.r/m selects GP + "B": "GP", # VEX.vvvv selects GP + "E": "GP", # ModRM.r/m selects GP or memory + "G": "GP", # ModRM.reg selects GP + "P": "MMX", # ModRM.reg selects MMX + "N": "MMX", # ModRM.r/m selects MMX + "Q": "MMX", # ModRM.r/m selects MMX or memory + "V": "XMM", # ModRM.reg selects XMM + "H": "XMM", # VEX.vvvv selects XMM + "L": "XMM", # bits7:4 of imm8 select XMM + "U": "XMM", # ModRM.r/m selects XMM + "W": "XMM", # ModRM.r/m selects XMM or memory + "S": "SEG", # ModRM.reg selects SEG + "C": "CR", # ModRM.reg selects CR + "D": "DR", # ModRM.reg selects DR + + # Custom names + "F": "FPU", # F is used for RFLAGS by Intel + "K": "MASK", + "T": "TMM", + "Z": "BND", +} +OPKIND_SIZES = { + "b": 1, + "w": 2, + "d": 4, + "ss": 4, # Scalar single of XMM (d) + "q": 8, + "sd": 8, # Scalar double of XMM (q) + "t": 10, # FPU/ten-byte + "dq": 16, + "qq": 32, + "oq": 64, # oct-quadword + "": 0, # for MEMZ + "v": -1, # operand size (w/d/q) + "y": -1, # operand size (d/q) + "z": -1, # w/d (immediates, min(operand size, 4)) + "a": -1, # z:z + "p": -1, # w:z + "x": -2, # vector size + "h": -3, # half x + "f": -4, # fourth x + "e": -5, # eighth x + "pd": -2, # packed double (x) + "ps": -2, # packed single (x) + + # Custom names + "bs": -1, # sign-extended immediate + "zd": 4, # z-immediate, but always 4-byte operand + "zq": 8, # z-immediate, but always 8-byte operand +} +class OpKind(NamedTuple): + regkind: str + sizestr: str + + SZ_OP = -1 + SZ_VEC = -2 + SZ_VEC_HALF = -3 + SZ_VEC_QUARTER = -4 + SZ_VEC_EIGHTH = -5 + + def abssize(self, opsz=None, vecsz=None): + res = opsz if self.size == self.SZ_OP else \ + vecsz if self.size == self.SZ_VEC else \ + vecsz >> 1 if self.size == self.SZ_VEC_HALF else \ + vecsz >> 2 if self.size == self.SZ_VEC_QUARTER else \ + vecsz >> 3 if self.size == self.SZ_VEC_EIGHTH else self.size + if res is None: + raise Exception("unspecified operand size") + return res + def immsize(self, opsz): + maxsz = 1 if self.sizestr == "bs" else 4 if self.sizestr[0] == "z" else 8 + return min(maxsz, self.abssize(opsz)) + @property + def kind(self): + return OPKIND_CANONICALIZE[self.regkind] + @property + def size(self): + return OPKIND_SIZES[self.sizestr] + @classmethod + def parse(cls, op): + return cls(op[0], op[1:]) + + def __eq__(self, other): + # Custom equality for canonicalization of kind/size. + return isinstance(other, OpKind) and self.kind == other.kind and self.size == other.size + +class InstrDesc(NamedTuple): + mnemonic: str + encoding: str + operands: Tuple[str, ...] + flags: FrozenSet[str] + + OPKIND_REGTYS = { + ("modrm", "GP"): 1, ("modreg", "GP"): 1, ("vexreg", "GP"): 1, + ("modrm", "XMM"): 0, ("modreg", "XMM"): 0, ("vexreg", "XMM"): 0, + ("modrm", "MMX"): 5, ("modreg", "MMX"): 5, + ("modrm", "FPU"): 4, ("vexreg", "FPU"): 3, + ("modrm", "TMM"): 6, ("modreg", "TMM"): 6, ("vexreg", "TMM"): 3, + ("modrm", "MASK"): 7, ("modreg", "MASK"): 7, ("vexreg", "MASK"): 2, + ("modreg", "SEG"): 3, + ("modreg", "DR"): 0, # handled in code + ("modreg", "CR"): 0, # handled in code + ("modrm", "MEM"): 0, + ("imm", "MEM"): 0, ("imm", "IMM"): 0, ("imm", "XMM"): 0, + } + OPKIND_SIZES = { + 0: 0, 1: 1, 2: 2, 4: 3, 8: 4, 16: 5, 32: 6, 64: 7, 10: 0, + # OpKind.SZ_OP: -2, OpKind.SZ_VEC: -3, OpKind.SZ_HALFVEC: -4, + } + + @classmethod + def parse(cls, desc): + desc = desc.split() + mnem, _, compactDesc = desc[5].partition("+") + flags = frozenset(desc[6:] + [{ + "w": "INSTR_WIDTH", + "a": "U67", + "s": "USEG", + "k": "MASK", + "b": "BCST", + "e": "SAE", + "r": "ER", + }[c] for c in compactDesc]) + operands = tuple(OpKind.parse(op) for op in desc[1:5] if op != "-") + return cls(mnem, desc[0], operands, flags) + + def imm_size(self, opsz): + flags = ENCODINGS[self.encoding] + if flags.imm_control < 3: + return 0 + if flags.imm_control == 3: + return 1 + if self.mnemonic == "ENTER": + return 3 + return self.operands[flags.imm_idx^3].immsize(opsz) + + def dynsizes(self): + dynopsz = set(op.size for op in self.operands if op.size < 0) + if {"INSTR_WIDTH", "SZ8"} & self.flags: dynopsz.add(OpKind.SZ_OP) + if OpKind.SZ_OP in dynopsz and len(dynopsz) > 1: + raise Exception(f"conflicting dynamic operand sizes in {self}") + return dynopsz + + def encode(self, mnem, ign66, modrm): + flags = ENCODINGS[self.encoding] + extraflags = {} + + dynopsz = self.dynsizes() + # Operand size either refers to vectors or GP, but not both + if dynopsz and OpKind.SZ_OP not in dynopsz: # Vector operand size + if self.flags & {"SZ8", "D64", "F64", "INSTR_WIDTH", "LOCK", "U66"}: + raise Exception(f"incompatible flags in {self}") + # Allow at most the vector size together with one alternative + dynsizes = [OpKind.SZ_VEC] + list(dynopsz - {OpKind.SZ_VEC}) + extraflags["opsize"] = 4 | (OpKind.SZ_VEC - dynsizes[-1]) + if len(dynsizes) > 2: + raise Exception(f"conflicting vector operand sizes in {self}") + else: # either empty or GP operand size + dynsizes = [OpKind.SZ_OP] + if "SZ8" in self.flags: + dynsizes = [] + if "D64" in self.flags: extraflags["opsize"] = 2 + if "F64" in self.flags: extraflags["opsize"] = 3 + extraflags["lock"] = "LOCK" in self.flags + + if (self.flags & {"SZ8", "INSTR_WIDTH"} or + mnem in ("MOVSX", "MOVZX", "XCHG_NOP", "3DNOW")): + extraflags["legacy"] = 1 + # INSTR_WIDTH defaults to zero, so only enable when SZ8 is unset + if "INSTR_WIDTH" in self.flags and "SZ8" not in self.flags: + extraflags["instr_width"] = 1 + + imm_byte = self.imm_size(4) == 1 + extraflags["imm_control"] = flags.imm_control | imm_byte + + # Sort fixed sizes encodable in size_fix2 as second element. + # But: byte-sized immediates are handled specially and don't cost space. + fixed = set(self.OPKIND_SIZES[op.size] for op in self.operands if + op.size >= 0 and not (imm_byte and op.kind == "IMM")) + fixed = sorted(fixed, key=lambda x: 1 <= x <= 4) + if len(fixed) > 2 or (len(fixed) == 2 and not (1 <= fixed[1] <= 4)): + raise Exception(f"invalid fixed sizes {fixed} in {self}") + sizes = (fixed + [1, 1])[:2] + dynsizes # See operand_sizes in decode.c. + extraflags["size_fix1"] = sizes[0] + extraflags["size_fix2"] = sizes[1] - 1 + + for i, opkind in enumerate(self.operands): + sz = self.OPKIND_SIZES[opkind.size] if opkind.size >= 0 else opkind.size + if opkind.kind == "IMM": + if imm_byte and sz not in [1] + dynsizes[:1]: + raise Exception(f"imm_byte with opsize {sz} in {self}") + extraflags[f"imm_size"] = sz == 1 if imm_byte else sizes.index(sz) + else: + opname = ENCODING_OPORDER[self.encoding][i] + extraflags[f"{opname}_size"] = sizes.index(sz) + extraflags[f"{opname}_ty"] = self.OPKIND_REGTYS[opname, opkind.kind] + + # Miscellaneous Flags + if "VSIB" in self.flags: extraflags["vsib"] = 1 + if "BCST" in self.flags: extraflags["evex_bcst"] = 1 + if "BCST16" in self.flags: extraflags["evex_bcst16"] = 1 + if "MASK" in self.flags: extraflags["evex_mask"] = 1 + if "SAE" in self.flags: extraflags["evex_rc"] = 1 + if "ER" in self.flags: extraflags["evex_rc"] = 3 + if modrm: extraflags["modrm"] = 1 + + if "U66" not in self.flags and (ign66 or "I66" in self.flags): + extraflags["ign66"] = 1 + + enc = flags._replace(**extraflags)._encode() + enc = tuple((enc >> i) & 0xffff for i in range(0, 48, 16)) + # First 2 bytes are the mnemonic, last 6 bytes are the encoding. + return f"{{FDI_{mnem}, {enc[0]}, {enc[1]}, {enc[2]}}}" + +class EntryKind(Enum): + NONE = 0x00 + PREFIX = 0x10 + INSTR = 0x20 + WEAKINSTR = 0x30 + TABLE16 = 0x01 + TABLE8E = 0x11 + ESCAPE = 0x02 + TABLE256 = 0x12 + TABLE_VEX = 0x22 + TABLE_PREFIX = 0x03 + TABLE_ROOT = -1 + @property + def is_table(self): + return self != EntryKind.INSTR and self != EntryKind.WEAKINSTR and self != EntryKind.PREFIX + +opcode_regex = re.compile( + r"^(?:(?P(?PE?VEX\.)?(?PNP|66|F2|F3|NFx)\." + + r"(?:W(?P[01])\.)?(?:L(?P0|1|12|2|IG)\.)?))?" + + r"(?P0f38|0f3a|0f|M[567]\.|)" + + r"(?P[0-9a-f]{2})" + + r"(?:/(?P[0-7]|[rm][0-7]?|[0-7][rm])|(?P[c-f][0-9a-f]))?(?P\+)?$") + +class Opcode(NamedTuple): + prefix: Union[None, str] # None/NP/66/F2/F3/NFx + escape: int # [0, 0f, 0f38, 0f3a] + opc: int + extended: bool # Extend opc or opcext in ModRM.rm, if present + # Fixed ModRM.mod ("r"/"m"), ModRM.reg, ModRM.rm (opcext + AMX) + modrm: Tuple[Union[None, str], Union[None, int], Union[None, int]] + vex: int # 0 = legacy, 1 = VEX, 2 = EVEX + vexl: Union[str, None] # 0, 1, 12, 2, IG, None = used, both + rexw: Union[str, None] # 0, 1, None = both (or ignored) + + @classmethod + def parse(cls, opcode_string): + match = opcode_regex.match(opcode_string) + if match is None: + raise Exception(opcode_string) + return None + + opcext = int(match.group("opcext") or "0", 16) + modreg = match.group("modreg") + if opcext: + modrm = "r", (opcext >> 3) & 7, opcext & 7 + elif modreg: + if modreg[0] in "rm": + modrm = modreg[0], None, int(modreg[1:]) if modreg[1:] else None + else: + modrm = modreg[1:] or None, int(modreg[0]), None + else: + modrm = None, None, None + + return cls( + prefix=match.group("legacy"), + escape=["", "0f", "0f38", "0f3a", "M4.", "M5.", "M6.", "M7."].index(match.group("escape")), + opc=int(match.group("opcode"), 16), + extended=match.group("extended") is not None, + modrm=modrm, + vex=[None, "VEX.", "EVEX."].index(match.group("vex")), + vexl=match.group("vexl"), + rexw=match.group("rexw"), + ) + +def verifyOpcodeDesc(opcode, desc): + flags = ENCODINGS[desc.encoding] + oporder = ENCODING_OPORDER[desc.encoding] + expected_immkinds = ["", "I", "O", "L", "IA", "", "J"][flags.imm_control] + fixed_mod = opcode.modrm[0] + if opcode.extended or desc.mnemonic in ("MOV_CR2G", "MOV_DR2G", "MOV_G2CR", "MOV_G2DR"): + fixed_mod = "r" + expected_modrmkinds = {None: "EQWFKT", "r": "RNUFKT", "m": "M"}[fixed_mod] + # allow F and R for zeroreg, which we overlap with vexreg + expected_vexkinds = "BHKT" if opcode.vex else "BHRF" + for i, opkind in enumerate(desc.operands): + if oporder[i] == "modrm" and opkind.regkind not in expected_modrmkinds: + raise Exception(f"modrm operand-regkind mismatch {opcode}, {desc}") + if oporder[i] == "modreg" and opkind.regkind not in "GPVSCDFKT": + raise Exception(f"modreg operand-regkind mismatch {opcode}, {desc}") + if oporder[i] == "vexreg" and opkind.regkind not in expected_vexkinds: + raise Exception(f"vexreg operand-regkind mismatch {opcode}, {desc}") + if oporder[i] == "imm" and opkind.regkind not in expected_immkinds: + raise Exception(f"imm operand-regkind mismatch {opcode}, {desc}") + if "INSTR_WIDTH" in desc.flags and len(desc.operands) > 3: + raise Exception(f"+w with four operands {opcode}, {desc}") + if opcode.escape == 2 and flags.imm_control != 0: + raise Exception(f"0f38 has no immediate operand {opcode}, {desc}") + if opcode.escape == 3 and desc.imm_size(4) != 1: + raise Exception(f"0f3a must have immediate byte {opcode}, {desc}") + if opcode.escape == 0 and opcode.prefix is not None: + raise Exception(f"unescaped opcode has prefix {opcode}, {desc}") + if opcode.escape == 0 and opcode.vexl is not None: + raise Exception(f"unescaped opcode has L specifier {opcode}, {desc}") + if opcode.escape == 0 and opcode.rexw is not None: + raise Exception(f"unescaped opcode has W specifier {opcode}, {desc}") + if opcode.escape == 0 and opcode.vex: + raise Exception(f"VEX opcode without escape {opcode}, {desc}") + if opcode.vex and opcode.extended: + raise Exception(f"VEX/EVEX must not be extended {opcode}, {desc}") + if opcode.vex and opcode.prefix not in ("NP", "66", "F2", "F3"): + raise Exception(f"VEX/EVEX must have mandatory prefix {opcode}, {desc}") + if opcode.vexl == "IG" and desc.dynsizes() - {OpKind.SZ_OP}: + raise Exception(f"(E)VEX.LIG with dynamic vector size {opcode}, {desc}") + if "VSIB" in desc.flags and opcode.modrm[0] != "m": + raise Exception(f"VSIB for non-memory opcode {opcode}, {desc}") + if opcode.vex == 2 and flags.vexreg_idx: + # Checking this here allows to omit check for V' in decoder. + if desc.operands[flags.vexreg_idx ^ 3].kind != "XMM": + raise Exception(f"EVEX.vvvv must refer to XMM {opcode}, {desc}") + if opcode.vex == 2 and flags.modreg_idx and flags.modreg_idx ^ 3 != 0: + # EVEX.z=0 is only checked for mask operands in ModReg + if desc.operands[flags.modreg_idx ^ 3].kind == "MASK": + raise Exception(f"ModRM.reg mask not first operand {opcode}, {desc}") + # Verify tuple type + if opcode.vex == 2 and opcode.modrm[0] != "r": + tts = [s for s in desc.flags if s.startswith("TUPLE")] + if len(tts) != 1: + raise Exception(f"missing tuple type in {opcode}, {desc}") + if flags.modrm_idx == 3 ^ 3: + raise Exception(f"missing memory operand {opcode}, {desc}") + # From Intel SDM + bcst, evexw, vszs = { + "TUPLE_FULL_16": (2, "0", ( 16, 32, 64)), + "TUPLE_FULL_32": (4, "0", ( 16, 32, 64)), + "TUPLE_FULL_64": (8, "1", ( 16, 32, 64)), + "TUPLE_HALF_16": (2, "0", ( 8, 16, 32)), + "TUPLE_HALF_32": (4, "0", ( 8, 16, 32)), + "TUPLE_HALF_64": (8, "1", ( 8, 16, 32)), + "TUPLE_QUARTER_16": (2, "0", ( 4, 8, 16)), + "TUPLE_FULL_MEM": (None, None, ( 16, 32, 64)), + "TUPLE_HALF_MEM": (None, None, ( 8, 16, 32)), + "TUPLE_QUARTER_MEM": (None, None, ( 4, 8, 16)), + "TUPLE_EIGHTH_MEM": (None, None, ( 2, 4, 8)), + "TUPLE1_SCALAR_8": (None, None, ( 1, 1, 1)), + "TUPLE1_SCALAR_16": (None, None, ( 2, 2, 2)), + "TUPLE1_SCALAR_32": (None, "0", ( 4, 4, 4)), + "TUPLE1_SCALAR_64": (None, "1", ( 8, 8, 8)), + "TUPLE1_SCALAR_OPSZ": (None, None, ( 0, 0, 0)), + "TUPLE1_FIXED_32": (None, None, ( 4, 4, 4)), + "TUPLE1_FIXED_64": (None, None, ( 8, 8, 8)), + "TUPLE2_32": (None, "0", ( 8, 8, 8)), + "TUPLE2_64": (None, "1", (None, 16, 16)), + "TUPLE4_32": (None, "0", (None, 16, 16)), + "TUPLE4_64": (None, "1", (None, None, 32)), + "TUPLE8_32": (None, "0", (None, None, 32)), + "TUPLE_MEM128": (None, None, ( 16, 16, 16)), + # TODO: Fix MOVDDUP tuple size :( + "TUPLE_MOVDDUP": (None, None, ( 16, 32, 64)), + }[tts[0]] + if "BCST" in desc.flags: + if bcst is None: + raise Exception(f"broadcast on incompatible type {opcode}, {desc}") + if ("BCST16" in desc.flags) != (bcst == 2): + raise Exception(f"bcst16 mismatch, should be {bcst} {opcode}, {desc}") + # EVEX.W is used to distinguish 4/8-byte broadcast size + if evexw and opcode.rexw != evexw: + raise Exception(f"incompatible EVEX.W {opcode}, {desc}") + for l, tupsz in enumerate(vszs): + opsz = desc.operands[flags.modrm_idx ^ 3].abssize(0, 16 << l) + if tupsz is not None and opsz != tupsz: + raise Exception(f"memory size {opsz} != {tupsz} {opcode}, {desc}") + +class Trie: + KIND_ORDER = (EntryKind.TABLE_ROOT, EntryKind.ESCAPE, EntryKind.TABLE256, + EntryKind.TABLE_PREFIX, EntryKind.TABLE16, + EntryKind.TABLE8E, EntryKind.TABLE_VEX) + TABLE_LENGTH = { + EntryKind.TABLE_ROOT: 256, + EntryKind.ESCAPE: 8, + EntryKind.TABLE256: 256, + EntryKind.TABLE_PREFIX: 4, + EntryKind.TABLE16: 16, + EntryKind.TABLE8E: 8, + EntryKind.TABLE_VEX: 8, + } + + def __init__(self, root_count): + self.trie = [] + self.trie.append([None] * root_count) + self.kindmap = defaultdict(list) + + def _add_table(self, kind): + self.trie.append([None] * self.TABLE_LENGTH[kind]) + self.kindmap[kind].append(len(self.trie) - 1) + return len(self.trie) - 1 + + def _clone(self, elem): + if not elem or not elem[0].is_table: + return elem + new_num = self._add_table(elem[0]) + self.trie[new_num] = [self._clone(e) for e in self.trie[elem[1]]] + return elem[0], new_num + + def _transform_opcode(self, opc): + realopcext = opc.extended and opc.modrm[2] is None + topc = [opc.opc + i for i in range(8 if realopcext else 1)] + if opc.escape == 0 and opc.opc in (0xc4, 0xc5, 0x62): + assert opc.prefix is None + assert opc.modrm == ("m", None, None) + assert opc.rexw is None + assert opc.vexl is None + # We do NOT encode /m, this is handled by prefix code. + # Order must match KIND_ORDER. + return topc, [0], None, None, None, None, None + elif opc.escape == 0: + troot, tescape, topc = topc, None, None + else: + troot = [[0x0f], [0xc4, 0xc5], [0x62]][opc.vex] + tescape = [opc.escape] + + tprefix, t16, t8e, tvex = None, None, None, None + if opc.prefix == "NFx": + tprefix = [0, 1] + elif opc.prefix: + tprefix = [["NP", "66", "F3", "F2"].index(opc.prefix)] + if opc.modrm != (None, None, None): + # TODO: optimize for /r and /m specifiers to reduce size + mod = {"m": [0], "r": [1], None: [0, 1]}[opc.modrm[0]] + reg = [opc.modrm[1]] if opc.modrm[1] is not None else list(range(8)) + t16 = [x + (y << 1) for x in mod for y in reg] + if opc.modrm[2] is not None and not opc.extended: + t8e = [opc.modrm[2]] + if opc.rexw is not None or (opc.vexl or "IG") != "IG": + rexw = {"0": [0], "1": [1<<0], None: [0, 1<<0]}[opc.rexw] + if opc.vex < 2: + vexl = {"0": [0], "1": [1<<1], "IG": [0, 1<<1]}[opc.vexl or "IG"] + else: + vexl = {"0": [0], "12": [1<<1, 2<<1], "2": [2<<1], "IG": [0, 1<<1, 2<<1, 3<<1]}[opc.vexl or "IG"] + tvex = list(map(sum, product(rexw, vexl))) + # Order must match KIND_ORDER. + return troot, tescape, topc, tprefix, t16, t8e, tvex + + def add_opcode(self, opcode, descidx, root_idx, weak=False): + opcode = self._transform_opcode(opcode) + frontier = [(0, root_idx)] + for elem_kind, elem in zip(self.KIND_ORDER, opcode): + new_frontier = [] + for entry_num, entry_idx in frontier: + entry = self.trie[entry_num] + if elem is None: + if entry[entry_idx] is None or entry[entry_idx][0] != elem_kind: + new_frontier.append((entry_num, entry_idx)) + continue + elem = list(range(self.TABLE_LENGTH[elem_kind])) + if entry[entry_idx] is None: + new_num = self._add_table(elem_kind) + entry[entry_idx] = elem_kind, new_num + elif entry[entry_idx][0] != elem_kind: + # Need to add a new node here and copy entry one level below + new_num = self._add_table(elem_kind) + # Keep original entry, but clone others recursively + self.trie[new_num][0] = entry[entry_idx] + for i in range(1, len(self.trie[new_num])): + self.trie[new_num][i] = self._clone(entry[entry_idx]) + entry[entry_idx] = elem_kind, new_num + for elem_idx in elem: + new_frontier.append((entry[entry_idx][1], elem_idx)) + frontier = new_frontier + for entry_num, entry_idx in frontier: + entry = self.trie[entry_num] + if not entry[entry_idx] or entry[entry_idx][0] == EntryKind.WEAKINSTR: + kind = EntryKind.INSTR if not weak else EntryKind.WEAKINSTR + entry[entry_idx] = kind, descidx << 2 + elif not weak: + raise Exception(f"redundant non-weak {opcode}") + + def add_prefix(self, byte, prefix, root_idx): + if self.trie[0][root_idx] is None: + self.trie[0][root_idx] = EntryKind.TABLE_ROOT, self._add_table(EntryKind.TABLE_ROOT) + self.trie[self.trie[0][root_idx][1]][byte] = EntryKind.PREFIX, prefix + + def deduplicate(self): + synonyms = {} + for kind in self.KIND_ORDER[::-1]: + entries = {} + for num in self.kindmap[kind]: + # Replace previous synonyms + entry = self.trie[num] + for i, elem in enumerate(entry): + if elem and elem[0].is_table and elem[1] in synonyms: + entry[i] = synonyms[elem[1]] + + unique_entry = tuple(entry) + if len(set(unique_entry)) == 1: + # Omit kind if all entries point to the same child + synonyms[num] = entry[0] + self.trie[num] = None + elif unique_entry in entries: + # Deduplicate entries of this kind + synonyms[num] = kind, entries[unique_entry] + self.trie[num] = None + else: + entries[unique_entry] = num + + def compile(self): + offsets = [None] * len(self.trie) + last_off = 0 + for num, entry in enumerate(self.trie[1:], start=1): + if not entry: + continue + offsets[num] = last_off + last_off += (len(entry) + 3) & ~3 + if last_off >= 0x8000: + raise Exception(f"maximum table size exceeded: {last_off:#x}") + + data = [0] * last_off + for off, entry in zip(offsets, self.trie): + if off is None: + continue + for i, elem in enumerate(entry, start=off): + if elem is not None: + value = offsets[elem[1]] if elem[0].is_table else elem[1] + data[i] = value | (elem[0].value & 3) + return tuple(data), [offsets[v] for _, v in self.trie[0]] + + @property + def stats(self): + return {k.name: sum(self.trie[e] is not None for e in v) + for k, v in self.kindmap.items()} + + +def superstring(strs): + # This faces the "shortest superstring" problem, which is NP-hard. + # Preprocessing: remove any strings which are already completely covered + realstrs = [] + for s in sorted(strs, key=len, reverse=True): + for s2 in realstrs: + if s in s2: + break + else: + realstrs.append(s) + + # Greedy heuristic generally yields acceptable results, though it depends on + # the order of the menmonics. More compact results are possible, but the + # expectable gains of an optimal result (probably with O(n!)) are small. + # First sort strings and later do a binary search for each possible prefix. + realstrs.sort() + merged = "" + while realstrs: + for i in range(min(16, len(merged)), 0, -1): + idx = bisect.bisect_left(realstrs, merged[-i:]) + if idx < len(realstrs) and realstrs[idx][:i] == merged[-i:]: + merged += realstrs.pop(idx)[i:] + break + else: + merged += realstrs.pop() + return merged + +def decode_table(entries, args): + modes = args.modes + + trie = Trie(root_count=len(modes)) + for i, mode in enumerate(modes): + # Magic values must match PF_* enum in decode.c. + trie.add_prefix(0x66, 0xfffa, i) + trie.add_prefix(0x67, 0xfffb, i) + trie.add_prefix(0xf0, 0xfffc, i) + trie.add_prefix(0xf2, 0xfffd, i) + trie.add_prefix(0xf3, 0xfffd, i) + trie.add_prefix(0x64, 0xfff9, i) + trie.add_prefix(0x65, 0xfff9, i) + for seg in (0x26, 0x2e, 0x36, 0x3e): + trie.add_prefix(seg, 0xfff8 + (mode <= 32), i) + if mode > 32: + for rex in range(0x40, 0x50): + trie.add_prefix(rex, 0xfffe, i) + + # pause is hardcoded together with XCHG_NOP. + mnems, descs, desc_map = {"PAUSE"}, [], {} + descs.append("{0}") # desc index zero is "invalid" + for weak, opcode, desc in entries: + ign66 = opcode.prefix in ("NP", "66", "F2", "F3") + modrm = opcode.modrm != (None, None, None) + mnem = { + "PUSH_SEG": "PUSH", "POP_SEG": "POP", + "MOV_CR2G": "MOV_CR", "MOV_G2CR": "MOV_CR", + "MOV_DR2G": "MOV_DR", "MOV_G2DR": "MOV_DR", + "MMX_MOVD_M2G": "MMX_MOVD", "MMX_MOVD_G2M": "MMX_MOVD", + "MMX_MOVQ_M2G": "MMX_MOVQ", "MMX_MOVQ_G2M": "MMX_MOVQ", + "SSE_MOVD_X2G": "SSE_MOVD", "SSE_MOVD_G2X": "SSE_MOVD", + "SSE_MOVQ_X2G": "SSE_MOVQ", "SSE_MOVQ_G2X": "SSE_MOVQ", + "VMOVD_X2G": "VMOVD", "VMOVD_G2X": "VMOVD", + "VMOVQ_X2G": "VMOVQ", "VMOVQ_G2X": "VMOVQ", + }.get(desc.mnemonic, desc.mnemonic) + mnems.add(mnem) + descenc = desc.encode(mnem, ign66, modrm) + desc_idx = desc_map.get(descenc) + if desc_idx is None: + desc_idx = desc_map[descenc] = len(descs) + descs.append(descenc) + for i, mode in enumerate(modes): + if "IO"[mode <= 32]+"64" not in desc.flags: + trie.add_opcode(opcode, desc_idx, i, weak) + + trie.deduplicate() + table_data, root_offsets = trie.compile() + + mnems = sorted(mnems) + decode_mnems_lines = [f"FD_MNEMONIC({m},{i})\n" for i, m in enumerate(mnems)] + + mnemonics_intel = [m.replace("SSE_", "").replace("MMX_", "") + .replace("EVX_", "V") + .replace("MOVABS", "MOV").replace("RESERVED_", "") + .replace("JMPF", "JMP FAR").replace("CALLF", "CALL FAR") + .replace("_S2G", "").replace("_G2S", "") + .replace("_X2G", "").replace("_G2X", "") + .replace("_CR", "").replace("_DR", "") + .replace("REP_", "REP ").replace("CMPXCHGD", "CMPXCHG") + .replace("JCXZ", "JCXZ JECXZJRCXZ") + .replace("C_SEP", "CWD CDQ CQO") + .replace("C_EX", "CBW CWDECDQE").replace("XCHG_NOP", "") + .lower() for m in mnems] + mnemonics_str = superstring(mnemonics_intel) + + if args.stats: + print(f"Decode stats: Descs -- {len(descs)} ({8*len(descs)} bytes); ", + f"Trie -- {2*len(table_data)} bytes, {trie.stats}; " + f"Mnems -- {len(mnemonics_str)} + {3*len(mnemonics_intel)} bytes") + + defines = ["FD_TABLE_OFFSET_%d %d\n"%k for k in zip(modes, root_offsets)] + + return "".join(decode_mnems_lines), f"""// Auto-generated file -- do not modify! +#if defined(FD_DECODE_TABLE_DATA) +{"".join(f"{e:#06x}," for e in table_data)} +#elif defined(FD_DECODE_TABLE_DESCS) +{",".join(descs)} +#elif defined(FD_DECODE_TABLE_STRTAB1) +"{mnemonics_str}" +#elif defined(FD_DECODE_TABLE_STRTAB2) +{",".join(str(mnemonics_str.index(mnem)) for mnem in mnemonics_intel)} +#elif defined(FD_DECODE_TABLE_STRTAB3) +{",".join(str(len(mnem)) for mnem in mnemonics_intel)} +#elif defined(FD_DECODE_TABLE_DEFINES) +{"".join("#define " + line for line in defines)} +#else +#error "unspecified decode table" +#endif +""" + +class EncodeVariant(NamedTuple): + opcode: Opcode + desc: InstrDesc + evexbcst: bool = False + evexmask: int = 0 # 0 = none, 1 = must have mask, 2 = mask + EVEX.z + evexsae: int = 0 # 0 = no EVEX.b, 1 = EVEX.b, 2 = EVEX.b + L'L is rounding mode + evexdisp8scale: int = 0 # EVEX disp8 shift + downgrade: int = 0 # 0 = none, 1 = to VEX, 2 = to VEX flipping REXW + flexcc: bool = False # Flexible condition code + +def encode_mnems(entries): + # mapping from (mnem, opsize, ots) -> (opcode, desc) + mnemonics = defaultdict(list) + # Cannot have PAUSE in instrs.txt, because opcodes in without escape must + # not have mandatory prefixes. For decode, this is hardcoded. + mnemonics["PAUSE", 0, ""] = [EncodeVariant(Opcode.parse("F3.90"), InstrDesc.parse("NP - - - - NOP"))] + for weak, opcode, desc in entries: + if "I64" in desc.flags or desc.mnemonic[:9] == "RESERVED_": + continue + mnem_name = {"MOVABS": "MOV", "XCHG_NOP": "XCHG"}.get(desc.mnemonic, desc.mnemonic) + mnem_name = mnem_name.replace("EVX_", "V") + + opsizes, vecsizes = {0}, {0} + prepend_opsize, prepend_vecsize = False, False + # Where to put the operand size in the mnemonic + separate_opsize = "ENC_SEPSZ" in desc.flags + + if "ENC_NOSZ" in desc.flags or not desc.dynsizes(): + pass + elif OpKind.SZ_OP in desc.dynsizes(): + if opcode.rexw is not None: + raise Exception(f"unexpected REXW specifier {desc}") + opsizes = {8} if "SZ8" in desc.flags else {16, 32, 64} + if opcode.prefix in ("NP", "66", "F2", "F3") and "U66" not in desc.flags: + opsizes -= {16} + if "I66" in desc.flags: + opsizes -= {16} + if "D64" in desc.flags: + opsizes -= {32} + prepend_opsize = not separate_opsize + if "F64" in desc.flags: + opsizes = {64} + prepend_opsize = False + elif opcode.vex and opcode.vexl != "IG": # vectors; don't care for SSE + vecsizes = {128, 256, 512} if opcode.vex == 2 else {128, 256} + if opcode.vexl: + vecsizes = {128 << int(c) for c in opcode.vexl} + prepend_vecsize = not separate_opsize + + # All encoding types; reg is r/k (mask); modrm is r/m/b (broadcast) + optypes_base = [] + for i, opkind in enumerate(desc.operands): + reg = "k" if opkind.kind == "MASK" else "r" + opname = ENCODING_OPORDER[desc.encoding][i] + if opname == "modrm": + modrm_type = (opcode.modrm[0] or "rm").replace("r", reg) + if opcode.extended or desc.mnemonic in ("MOV_CR2G", "MOV_DR2G", "MOV_G2CR", "MOV_G2DR"): + modrm_type = reg + if "BCST" in desc.flags: + modrm_type += "b" + optypes_base.append(modrm_type) + elif opname == "modreg" or opname == "vexreg": + optypes_base.append(reg) + else: + optypes_base.append(" iariioo"[ENCODINGS[desc.encoding].imm_control]) + optypes = ["".join(x) for x in product(*optypes_base)] + + prefixes = [("", "")] + if "LOCK" in desc.flags: + prefixes.append(("LOCK_", "LOCK")) + if "ENC_REP" in desc.flags: + prefixes.append(("REP_", "F3")) + if "ENC_REPCC" in desc.flags: + prefixes.append(("REPNZ_", "F2")) + prefixes.append(("REPZ_", "F3")) + + evexmasks = [0] + if "MASK" in desc.flags: + if "VSIB" in desc.flags: + evexmasks = [1] + else: + evexmasks.append(1) + if desc.operands[0].kind != "MASK": + evexmasks.append(2) # maskz only for non-mask destinations + evexsaes = [0] + if "SAE" in desc.flags: + evexsaes.append(1) + elif "ER" in desc.flags: + evexsaes.append(2) + + keys = (opsizes, vecsizes, prefixes, optypes, evexmasks, evexsaes) + for opsize, vecsize, prefix, ots, evexmask, evexsae in product(*keys): + has_memory = "m" in ots or "b" in ots + if prefix[1] == "LOCK" and ots[0] != "m": + continue + if evexmask == 2 and ots[0] != "r": + continue # EVEX.z must be zero for memory destination + if evexsae and (vecsize not in (0, 512) or has_memory): + continue # SAE/ER only works with 512 bit width and no memory + + spec_opcode = opcode + if prefix[1]: + spec_opcode = spec_opcode._replace(prefix=prefix[1]) + if opsize == 64 and "D64" not in desc.flags and "F64" not in desc.flags: + spec_opcode = spec_opcode._replace(rexw="1") + if vecsize == 512: + spec_opcode = spec_opcode._replace(vexl="2") + if vecsize == 256: + spec_opcode = spec_opcode._replace(vexl="1") + if vecsize == 128: + spec_opcode = spec_opcode._replace(vexl="0") + if spec_opcode.vexl == "IG": + spec_opcode = spec_opcode._replace(vexl="0") + if ENCODINGS[desc.encoding].modrm_idx: + modrm = ("m" if has_memory else "r",) + spec_opcode.modrm[1:] + spec_opcode = spec_opcode._replace(modrm=modrm) + if ENCODINGS[desc.encoding].modrm or None not in opcode.modrm: + assert spec_opcode.modrm[0] in ("r", "m") + + evexbcst = "b" in ots + evexdisp8scale = 0 + if spec_opcode.vex == 2 and has_memory: + if not evexbcst: + op = desc.operands[ENCODINGS[desc.encoding].modrm_idx^3] + size = op.abssize(opsize//8, vecsize//8) + evexdisp8scale = size.bit_length() - 1 + elif "BCST16" in desc.flags: + evexdisp8scale = 1 + else: + evexdisp8scale = 2 if spec_opcode.rexw != "1" else 3 + + # Construct mnemonic name + name = prefix[0] + mnem_name + + # Transform MOV_G2X/X2G into MOVD/MOVQ_G2X/X2G. This isn't done for + # VEX for historical reasons and there's no reason to break + # backwards compatibility. This enables EVEX->VEX fallback. + if desc.mnemonic in ("EVX_MOV_G2X", "EVX_MOV_X2G"): + name = name[:-4] + "DQ"[opsize == 64] + name[-4:] + prepend_opsize, opsize = False, 0 + # For VMOVD with memory operand, there's no need to be explicit + # about G2X/X2G, as there's no alternative. For VMOVQ, another + # opcode exists, so keep G2X/X2G there for distinguishing. + if name in ("VMOVD_G2X", "VMOVD_X2G") and has_memory: + name = name.replace("_G2X", "").replace("_X2G", "") + # PEXTR/PBROADCAST/PINSR are stored without size suffix in the table + # to avoid having different tables for 32/64 bit mode due to EVEX.W + # being ignored in 32-bit mode. Add suffix here. + if desc.mnemonic == "EVX_PEXTR": + name += " BW D Q"[desc.operands[0].abssize(opsize//8, vecsize//8)] + prepend_opsize, opsize = False, 0 + if desc.mnemonic == "EVX_PBROADCAST": + name += " BW D Q"[desc.operands[1].abssize(opsize//8, vecsize//8)] + name += "_GP" + prepend_opsize, opsize = False, 0 + if desc.mnemonic == "EVX_PINSR": + name += " BW D Q"[desc.operands[2].abssize(opsize//8, vecsize//8)] + prepend_opsize, opsize = False, 0 + + if prepend_opsize and not ("D64" in desc.flags and opsize == 64): + name += f"_{opsize}"[name[-1] not in "0123456789":] + if prepend_vecsize: + name += f"_{vecsize}"[name[-1] not in "0123456789":] + for ot, op in zip(ots, desc.operands): + name += ot.replace("o", "") + if separate_opsize: + name += f"{op.abssize(opsize//8, vecsize//8)*8}" + if "VSIB" not in desc.flags: + # VSIB implies non-zero mask register, so suffix is not required + name += ["", "_mask", "_maskz"][evexmask] + name += ["", "_sae", "_er"][evexsae] + variant = EncodeVariant(spec_opcode, desc, evexbcst, evexmask, evexsae, evexdisp8scale) + mnemonics[name, opsize, ots].append(variant) + altname = { + "C_EX16": "CBW", "C_EX32": "CWDE", "C_EX64": "CDQE", + "C_SEP16": "CWD", "C_SEP32": "CDQ", "C_SEP64": "CQO", + "CMPXCHGD32m": "CMPXCHG8Bm", "CMPXCHGD64m": "CMPXCHG16Bm", + }.get(name) + if altname: + mnemonics[altname, opsize, ots].append(variant) + if "ENC_CC_BEGIN" in desc.flags: + # Replace last "O" with "cc" + ccname = "cc".join(name.rsplit("O", 1)) + ccvariant = variant._replace(flexcc=True) + mnemonics[ccname, opsize, ots].append(ccvariant) + + for (mnem, opsize, ots), all_variants in mnemonics.items(): + dedup = OrderedDict() + for i, variant in enumerate(all_variants): + PRIO = ["O", "OA", "AO", "AM", "MA", "IA", "OI"] + enc_prio = PRIO.index(variant.desc.encoding) if variant.desc.encoding in PRIO else len(PRIO) + unique = 0 if variant.desc.encoding != "S" else i + # Prefer VEX over EVEX for shorter encoding + key = variant.desc.imm_size(opsize//8), variant.opcode.vex, enc_prio, unique + if key not in dedup: + dedup[key] = variant + variants = [dedup[k] for k in sorted(dedup.keys())] + if len(variants) > 1 and any(v.opcode.vex for v in variants): + # Case 1: VEX -> EVEX promotion (AVX-512, APX) + # Case 2: legacy -> EVEX promotion (APX) + # In any case, there should be exactly one EVEX opcode. + if len(variants) != 2: + raise Exception(f"VEX/EVEX mnemonic with more than two encodings {mnem} {opcode}") + if variants[0].opcode.vex == 2 or variants[1].opcode.vex != 2: + raise Exception(f"EVEX mnemonic not with non-EVEX pair {mnem} {opcode} {variants}") + no_evex, evex = variants[0], variants[1] + + # Make sure that for promotions, only minor things vary. + # REX.W is special, EVEX might mandate W1 while VEX mandates W0/WIG. + # Technically ok: IG -> IG/IG -> 0/0 -> IG/0 -> 0/1 -> IG/1 -> 1 + # rexwdowngrade = (no_evex.opcode.rexw is None or + # no_evex.opcode.rexw == evex.opcode.rexw) + # + # However, other encoders always use W0 in case of WIG for VEX, and + # that's probably most beneficial... so: + # Possible downgrades: IG -> IG/IG -> 0/0 -> IG/0 -> 0/1 -> 1 + # This affects quite a few instructions, so we use an extra bit to + # flip EVEX.W to VEX.W. + + if (no_evex.opcode.prefix != evex.opcode.prefix or + no_evex.opcode.escape != evex.opcode.escape or + no_evex.opcode.opc != evex.opcode.opc or + # reg/mem doesn't matter, it's already fixed in the mnemonic + no_evex.opcode.modrm[1:] != evex.opcode.modrm[1:] or + no_evex.opcode.vexl != evex.opcode.vexl or + # we don't check rexw_flip here, we can always handle it + no_evex.desc.encoding != evex.desc.encoding or + no_evex.desc.operands != evex.desc.operands): + print(mnem, no_evex) + print(mnem, evex) + # Should not happen. + raise Exception("cannot downgrade EVEX?") + else: + rexw_flip = (no_evex.opcode.rexw == "1") != (evex.opcode.rexw == "1") + variants = [evex._replace(downgrade=1 if not rexw_flip else 2)] + mnemonics[mnem, opsize, ots] = variants + + return dict(mnemonics) + +def encode_table(entries, args): + mnemonics = encode_mnems(entries) + mnemonics["NOP", 0, ""] = [EncodeVariant(Opcode.parse("90"), InstrDesc.parse("NP - - - - NOP"))] + mnem_map = {} + alt_table = [0] # first entry is unused + for (mnem, opsize, ots), variants in mnemonics.items(): + supports_high_regs = [] + if variants[0][1].mnemonic in ("MOVSX", "MOVZX") or opsize == 8: + # Should be the same for all variants + desc = variants[0][1] + for i, (ot, op) in enumerate(zip(ots, desc.operands)): + if ot == "r" and op.kind == "GP" and op.abssize(opsize//8) == 1: + supports_high_regs.append(i) + + alt_indices = [i + len(alt_table) for i in range(len(variants) - 1)] + [0] + + if variants[0][1].encoding == "D": + assert 1 <= len(variants) <= 2 + # We handle jump (jmp/jcc) alternatives in code to support Jcc. + if len(variants) > 1: + assert variants[0][1].mnemonic[:1] == "J" + variants = variants[:1] + alt_indices = [0xff] + + enc_opcs = [] + for alt, variant in zip(alt_indices, variants): + opcode, desc = variant.opcode, variant.desc + encoding = ENCODINGS[desc.encoding] + opc_i = opcode.opc + if None not in opcode.modrm: + opc_i |= 0xc000 | opcode.modrm[1] << 11 | opcode.modrm[2] << 8 + elif opcode.modrm[1] is not None: + opc_i |= opcode.modrm[1] << 8 + if opcode.modrm == ("m", None, 4): + opc_i |= 0x2000000000 # FORCE_SIB + if not opcode.vex: + assert opcode.escape < 4 + opc_i |= opcode.escape * 0x10000 + opc_i |= 0x80000 if opcode.prefix == "66" or opsize == 16 else 0 + opc_i |= 0x100000 if opcode.prefix == "F2" else 0 + opc_i |= 0x200000 if opcode.prefix == "F3" else 0 + else: + assert opcode.escape < 8 + opc_i |= opcode.escape * 0x10000 + if opcode.prefix == "66" or opsize == 16: + assert opcode.prefix not in ("F2", "F3") + opc_i |= 0x100000 + if opcode.prefix == "F3": + opc_i |= 0x200000 + elif opcode.prefix == "F2": + opc_i |= 0x300000 + opc_i |= 0x400000 if opcode.rexw == "1" else 0 + if opcode.prefix == "LOCK": + opc_i |= 0x800000 + elif opcode.vex == 1: + opc_i |= 0x1000000 + 0x800000 * int(opcode.vexl or 0) + elif opcode.vex == 2: + opc_i |= 0x2000000 + # L'L encodes SAE rounding mode otherwise + if not variant.evexsae: + opc_i |= 0x800000 * int(opcode.vexl or 0) + assert not (variant.evexsae and variant.evexbcst) + opc_i |= 0x4000000 if variant.evexsae or variant.evexbcst else 0 + opc_i |= 0x8000000 if "VSIB" in desc.flags else 0 + opc_i |= 0x1000000000 if variant.evexmask == 2 else 0 + opc_i |= 0x4000000000 if variant.downgrade in (1, 2) else 0 + opc_i |= 0x40000000000 if variant.downgrade == 2 else 0 + opc_i |= 0x8000000000 * variant.evexdisp8scale + if alt >= 0x100: + raise Exception("encode alternate bits exhausted") + opc_i |= sum(1 << i for i in supports_high_regs) << 45 + if encoding.imm_control >= 3: + opc_i |= desc.imm_size(opsize//8) << 47 + elif encoding.imm_control in (1, 2): + # Must be an arbitrary non-zero value, replaced by address size + # for imm_ctl=2 and zero for imm_ctl=1 (constant 1). + opc_i |= 1 << 47 + + enc_encoding = desc.encoding + if desc.encoding != "I" and desc.encoding.endswith("I"): + enc_encoding = desc.encoding[:-1] + elif desc.encoding == "IA": + enc_encoding = "A" + opc_i |= ["NP", "M", "R", "M1", "MC", "MR", "RM", "RMA", "MRC", + "AM", "MA", "I", "O", "OA", "S", "A", "D", "FD", "TD", "IM", + "RVM", "RVMR", "RMV", "VM", "MVR", "MRV", + ].index(enc_encoding) << 51 + opc_i |= alt << 56 + enc_opcs.append(opc_i) + mnem_map[f"FE_{mnem}"] = enc_opcs[0] + alt_table += enc_opcs[1:] + + mnem_tab = "".join(f"#define {m} {v:#x}\n" for m, v in mnem_map.items()) + alt_tab = "".join(f"[{i}] = {v:#x},\n" for i, v in enumerate(alt_table)) + return mnem_tab, alt_tab + +def unique(it): + vals = set(it) + if len(vals) != 1: + raise Exception(f"multiple values: {vals}") + return next(iter(vals)) + +def encode2_gen_legacy(variant: EncodeVariant, opsize: int, supports_high_regs: list[int], imm_expr: str, imm_size_expr: str, has_idx: bool) -> str: + opcode = variant.opcode + desc = variant.desc + flags = ENCODINGS[variant.desc.encoding] + code = "" + + rex_expr = [] if opcode.rexw != "1" else ["0x48"] + rex_values = set() + for i in supports_high_regs: + rex_expr.append(f"(op_reg_idx(op{i}) >= 4 && op_reg_idx(op{i}) <= 15?0x40:0)") + rex_values.add(0x40) + has_modreg_rex = False + if flags.modreg_idx: + has_modreg_rex = desc.operands[flags.modreg_idx^3].kind in ("GP", "XMM", "CR", "DR") + if flags.modrm_idx: + if opcode.modrm[0] == "m": + rex_modreg_op = f"op_reg_idx(op{flags.modreg_idx^3})" if has_modreg_rex else "0" + rex_expr.append(f"enc_rex_mem(op{flags.modrm_idx^3}, {rex_modreg_op})") + rex_values |= {0x41, 0x42, 0x44} + elif desc.operands[flags.modrm_idx^3].kind in ("GP", "XMM"): + rex_expr.append(f"(op_reg_idx(op{flags.modrm_idx^3})&8?0x1:0)") + rex_values.add(0x41) + if has_modreg_rex: + rex_expr.append(f"(op_reg_idx(op{flags.modreg_idx^3})&8?0x4:0)") + rex_values.add(0x44) + elif has_modreg_rex: # O encoding + rex_expr.append(f"(op_reg_idx(op{flags.modreg_idx^3})&8?0x1:0)") + rex_values.add(0x41) + + if rex_expr: + code += f" unsigned rex = {'|'.join(rex_expr) or '0'};\n" + for i in supports_high_regs: + code += f" if (rex && op_reg_gph(op{i})) return 0;\n" + + if not has_idx: + code += " unsigned idx = 0;\n" + if opcode.prefix == "LOCK": + code += f" buf[idx++] = 0xF0;\n" + if opsize == 16 or opcode.prefix == "66": + code += " buf[idx++] = 0x66;\n" + if opcode.prefix in ("F2", "F3"): + code += f" buf[idx++] = 0x{opcode.prefix};\n" + if opcode.rexw == "1": + code += f" buf[idx++] = rex;\n" + elif len(rex_values) == 1: + code += f" buf[idx] = {next(iter(rex_values))};\n idx += rex != 0;\n" + elif len(rex_values) == 2: + code += f" buf[idx] = 0x40|rex;\n idx += rex != 0;\n" + elif rex_expr: # memory, multiplication is expensive + code += f" if (rex) buf[idx++] = 0x40|rex;\n" + if opcode.escape: + code += f" buf[idx++] = 0x0F;\n" + if opcode.escape == 2: + code += f" buf[idx++] = 0x38;\n" + elif opcode.escape == 3: + code += f" buf[idx++] = 0x3A;\n" + opcodestr = f"{opcode.opc:#x}" + ("|(flags>>16)" if variant.flexcc else "") + code += f" buf[idx++] = {opcodestr};\n" + if None not in opcode.modrm: + opcext = 0xc0 | opcode.modrm[1] << 3 | opcode.modrm[2] + code += f" buf[idx++] = {opcext:#x};\n" + + if flags.modrm: + if flags.modreg_idx: + modreg = f"op_reg_idx(op{flags.modreg_idx^3})" + else: + modreg = opcode.modrm[1] or 0 + if opcode.modrm[0] == "m": + assert "VSIB" not in desc.flags + assert opcode.modrm[2] is None + modrm = f"op{flags.modrm_idx^3}" + code += f" idx = enc_mem(buf+idx, idx+{imm_size_expr}, {modrm}, {modreg}, 0, 0);\n" + code += f" if (!idx) return 0;\n idx -= {imm_size_expr};\n" + else: + if flags.modrm_idx: + modrm = f"op_reg_idx(op{flags.modrm_idx^3})" + else: + modrm = f"{opcode.modrm[2] or 0}" + code += f" buf[idx++] = 0xC0|({modreg}<<3)|({modrm}&7);\n" + elif flags.modrm_idx: + code += f" buf[idx-1] |= op_reg_idx(op{flags.modrm_idx^3}) & 7;\n" + if flags.imm_control >= 2: + if flags.imm_control == 6: + imm_expr += " - idx" + code += f" enc_imm(buf+idx, {imm_expr}, {imm_size_expr});\n" + code += f" return idx + {imm_size_expr};\n" + else: + code += f" return idx;\n" + return code + +def encode2_gen_vex(variant: EncodeVariant, imm_expr: str, imm_size_expr: str, has_idx: bool) -> str: + opcode = variant.opcode + flags = ENCODINGS[variant.desc.encoding] + code = "" + + helperopc = opcode.opc << 16 + helperopc |= ["NP", "66", "F3", "F2"].index(opcode.prefix) << 8 + helperopc |= 0x8000 if opcode.rexw == "1" else 0 + if not variant.evexsae: + # ER: L'L encodes rounding mode for SAE + helperopc |= 0x0020 * int(opcode.vexl or 0) # EVEX.L'L + helperopc |= opcode.escape << 10 + helperopc |= 0x10 if variant.evexsae or variant.evexbcst else 0 # EVEX.b + helperopc |= 0x80 if variant.evexmask == 2 else 0 # EVEX.z + helperopc |= 0x1000000 if variant.downgrade in (1, 2) else 0 + helperopc |= 0x2000000 if variant.downgrade == 2 else 0 + helperopc = f"{helperopc:#x}" + if variant.flexcc: + helperopc += "|(flags&FE_CC_MASK)" + if variant.evexsae == 2: + helperopc += "|(flags&FE_RC_MASK)" + if variant.evexmask: + code += " if (!op_reg_idx(opmask)) return 0;\n" + helperopc += "|(op_reg_idx(opmask)&7)" + + if flags.modreg_idx: + modreg = f"op_reg_idx(op{flags.modreg_idx^3})" + else: + modreg = opcode.modrm[1] or 0 + vexop = f"op_reg_idx(op{flags.vexreg_idx^3})" if flags.vexreg_idx else 0 + is_memory = opcode.modrm[0] == "m" + if not flags.modrm and opcode.modrm == (None, None, None): + # No ModRM, prefix only (VZEROUPPER/VZEROALL) + assert opcode.vex == 1 + assert not has_idx + helperfn, helperargs = "enc_vex_common", f"0, 0, 0, 0" + elif opcode.modrm[0] == "m": + vsib = "VSIB" in variant.desc.flags + helperfn = "enc" + ["", "_vex", "_evex"][opcode.vex] + ["_mem", "_vsib"][vsib] + assert opcode.modrm[2] in (None, 4) + forcesib = 1 if opcode.modrm[2] == 4 else 0 # AMX + modrm = f"op{flags.modrm_idx^3}" + ripoff = imm_size_expr + ("" if not has_idx else "+idx") + helperargs = (f"{modrm}, {modreg}, {vexop}, {ripoff}, " + + f"{forcesib}, {variant.evexdisp8scale}") + else: + if flags.modrm_idx: + modrm = f"op_reg_idx(op{flags.modrm_idx^3})" + else: + modrm = f"{opcode.modrm[2] or 0}" + suffix = "_reg" + if (opcode.vex == 2 and flags.modrm_idx and + variant.desc.operands[flags.modrm_idx^3].kind == "XMM"): + suffix = "_xmm" + helperfn = "enc" + ["", "_vex", "_evex"][opcode.vex] + suffix + helperargs = f"{modrm}, {modreg}, {vexop}" + bufidx = "buf" if not has_idx else "buf+idx" + helpercall = f"{helperfn}({bufidx}, {helperopc}, {helperargs})" + if flags.imm_control >= 2: + assert flags.imm_control < 6, "jmp with VEX/EVEX?" + if is_memory: + code += f" unsigned instlen = {helpercall};\n" + code += f" if (instlen) enc_imm(buf+instlen-{imm_size_expr}, {imm_expr}, {imm_size_expr});\n" + code += f" return instlen;\n" + else: + code += f" unsigned vexoff = {helpercall};\n" + code += f" enc_imm({bufidx}+vexoff, {imm_expr}, {imm_size_expr});\n" + code += f" return vexoff ? vexoff+{imm_size_expr}{'+idx' if has_idx else ''} : 0;\n" + elif has_idx and not is_memory: + code += f" unsigned vexoff = {helpercall};\n" + code += f" return vexoff ? vexoff+idx : 0;\n" + else: + code += f" return {helpercall};\n" + return code + +def encode2_table(entries, args): + mnemonics = encode_mnems(entries) + + enc_decls, enc_code = "", "" + for (mnem, opsize, ots), variants in mnemonics.items(): + max_imm_size = max(v.desc.imm_size(opsize//8) for v in variants) + + supports_high_regs = [] + if variants[0].desc.mnemonic in ("MOVSX", "MOVZX") or opsize == 8: + # Should be the same for all variants + for i, (ot, op) in enumerate(zip(ots, variants[0].desc.operands)): + if ot == "r" and op.kind == "GP" and op.abssize(opsize//8) == 1: + supports_high_regs.append(i) + supports_vsib = unique("VSIB" in v.desc.flags for v in variants) + opkinds = unique(tuple(op.kind for op in v.desc.operands) for v in variants) + evexmask = unique(v.evexmask for v in variants) + evexsae = unique(v.evexsae for v in variants) + + OPKIND_LUT = {"FPU": "ST", "SEG": "SREG", "MMX": "MM"} + reg_tys = [OPKIND_LUT.get(opkind, opkind) for opkind in opkinds] + + fnname = f"fe64_{mnem}" + op_tys = [{ + "i": f"int{max_imm_size*8 if max_imm_size != 3 else 32}_t", + "a": "uintptr_t", + "r": f"FeReg{reg_ty if i not in supports_high_regs else 'GPLH'}", + "k": "FeRegMASK", + "m": "FeMem" if not supports_vsib else "FeMemV", + "b": "FeMem", + "o": "const void*", + }[ot] for i, (ot, reg_ty) in enumerate(zip(ots, reg_tys))] + fn_opargs = ", FeRegMASK opmask" if evexmask else "" + fn_opargs += "".join(f", {ty} op{i}" for i, ty in enumerate(op_tys)) + fn_sig = f"unsigned ({fnname})(uint8_t* buf, int flags{fn_opargs})" + enc_decls += f"{fn_sig};\n" + if supports_high_regs: + enc_decls += f"#define fe64_{mnem}(buf, flags" + enc_decls += "".join(f", op{i}" for i in range(len(op_tys))) + enc_decls += f") {fnname}(buf, flags" + enc_decls += "".join(f", FE_MAKE_GPLH(op{i})" if i in supports_high_regs else f", op{i}" for i in range(len(op_tys))) + enc_decls += f")\n" + + code = f"{fn_sig} {{\n" + + has_memory = unique(v.opcode.modrm[0] == "m" for v in variants) + has_useg = unique("USEG" in v.desc.flags for v in variants) + has_u67 = unique("U67" in v.desc.flags for v in variants) + if has_memory or has_useg: + # segment override without addrsize override shouldn't happen + assert has_memory or has_u67 + code += f" unsigned idx = UNLIKELY(flags & (FE_SEG_MASK|FE_ADDR32)) ? enc_seg67(buf, flags) : 0;\n" + elif has_u67: + # STOS, SCAS, JCXZ, LOOP, LOOPcc + code += f" unsigned idx = UNLIKELY(flags & FE_ADDR32) ? (*buf=0x67, 1) : 0;\n" + else: + code += " (void) flags;\n" + + # indicate whether an idx variable exists + has_idx = has_memory or has_useg or has_u67 + + for i, variant in enumerate(variants): + opcode, desc = variant.opcode, variant.desc + flags = ENCODINGS[desc.encoding] + + conds = [] + # Select usable encoding. + if desc.encoding == "S": + # Segment encoding is weird. + conds.append(f"op_reg_idx(op0)=={(opcode.opc>>3)&0x7:#x}") + if desc.mnemonic == "XCHG_NOP" and opsize == 32: + # XCHG eax, eax must not be encoded as 90 -- that'd be NOP. + conds.append(f"!(op_reg_idx(op0)==0&&op_reg_idx(op1)==0)") + if flags.vexreg_idx and not opcode.vex: # vexreg w/o vex is zeroreg + conds.append(f"op_reg_idx(op{flags.vexreg_idx^3})=={flags.zeroreg_val}") + + imm_size = desc.imm_size(opsize//8) + imm_size_expr = f"{imm_size}" + imm_expr = f"(int64_t) op{flags.imm_idx^3}" + if flags.imm_control == 1: + conds.append(f"op{flags.imm_idx^3} == 1") + elif flags.imm_control == 2: + imm_size_expr = "(flags & FE_ADDR32 ? 4 : 8)" + imm_expr = f"(int64_t) (flags & FE_ADDR32 ? (int32_t) {imm_expr} : {imm_expr})" + elif flags.imm_control == 3: + imm_expr = f"op_reg_idx(op{flags.imm_idx^3}) << 4" + code += f" if (op_reg_idx(op{flags.imm_idx^3}) >= 16) return 0;\n" + elif flags.imm_control == 4 and imm_size == 3: # ENTER + code += f" if ((uint32_t) op{flags.imm_idx^3} >= 0x1000000) return 0;\n" + elif flags.imm_control == 4 and imm_size < max_imm_size: + conds.append(f"op_imm_n({imm_expr}, {imm_size})") + elif flags.imm_control == 6: + imm_expr = f"{imm_expr} - (int64_t) buf - {imm_size}" + if i != len(variants) - 1: # only Jcc+JMP + conds.append(f"!(flags & FE_JMPL)") + # assume one-byte opcode without escape/prefixes + conds.append(f"op_imm_n({imm_expr}-1, {imm_size})") + + if conds: + code += f" if ({'&&'.join(conds)}) {{\n" + + if opcode.vex: + code += encode2_gen_vex(variant, imm_expr, imm_size_expr, has_idx) + else: + code += encode2_gen_legacy(variant, opsize, supports_high_regs, imm_expr, imm_size_expr, has_idx) + + if conds: + code += " }\n" + else: + break + else: + code += " return 0;\n" + + enc_code += code + "}\n" + + return enc_decls, enc_code + + +if __name__ == "__main__": + generators = { + "decode": decode_table, + "encode": encode_table, + "encode2": encode2_table, + } + + parser = argparse.ArgumentParser() + parser.add_argument("--32", dest="modes", action="append_const", const=32) + parser.add_argument("--64", dest="modes", action="append_const", const=64) + parser.add_argument("--with-undoc", action="store_true") + parser.add_argument("--stats", action="store_true") + parser.add_argument("mode", choices=generators.keys()) + parser.add_argument("table", type=argparse.FileType('r')) + parser.add_argument("out_public", type=argparse.FileType('w')) + parser.add_argument("out_private", type=argparse.FileType('w')) + args = parser.parse_args() + + entries = [] + for line in args.table.read().splitlines(): + if not line or line[0] == "#": continue + line, weak = (line, False) if line[0] != "*" else (line[1:], True) + opcode_string, desc_string = tuple(line.split(maxsplit=1)) + opcode, desc = Opcode.parse(opcode_string), InstrDesc.parse(desc_string) + verifyOpcodeDesc(opcode, desc) + if "UNDOC" not in desc.flags or args.with_undoc: + entries.append((weak, opcode, desc)) + + res_public, res_private = generators[args.mode](entries, args) + args.out_public.write(res_public) + args.out_private.write(res_private)