mirror of
https://github.com/NohamR/Reclass.git
synced 2026-05-10 19:59:21 +00:00
feat: disasm popup, symbol separation, context menu improvements, RVA fixes
- Add Fadec x86 disassembler with hover popup for FuncPtr/void Pointer nodes - Separate pointer symbol from address: // prefix, green comment coloring, independent hover/click zones (address triggers popup, symbol is passive) - Fix RVA margin and inline local offset for pointer-expanded vtable children using ptrBase field threaded through composition - Expand multi-select context menu with quick-convert, duplicate, copy address - Remove Edit Value from hex node context menu - Fix heatmap flickering on hex nodes (remove per-byte alternation) - Fix popup repositioning when moving mouse between lines - Truncate disasm popup to 6 lines with ... indicator - Add BUILD_UI_TESTS option to skip widget tests on headless CI - Add test_disasm with 35 test cases for disassembly and hex dump - Add KUSER_SHARED_DATA example .rcx file
This commit is contained in:
IChooseYou
345
third_party/fadec/encode2.c
vendored
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345
third_party/fadec/encode2.c
vendored
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@@ -0,0 +1,345 @@
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <fadec-enc2.h>
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#ifdef __GNUC__
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#define LIKELY(x) __builtin_expect(!!(x), 1)
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#define UNLIKELY(x) __builtin_expect(!!(x), 0)
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#if __has_attribute(cold) && __has_attribute(preserve_most)
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#define HINT_COLD __attribute__((cold,preserve_most,noinline))
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#elif __has_attribute(cold)
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#define HINT_COLD __attribute__((cold,noinline))
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#else
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#define HINT_COLD
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#endif
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#else
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#define LIKELY(x) (x)
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#define UNLIKELY(x) (x)
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#define HINT_COLD
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#endif
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#define op_reg_idx(op) (op).idx
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#define op_reg_gph(op) (((op).idx & ~0x3) == 0x24)
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#define op_mem_base(mem) op_reg_idx((mem).base)
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#define op_mem_idx(mem) op_reg_idx((mem).idx)
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static bool
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op_imm_n(int64_t imm, unsigned immsz) {
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if (immsz == 0 && !imm) return true;
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if (immsz == 1 && (int8_t) imm == imm) return true;
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if (immsz == 2 && (int16_t) imm == imm) return true;
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if (immsz == 3 && (imm&0xffffff) == imm) return true;
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if (immsz == 4 && (int32_t) imm == imm) return true;
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if (immsz == 8 && (int64_t) imm == imm) return true;
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return false;
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}
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HINT_COLD static unsigned
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enc_seg67(uint8_t* buf, unsigned flags) {
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unsigned idx = 0;
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if (UNLIKELY(flags & FE_SEG_MASK)) {
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unsigned seg = (0x65643e362e2600 >> (8 * (flags & FE_SEG_MASK))) & 0xff;
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buf[idx++] = seg;
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}
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if (UNLIKELY(flags & FE_ADDR32)) buf[idx++] = 0x67;
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return idx;
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}
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static unsigned
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enc_rex_mem(FeMem op0, uint64_t op1) {
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// Essentially just an and+or due to struct layout.
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uint32_t val = op1 | op0.flags | (op_mem_base(op0) << 8) |
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((uint32_t)op_mem_idx(op0) << 24);
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// Combine REX.RXB using multiplication for branch-less code.
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uint32_t masked = val & 0x08000808;
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return masked ? (uint8_t) (masked * (1|(1<<15)|(1<<25)) >> 26) + 0x40 : 0;
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}
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static void
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enc_imm(uint8_t* buf, uint64_t imm, unsigned immsz) {
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#ifdef __GNUC__
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// Clang doesn't fold the loop into a single store.
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// See: https://github.com/llvm/llvm-project/issues/154696
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if (__builtin_constant_p(immsz)) {
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__builtin_memcpy(buf, &imm, immsz);
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return;
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}
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#endif
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for (unsigned i = 0; i < immsz; i++)
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*buf++ = imm >> 8 * i;
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}
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static int
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enc_mem_common(uint8_t* buf, unsigned ripoff, FeMem op0, uint64_t op1,
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unsigned disp8scale) {
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int mod = 0, reg = op1 & 7, rm;
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unsigned sib = 0x20;
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bool withsib = false;
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unsigned dispsz = 0;
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int32_t off = op0.off;
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if (op_reg_idx(op0.idx) < 0x80) {
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int scalabs = op0.scale;
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if (UNLIKELY((unsigned) (op0.scale - 1) >= 8 ||
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(op0.scale & (op0.scale - 1))))
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return 0;
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unsigned scale = (scalabs & 0xA ? 1 : 0) | (scalabs & 0xC ? 2 : 0);
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sib = scale << 6 | (op_reg_idx(op0.idx) & 7) << 3;
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withsib = true;
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} else if (UNLIKELY(op0.scale != 0)) {
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return 0;
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}
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if (UNLIKELY(op0.base.idx >= 0x20)) {
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if (UNLIKELY(op0.base.idx >= op_reg_idx(FE_NOREG))) {
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*buf++ = (reg << 3) | 4;
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*buf++ = sib | 5;
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enc_imm(buf, off, 4);
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return ripoff + 6;
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} else if (LIKELY(op0.base.idx == FE_IP.idx)) {
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if (withsib)
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return 0;
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*buf++ = (reg << 3) | 5;
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// Adjust offset, caller doesn't know instruction length.
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enc_imm(buf, off - ripoff - 5, 4);
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return ripoff + 5;
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} else {
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return 0;
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}
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}
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rm = op_reg_idx(op0.base) & 7;
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if (off) {
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if (LIKELY(!disp8scale)) {
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mod = (int8_t) off == off ? 0x40 : 0x80;
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dispsz = (int8_t) off == off ? 1 : 4;
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} else {
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if (!(off & ((1 << disp8scale) - 1)) && op_imm_n(off >> disp8scale, 1))
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off >>= disp8scale, mod = 0x40, dispsz = 1;
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else
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mod = 0x80, dispsz = 4;
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}
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} else if (rm == 5) {
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dispsz = 1;
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mod = 0x40;
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}
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// Always write four bytes of displacement. The buffer is always large
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// enough, and we truncate by returning a smaller "written bytes" count.
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if (withsib || rm == 4) {
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*buf++ = mod | (reg << 3) | 4;
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*buf++ = sib | rm;
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enc_imm(buf, off, 4);
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return ripoff + 2 + dispsz;
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} else {
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*buf++ = mod | (reg << 3) | rm;
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enc_imm(buf, off, 4);
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return ripoff + 1 + dispsz;
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}
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}
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static int
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enc_mem(uint8_t* buf, unsigned ripoff, FeMem op0, uint64_t op1, bool forcesib,
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unsigned disp8scale) {
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if (UNLIKELY(op_reg_idx(op0.idx) == 4))
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return 0;
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if (forcesib && op_reg_idx(op0.idx) == op_reg_idx(FE_NOREG)) {
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op0.scale = 1;
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op0.idx = FE_GP(4);
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}
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return enc_mem_common(buf, ripoff, op0, op1, disp8scale);
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}
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static int
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enc_mem_vsib(uint8_t* buf, unsigned ripoff, FeMemV op0, uint64_t op1,
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bool forcesib, unsigned disp8scale) {
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(void) forcesib;
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FeMem mem = FE_MEM(op0.base, op0.scale, FE_GP(op_reg_idx(op0.idx)), op0.off);
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return enc_mem_common(buf, ripoff, mem, op1, disp8scale);
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}
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// EVEX/VEX "Opcode" format:
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//
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// | EVEX byte 4 | P P M M M - - W | Opcode byte | VEX-D VEX-D-FLIPW
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// 0 8 16 24
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enum {
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FE_OPC_VEX_WPP_SHIFT = 8,
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FE_OPC_VEX_WPP_MASK = 0x83 << FE_OPC_VEX_WPP_SHIFT,
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FE_OPC_VEX_MMM_SHIFT = 10,
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FE_OPC_VEX_MMM_MASK = 0x1f << FE_OPC_VEX_MMM_SHIFT,
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FE_OPC_VEX_DOWNGRADE_VEX = 1 << 24,
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FE_OPC_VEX_DOWNGRADE_VEX_FLIPW = 1 << 25,
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};
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static int
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enc_vex_common(uint8_t* buf, unsigned opcode, unsigned base,
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unsigned idx, unsigned reg, unsigned vvvv) {
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if ((base | idx | reg | vvvv) & 0x10) return 0;
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bool vex3 = ((base | idx) & 0x08) || (opcode & 0xfc00) != 0x0400;
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if (vex3) {
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*buf++ = 0xc4;
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unsigned b1 = (opcode & FE_OPC_VEX_MMM_MASK) >> FE_OPC_VEX_MMM_SHIFT;
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if (!(reg & 0x08)) b1 |= 0x80;
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if (!(idx & 0x08)) b1 |= 0x40;
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if (!(base & 0x08)) b1 |= 0x20;
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*buf++ = b1;
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unsigned b2 = (opcode & FE_OPC_VEX_WPP_MASK) >> FE_OPC_VEX_WPP_SHIFT;
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if (opcode & 0x20) b2 |= 0x04;
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b2 |= (vvvv ^ 0xf) << 3;
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*buf++ = b2;
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} else {
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*buf++ = 0xc5;
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unsigned b2 = opcode >> FE_OPC_VEX_WPP_SHIFT & 3;
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if (opcode & 0x20) b2 |= 0x04;
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if (!(reg & 0x08)) b2 |= 0x80;
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b2 |= (vvvv ^ 0xf) << 3;
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*buf++ = b2;
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}
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*buf++ = (opcode & 0xff0000) >> 16;
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return 3 + vex3;
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}
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static int
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enc_vex_reg(uint8_t* buf, unsigned opcode, uint64_t rm, uint64_t reg,
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uint64_t vvvv) {
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unsigned off = enc_vex_common(buf, opcode, rm, 0, reg, vvvv);
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buf[off] = 0xc0 | (reg << 3 & 0x38) | (rm & 7);
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return off ? off + 1 : 0;
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}
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static int
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enc_vex_mem(uint8_t* buf, unsigned opcode, FeMem rm, uint64_t reg,
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uint64_t vvvv, unsigned ripoff, bool forcesib, unsigned disp8scale) {
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unsigned off = enc_vex_common(buf, opcode, op_reg_idx(rm.base), op_reg_idx(rm.idx), reg, vvvv);
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unsigned memoff = enc_mem(buf + off, ripoff + off, rm, reg, forcesib, disp8scale);
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return off && memoff ? memoff : 0;
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}
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static int
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enc_vex_vsib(uint8_t* buf, unsigned opcode, FeMemV rm, uint64_t reg,
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uint64_t vvvv, unsigned ripoff, bool forcesib, unsigned disp8scale) {
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unsigned off = enc_vex_common(buf, opcode, op_reg_idx(rm.base), op_reg_idx(rm.idx), reg, vvvv);
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unsigned memoff = enc_mem_vsib(buf + off, ripoff + off, rm, reg, forcesib, disp8scale);
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return off && memoff ? memoff : 0;
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}
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static int
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enc_evex_common(uint8_t* buf, unsigned opcode, unsigned base,
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unsigned idx, unsigned reg, unsigned vvvv) {
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*buf++ = 0x62;
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bool evexr3 = reg & 0x08;
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bool evexr4 = reg & 0x10;
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bool evexb3 = base & 0x08;
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bool evexb4 = base & 0x10; // evexb4 is unused in AVX-512 encoding
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bool evexx3 = idx & 0x08;
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bool evexx4 = idx & 0x10;
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bool evexv4 = vvvv & 0x10;
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unsigned b1 = (opcode & FE_OPC_VEX_MMM_MASK) >> FE_OPC_VEX_MMM_SHIFT;
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if (!evexr3) b1 |= 0x80;
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if (!evexx3) b1 |= 0x40;
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if (!evexb3) b1 |= 0x20;
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if (!evexr4) b1 |= 0x10;
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if (evexb4) b1 |= 0x08;
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*buf++ = b1;
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unsigned b2 = (opcode & FE_OPC_VEX_WPP_MASK) >> FE_OPC_VEX_WPP_SHIFT;
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if (!evexx4) b2 |= 0x04;
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b2 |= (~vvvv & 0xf) << 3;
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*buf++ = b2;
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unsigned b3 = opcode & 0xff;
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if (!evexv4) b3 |= 0x08;
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*buf++ = b3;
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*buf++ = (opcode & 0xff0000) >> 16;
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return 5;
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}
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static unsigned
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enc_evex_to_vex(unsigned opcode) {
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return opcode & FE_OPC_VEX_DOWNGRADE_VEX_FLIPW ? opcode ^ 0x8000 : opcode;
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}
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// Encode AVX-512 EVEX r/m-reg, non-xmm reg, vvvv, prefer vex
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static int
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enc_evex_reg(uint8_t* buf, unsigned opcode, unsigned rm,
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unsigned reg, unsigned vvvv) {
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unsigned off;
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if (!((rm | reg | vvvv) & 0x10) && (opcode & FE_OPC_VEX_DOWNGRADE_VEX))
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off = enc_vex_common(buf, enc_evex_to_vex(opcode), rm, 0, reg, vvvv);
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else
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off = enc_evex_common(buf, opcode, rm, 0, reg, vvvv);
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buf[off] = 0xc0 | (reg << 3 & 0x38) | (rm & 7);
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return off + 1;
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}
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// Encode AVX-512 EVEX r/m-reg, xmm reg, vvvv, prefer vex
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static int
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enc_evex_xmm(uint8_t* buf, unsigned opcode, unsigned rm,
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unsigned reg, unsigned vvvv) {
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unsigned off;
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if (!((rm | reg | vvvv) & 0x10) && (opcode & FE_OPC_VEX_DOWNGRADE_VEX))
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off = enc_vex_common(buf, enc_evex_to_vex(opcode), rm, 0, reg, vvvv);
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else
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// AVX-512 XMM reg encoding uses X3 instead of B4.
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off = enc_evex_common(buf, opcode, rm & 0x0f, rm >> 1, reg, vvvv);
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buf[off] = 0xc0 | (reg << 3 & 0x38) | (rm & 7);
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return off + 1;
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}
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static int
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enc_evex_mem(uint8_t* buf, unsigned opcode, FeMem rm, uint64_t reg,
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uint64_t vvvv, unsigned ripoff, bool forcesib, unsigned disp8scale) {
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unsigned off;
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if (!((op_reg_idx(rm.base) | op_reg_idx(rm.idx) | reg | vvvv) & 0x10) &&
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(opcode & FE_OPC_VEX_DOWNGRADE_VEX)) {
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disp8scale = 0; // Only AVX-512 EVEX compresses displacement
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off = enc_vex_common(buf, enc_evex_to_vex(opcode), op_reg_idx(rm.base), op_reg_idx(rm.idx), reg, vvvv);
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} else {
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off = enc_evex_common(buf, opcode, op_reg_idx(rm.base), op_reg_idx(rm.idx), reg, vvvv);
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}
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unsigned memoff = enc_mem(buf + off, ripoff + off, rm, reg, forcesib, disp8scale);
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return off && memoff ? memoff : 0;
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}
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static int
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enc_evex_vsib(uint8_t* buf, unsigned opcode, FeMemV rm, uint64_t reg,
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uint64_t vvvv, unsigned ripoff, bool forcesib, unsigned disp8scale) {
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(void) vvvv;
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// EVEX VSIB requires non-zero mask operand
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if (!(opcode & 0x7)) return 0;
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// EVEX.X4 is encoded in EVEX.V4
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unsigned idx = op_reg_idx(rm.idx);
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unsigned off = enc_evex_common(buf, opcode, op_reg_idx(rm.base), idx & 0x0f, reg, idx & 0x10);
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unsigned memoff = enc_mem_vsib(buf + off, ripoff + off, rm, reg, forcesib, disp8scale);
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return off && memoff ? memoff : 0;
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}
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unsigned fe64_NOP(uint8_t* buf, unsigned flags) {
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unsigned len = flags ? flags : 1;
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// Taken from Intel SDM
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static const uint8_t tbl[] = {
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0x90,
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0x66, 0x90,
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0x0f, 0x1f, 0x00,
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0x0f, 0x1f, 0x40, 0x00,
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0x0f, 0x1f, 0x44, 0x00, 0x00,
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0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00,
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0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00,
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0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00,
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};
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unsigned remain = len;
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for (; remain > 9; remain -= 9)
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for (unsigned i = 0; i < 9; i++)
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*(buf++) = tbl[36 + i];
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const uint8_t* src = tbl + (remain * (remain - 1)) / 2;
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for (unsigned i = 0; i < remain; i++)
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*(buf++) = src[i];
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return len;
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}
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#include <fadec-encode2-private.inc>
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